Interfacing CPU with external word s interfacing signals bus bus Power supply lines a d Typical Bus arbitration Status Bus control Interrupts control Control bus Clock signal Miscellaneous External Buses We classify the CPU interfacing signals in three functional buses: bus bus Control Bus Bus Unidirectional, from processor to outside word. CPU outputs have the possibility to pass in high Impedance (HiZ) state Higher order bits are decoded for selecting block of memories. Three types of obtaining the selecting signals for addressing: Linear addressing (Fully) Decoded addressing Combined addressed 3 4
DECODE AND ADDRESSING LOGIC N Write Read A14 Linear addressing example Bus A13 A1 decoding 1 N bus bus RD 1 Main memory Dispozitiv device Main memory memorie device principală A 11 -A 0 ROM 1 4K D7-D0 A 11 -A 0 A 11 -A 0 A 11 -A 0 ROM 4K D7-D0 RAM 1 4K 4 R/W D7-D4 RAM 4K 4 R/W D3-D0 = RD A14 = RD A14 WR = RD + A14 Bus R / W = WR A1 = WR + A1 = A1 (RD + WR) = A1 RD + A1 WR = A1 RD A1 WR 5 = (A1 + RD) (A1 + WR) 6 (Fully) Decoded addressing Example for bits addresses A 15 A 14 Memory Access Control Decoder to 4 0 1 3 Block 1 selection ( k) Block selection ( k) Block 3 selection ( k) Block 4 selection ( k) A17 Constructing LONGER MEMORY Example: A17 to 4 56 KB with A chips Chip Select A Decoder Bus 0 1 3 Mem. 1 Mem. Mem. 3 Mem. 4 7 Bus
Constructing Wider Memory Bus Chip Select Bus Mem. 1 Mem. D15-D D7-D0 Bi-directional. Usually width d =,, 3, 64. The CPU outputs have the possibility to pass in High Impedance (HiZ) state. Some microprocessors use time multiplexing of data lines for transmit address or control information through these lines. economy of pin terminals in the first part of the first machine cycle, address information, that is validated by an ALE ( Latch Enable) signal. in the first part of the first machine cycle control information memorized and used by a bus controller. 9 10 Control Bus Bus control signals Bi-directional bus composed by a lot of unidirectional lines (inputs or outputs) and some bi-directional lines. We can classify the Control Bus signals in Bus control signals Bus arbitration signals Interrupts control signals Status signals Miscellaneous signals Minimum set: Write - output from CPU. Read - input to CPU. Strobe - output from CPU. - an input to CPU 11 1
Example for synchronization with signal Adr. Bus Example of real signals Bus CPU RD or WR Main Memory type Echivalent Echivalent AS I00+ I IOR IOW MEMW MEMR CLK ADR AS RD Bus (Memory out) T1 T Tw T3 T4 HiZ From CPU (from master) From memory Z0 I06, I0, I0x6 ALE M / IO DT / R DEN MC60x0 MREQ RFSH IOREQ AS UDS LDS WAIT DTACK 13 14 Bus arbitration signals Examples of real signals (bus arbitration) Control (outputs) and synchronization (inputs) signals for administrating the external requests to control the buses. A master device can control all the 3 computer buses is a master device. CPU pass his outputs in HiZ state Minimum types of signals necessary for arbitration are: a Bus Request input (BR) - recognized at the end of current machine cycle a Bus Grant output (BG) type BR Echivalent BG Echivalent I00, I05, I06 minim mode Z0 MC60x0 HOLD BUSRQ HLDA BUSAK BR BG BGACK 15
Interrupts control signals There are control and synchronization signals with external word of CPU. For synchronization with external events there must be two types of signals: - interrupt request (INT, or NMI) - recognized at the end of current instruction cycle. - interrupt acknowledge. INTA (play also the role of a Read signal for reading the vector of interrupt) There are two types of (hardware) interrupt request: - maskable interrupts INT - non-maskable interrupt, NMI Examples of real signals (interrupts) Tip microprocesor Echivalent INT Echivalent INTA I00, I0x6 INTR, NMI Z0 INTA INT NMI IORQ + M1 MC60x0 IPL, IPL1, IPL0 FC, FC1, FC0 17 1 Status signals Miscellaneous signals Usually output signals that indicate the state of a CPU. Can indicate: type of current machine cycle bus controller - control signals information about internal registers used for address computing synchronization information with other bus masters (lock, busy) the state of internal cache (queue) memory memory controller and external cache special signals for external co-processors request for operand transfer (PEREQ / PEACK 6) acceptance of operand transfer busy test (BUSY 06) error information (BERR 6000) Special signals for every microprocessor type External coprocessor control Inputs tested by software Debugging signals Reset - go to a pre-defined state of microprocessor' control and state registers. 19 0
RESET CLOCK signals All microprocessors has a RESET (input) signal Set the contents of microprocessor registers in a prefixed state (general purp. regs, PC, configuration regs, etc.) Program counter (PC) is set to a predetermined fixed value (usually to 0) Mascable interrupts are invalidated Reset: Restart microprocessor Power-on Reset C1 X1 quartz X C RLC parallel equivalent quartz circuit X1 X C cuarţ RLC cu serial schemă equivalent echivalentă quartz circuit RLC serie 1