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ADS Ptolemy in AMSD-ADE August 2007

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Contents 1 ADS Ptolemy in AMSD-ADE Introduction... 1-1 Supported Platforms and Required Licenses... 1-3 2 ADS Ptolemy AMS Examples Introduction... 2-1 Example Directory Structure... 2-2 Example Contents... 2-4 WLAN IEEE 802.11a/g EVM Test Example... 2-5 WLAN_802_11ag_IQ... 2-9 WLAN_802_11ag_EVM_IQ... 2-12 WLAN IEEE 802.11a/g BER Test Example... 2-14 WLAN_802_11ag_IQ... 2-18 WLAN_802_11ag_BER_IQ... 2-21 WLAN IEEE 802.11a/g ESG Test Example... 2-23 WLAN_802_11ag_IQ... 2-28 CM_ESG_E4438C_Sink_IQ... 2-31 Using this Example Project in AMSD-ADE... 2-32 Using Pre-Configured AMSD-ADE Top Cellviews and Pre-Imported Library... 2-33 Importing Pre-Configured ADS Ptolemy Models to Different Libraries... 2-36 Modifying Pre-Configured ADS Ptolemy Models... 2-37 References... 2-38 3 Using ADS Ptolemy AMS Models in AMSD-ADE Introduction... 3-1 Importing ADS Ptolemy AMS Models... 3-1 Simulating ADS Ptolemy AMS Models... 3-3 Viewing Simulation Results for ADS Ptolemy AMS Models... 3-3 Setting Random Seed for ADS Ptolemy Models... 3-4 Using Instrument Connectivity... 3-4 Limitations... 3-4 A Creating and Exporting ADS Ptolemy AMS Models Introduction... A-1 Creating ADS Ptolemy Designs for Use in AMSD-ADE... A-1 Before Exporting ADS Ptolemy Designs for Use in AMSD-ADE... A-2 Exporting ADS Ptolemy Designs for Use in AMSD-ADE... A-2 Creating a Results Display for ADS Ptolemy Designs Used in AMSD-ADE... A-3 Index iii

Chapter 1: ADS Ptolemy in AMSD-ADE Introduction This document describes the use of design collateral from the ADS Ptolemy system simulation environment inside of the Cadence Analog Mixed-Signal Simulator running under the Analog Design Environment (AMSD-ADE). Note The export of wireless test benches and system test benches from ADS Ptolemy can be referred to as the export of design collateral the system designer has created in ADS. More formally, design collateral is used to mean the export of intellectual property from one design environment to another. Chapter 2, ADS Ptolemy AMS Examples describes the use of ADS Ptolemy source and sink subcircuits (system test benches) as components for use in Cadence s Analog-Mixed Signal Simulator running under the Analog Design Environment (AMSD-ADE). This feature is similar to the export of Wireless Test Benches from ADS Ptolemy to the RFDE design environment; for details, refer to Wireless Test Bench Basics in the Wireless Test Bench Simulation manual. For details regarding creating and exporting ADS Ptolemy source and sink subcircuits, refer to Appendix A, Creating and Exporting ADS Ptolemy AMS Models. Introduction 1-1

ADS Ptolemy in AMSD-ADE AMSD-ADE is used to implement and simulate analog/mixed-signal/rf ICs. Cadence uses the term SystemIC to refer to a chip (or chipset) that has a combination of two or more of the following technologies: analog, mixed-signal, digital, and RF. The design collateral flow between ADS Ptolemy, AMSD-ADE, and RFDE is shown: AMS HDL import into Ptolemy is planned for a future release of Cadence AMSD-ADE. AMSD-ADE uses a behavioral-level modeling language that is closer to implementation than the high-level models used in ADS Ptolemy. An ADS Ptolemy model is written as C++ whereas an AMSD-ADE model is written in analog and digital HDL. In AMSD-ADE, a designer creates a model of the system, or virtual prototype, that lives through the implementation cycle for use in evaluating desired system performance and functionality. The export of ADS Ptolemy system test benches enables testing the correct functionality and system performance of this virtual prototype. As the implementation evolves in AMSD-ADE, the system function and performance can be continuously verified. Transistor-level design of the baseband portions of a SystemIC is done in AMSD-ADE; RF portions of the design are done in RFDE. The transistor-level block is verified by running system-level test benches on the virtual prototype. In AMSD-ADE, baseband equivalent models are typically used to simulate the RF circuit. The benefit of this is short simulation times but at the cost of accuracy and the need to model RF portions with either table-based behavioral model using Cadence s DCM-RF or by the designer writing a custom Verilog-A model. 1-2 Introduction

Supported Platforms and Required Licenses Supported operating systems and required Cadence releases are listed: Platform Operating System Cadence Releases UNIX HP-UX 11i IC 5.1.41 USR4 and IUS 5.4 Linux Redhat RHEL WS 3.0 IC 5.1.41 USR4 and IUS 5.8 Sun Solaris 8, 9 IC 5.1.41 USR4 and IUS 5.8 To use the content exported from ADS Ptolemy inside of Cadence s AMS in ADE, these licenses are required: ads_datadisplay enables the ADS Data Display to view the data generated during AMS simulation of the Ptolemy exported content. rfde_amsd_int enables ADS Ptolemy content to be cosimulated under Cadence AMS simulator. rfde_environment Cadence s ADE. sim_systime enables integration of ADS Ptolemy menu selections in enables the ADS Ptolemy simulation engine. When running a design under AMSD, licenses for ADS Ptolemy model libraries, instrument connectivity, and A/RF simulator licenses needed to simulate a design under ADS Ptolemy are also required. The mdl_wlan license is required for simulating examples described in Chapter 2, ADS Ptolemy AMS Examples. If this license is not available, it is still possible to export a design from ADS Ptolemy and import it into Cadence; however, simulation cannot be performed. Supported Platforms and Required Licenses 1-3

ADS Ptolemy in AMSD-ADE 1-4 Supported Platforms and Required Licenses

Chapter 2: ADS Ptolemy AMS Examples Introduction ADS Ptolemy AMS Examples demonstrate building, testing, and exporting ADS Ptolemy designs as well as importing and using them in AMSD-ADE (Cadence Analog Mixed Signal Designer integrated into Cadence Analog Design Environment). The examples are built on the ADS WLAN Design Library. The WLAN library features WLAN IEEE 802.11a (and IEEE 802.11g OFDM) signal source, and EVM and BER/PER measurements. To access the example project from an ADS Main window, choose File > Example Project > Tutorial > WLAN_ExportToAMSD_prj. Introduction 2-1

ADS Ptolemy AMS Examples Example Directory Structure Figure 2-1 shows the directory structure of the WLAN_ExportToAMSD_prj example project. Figure 2-1. WLAN_ExportToAMSD_prj Directory Structure To use this project, copy the project to the user s area by using the ADS Copy Project function or another method provided by the operating system. Referring to the structure in Figure 2-1, observe the following comments: adsptolemy This is not a standard ADS project subdirectory. ams This directory is automatically created during the export process. It stores the exported contents. templates This directory stores Data Display Templates. To use the ADS autoplot feature (in either ADS or AMSD-ADE), the contents of this directory must be copied to $HOME/circuit/templates. artist_states This is not a standard ADS project subdirectory. 2-2 Example Directory Structure

adswlan_test This directory stores the states for the example cells (top level) to be used in AMSD-ADE. To use these states, this directory must be copied to Cadence State Save Directory (by default, $HOME/.artist_states). Note For more information about the State Save Directory, refer to Cadence Product Documentation Virtuoso Analog Design Environment User Guide, Environment Setup. cdslibs This is not a standard ADS project subdirectory. This directory stores libraries to be used in AMSD-ADE. adswlanexamplelib This library includes four examples cells; these cells were generated by Importing ADS Ptolemy AMS Models. adswlan_test This library includes 3 top-level example cells created in AMSD-ADE. These top-level cells use the design under test (DUT) and other cells from adswlanexamplelib. rflib sic_modules This library includes part of the DUT. This library includes part of the DUT. data This is a standard ADS project subdirectory. This directory stores the datasets generated in ADS simulation. networks This is a standard ADS project subdirectory. This directory stores pre-configured WLAN subnetwork models (to be exported and used in AMSD-ADE) and top-level ADS schematic designs (to test the predefined models). Example Directory Structure 2-3

ADS Ptolemy AMS Examples Example Contents The example project includes pre-configured ADS Ptolemy models, AMSD-ADE top cellviews, saved states for top cellviews, and ADS Data Display templates. The pre-configured ADS Ptolemy models and AMSD-ADE top-level cells are described in below; saved states and data display templates are described in the test example sections. Pre-configured subnetwork models defined in this example project are: WLAN_802_11ag_IQ WLAN_802_11ag_EVM_IQ WLAN_802_11ag_BER_IQ CM_ESG_E4438C_Sink_IQ Each pre-configured subnetwork model includes: an ADS subnetwork; file is located under WLAN_ExportToAMSD_prj/networks. an exported ADS Ptolemy design for use in AMSD-ADE; files are located under WLAN_ExportToAMSD_prj/adsptolemy/ams. an imported ADS Ptolemy AMS Model; files are located under WLAN_ExportToAMSD_prj/cdsLibs/adswlanExampleLib as an AMSD-ADE library. Top-level cells (to be used in AMSD-ADE) provided in WLAN_ExportToAMSD_prj/cdsLibs/adswlan_test example project are: WLAN_802_11ag_EVM_test WLAN_802_11ag_BER_test WLAN_802_11ag_ESG_test Each top-level cell uses two pre-configured ADS Ptolemy designs and a DUT. The DUT is located in the rflib and sic_modules libraries under WLAN_ExportToAMSD_prj/cdsLibs. 2-4 Example Directory Structure

WLAN IEEE 802.11a/g EVM Test Example WLAN_802_11ag_EVM_test Features IEEE 802.11a/g configurable signal source, EVM measurement Adjustable data rate TX DUT Description This example tests IEEE 802.11a/g transmit modulation accuracy and transmitter constellation error by measuring the EVM. The AMSD-ADE schematic view of this example is shown in Figure 2-2. Figure 2-2. WLAN_802_11ag_EVM_test Schematic View WLAN_802_11ag_IQ and WLAN_802_11ag_EVM_IQ are imported ADS Ptolemy subnetwork models. BW (BandWidth) and GI (GuardInterval) are design variables. Figure 2-3 shows the Analog Design Environment after loading the saved state for EVM measurement. WLAN IEEE 802.11a/g EVM Test Example 2-5

ADS Ptolemy AMS Examples Figure 2-3. ADE with Saved EVM Measurement State 2-6 WLAN IEEE 802.11a/g EVM Test Example

The signal waveform can be plotted in Wavescan (Figure 2-4) and the EVM measurement can be displayed in ADS Data Display (Figure 2-5). Figure 2-4. I/Q Waveform Before and After DUT WLAN IEEE 802.11a/g EVM Test Example 2-7

ADS Ptolemy AMS Examples Figure 2-5. WLAN_802_11ag_EVM_test EVM Results 2-8 WLAN IEEE 802.11a/g EVM Test Example

WLAN_802_11ag_IQ WLAN_802_11ag_IQ is an imported ADS Ptolemy AMS model. It was created in ADS as subnetwork WLAN_802_11ag_IQ.dsn. Figure 2-6 shows the WLAN_802_11ag_IQ subnetwork design in an ADS DSP schematic. Design parameters for this subnetwork are shown in Figure 2-7. Components used in this subnetwork are described in the following paragraphs. Figure 2-6. ADS Ptolemy Design WLAN_802_11ag_IQ.dsn WLAN IEEE 802.11a/g EVM Test Example 2-9

ADS Ptolemy AMS Examples Figure 2-7. WLAN_802_11ag_IQ Subnetwork Parameters WLAN_802_11a_RF This ADS WLAN Design Library model is the core signal generation model in this subnetwork design. USampleRF This component is used to achieve a high fidelity signal when the native ADS Ptolemy time step is not small enough to satisfy the designer s needs. When OutputUpsample is greater than 1, PolyPhaseFilter will be used for interpolation. As a result, the output signal will be delayed. For more details, refer to USampleRF component documentation. AMS_Interface The ADS Ptolemy AMSD-ADE integration infrastructure requires the AMS_Interface model to be used for every port of the subnetwork design. AMS_Interface has two functions to the user: specify the PortType and specify the TStep. PortType must be correctly set for each of the AMS_interface models. In this subnetwork, Port II and QQ are set to electrical; Port PSDU is set to wreal. Setting of TStep for AMS_interface is optional. TStep needs to be set at only one place in the subnetwork design; in this design, TStep is set in WLAN_802_11a_RF. For more details, refer to AMS_Interface component documentation. TimedSink and ActivatePath TimedSink is used for every port with ActivatePath to collect the data on demand. When CollectData=YES, ActivatePath will enable TimedSink to collect data. Data collected by TimedSink can be used and displayed in the ADS Data Display after simulation. VAR The VAR block contains equations to convert SignalIQrms voltage and NoiseIQrms voltage to signal power and resistor temperature. 2-10 WLAN IEEE 802.11a/g EVM Test Example

RangeCheck This model will check parameter settings and report errors at the beginning of simulation. Currently, RangeCheck is not customizable and works for pre-configured ADS Ptolemy models only. WLAN IEEE 802.11a/g EVM Test Example 2-11

ADS Ptolemy AMS Examples WLAN_802_11ag_EVM_IQ WLAN_802_11ag_EVM_IQ is an imported ADS Ptolemy AMS model. It was created in ADS as subnetwork WLAN_802_11ag_EVM_IQ.dsn. Figure 2-8 shows the WLAN_802_11ag_EVM_IQ subnetwork design in ADS DSP schematic. The design parameters and ADS symbol are shown in Figure 2-9. Figure 2-8. ADS Ptolemy Design WLAN_802_11ag_EVM_IQ.dsn 2-12 WLAN IEEE 802.11a/g EVM Test Example

Figure 2-9. WLAN_802_11ag_EVM_IQ Subnetwork Parameters WLAN_80211a_EVM This ADS WLAN Design Library model is the core signal analysis model in this subnetwork design. AMS_Interface For this design, TStep is set by AMS_Interface A1 (TStep = 12.5 nsec). (For the case that TStep is not set by AMS_Interface, refer to AMS_Interface information in WLAN_802_11ag_IQ on page 2-9.) OutputOption With OutputOption, the specified ADS Data Display Template will be inserted automatically into the ADS Data Display window when the Data Display window is launched in AMSD-ADE. To use this feature, the ADS Data Display Template files (.ddt file) must be copied to $HOME/hpeesof/circuit/templates. Refer to OutputOption component documentation and Data Display Basic: Using a Template in Your Display for more details. TimedSink and ActivatePath TimedSink is used for every port with ActivatePath to collect data on demand. When CollectData=YES, ActivatePath will enable TimedSink to collect data. Data collected by TimedSink can be used and displayed in the ADS Data Display after simulation. RangeCheck This model checks parameter settings and reports errors at start of simulation. Currently, RangeCheck is not customizable and works for pre-configured ADS Ptolemy models only. WLAN IEEE 802.11a/g EVM Test Example 2-13

ADS Ptolemy AMS Examples WLAN IEEE 802.11a/g BER Test Example WLAN_802_11ag_BER_test Features IEEE 802.11a/g configurable signal source, BER measurement Adjustable data rate RX DUT Description This example tests IEEE 802.11a/g BER (Bit Error Rate) and PER (Packet Error Rate). The AMSD-ADE Schematic view of this example is show in Figure 2-10. Figure 2-10. WLAN_802_11ag_BER_test Schematic View WLAN_802_11ag_IQ and WLAN_802_11ag_BER_IQ are imported ADS Ptolemy subnetwork models. DATALEGNTH, BW (BandWidth), DATARATE, IDLE, and GI (GuardInterval) are design variables. Figure 2-11 shows the Analog Design Environment after loading saved state for BER measurement. 2-14 WLAN IEEE 802.11a/g BER Test Example

Figure 2-11. ADE with Saved BER Measurement State The signal waveform can be plotted in Wavescan (Figure 2-12) and the EVM measurement can be displayed in ADS Data Display (Figure 2-13). WLAN IEEE 802.11a/g BER Test Example 2-15

ADS Ptolemy AMS Examples Figure 2-12. I/Q Waveform Before and After DUT 2-16 WLAN IEEE 802.11a/g BER Test Example

Figure 2-13. BER / PER Results WLAN IEEE 802.11a/g BER Test Example 2-17

ADS Ptolemy AMS Examples WLAN_802_11ag_IQ WLAN_802_11ag_IQ is an imported ADS Ptolemy AMS model. It was created in ADS as subnetwork WLAN_802_11ag_IQ.dsn. Figure 2-14 shows the WLAN_802_11ag_IQ subnetwork design in an ADS DSP schematic. Design parameters for this subnetwork are shown in Figure 2-15. Components used in this subnetwork are described in the following paragraphs. Figure 2-14. ADS Ptolemy Design WLAN_802_11ag_IQ.dsn 2-18 WLAN IEEE 802.11a/g BER Test Example

Figure 2-15. WLAN_802_11ag_IQ Subnetwork Parameters WLAN_802_11a_RF This ADS WLAN Design Library model is the core signal generation model in this subnetwork design. USampleRF This component is used to achieve a high fidelity signal when the native ADS Ptolemy time step is not small enough to satisfy the designer s needs. When OutputUpsample is greater than 1, PolyPhaseFilter will be used for interpolation. As a result, the output signal will be delayed. For more details, refer to USampleRF component documentation. AMS_Interface The ADS Ptolemy AMSD-ADE integration infrastructure requires the AMS_Interface model to be used for every port of the subnetwork design. AMS_Interface has two functions to the user: specify PortType and specify TStep. PortType must be correctly set for each of the AMS_interface models. In this subnetwork, Port II and QQ are set to electrical; Port PSDU is set to wreal. Setting of TStep for AMS_interface is optional. TStep needs to be set at only one place in the subnetwork design; in this design, TStep is set in WLAN_802_11a_RF. For more details, refer to AMS_Interface component documentation. TimedSink and ActivatePath TimedSink is used for every port with ActivatePath to collect the data on demand. When CollectData=YES, ActivatePath will enable TimedSink to collect the data. Data collected by TimedSink can be used and displayed in the ADS Data Display after simulation. VAR The VAR block contains the equations to convert SignalIQrms voltage and NoiseIQrms voltage to signal power and resistor temperature. WLAN IEEE 802.11a/g BER Test Example 2-19

ADS Ptolemy AMS Examples RangeCheck This model checks parameter settings and reports errors at the beginning of simulation. Currently, RangeCheck is not customizable and works for pre-configured ADS Ptolemy models only. 2-20 WLAN IEEE 802.11a/g BER Test Example

WLAN_802_11ag_BER_IQ WLAN_802_11ag_BER_IQ is an imported ADS Ptolemy AMS model. It was created in ADS as a subnetwork - WLAN_802_11ag_BER_IQ.dsn. Figure 2-16 shows the WLAN_802_11ag_BER_IQ subnetwork design in ADS DSP schematic. The design parameters and ADS symbol are shown in Figure 2-17. Figure 2-16. ADS Ptolemy Design WLAN_802_11ag_BER_IQ.dsn WLAN IEEE 802.11a/g BER Test Example 2-21

ADS Ptolemy AMS Examples Figure 2-17. WLAN_802_11ag_BER_IQ Subnetwork Parameters WLAN_80211a_RxSoft and WLAN_80211a_BERPER These ADS WLAN Design Library models are the core signal analysis models in this subnetwork design. AMS_Interface, Output Option, TimedSink, ActivatePath, and RangeCheck Refer to corresponding sections of WLAN_802_11ag_IQ on page 2-9 and WLAN_802_11ag_EVM_IQ on page 2-12. 2-22 WLAN IEEE 802.11a/g BER Test Example

WLAN IEEE 802.11a/g ESG Test Example WLAN_802_11ag_ESG_test Features IEEE 802.11a/g configurable signal source Agilent ESG E4438C connectivity TX DUT Description This example downloads an IEEE 802.11a/g signal to Agilent ESG instrument E4438C. The AMSD-ADE Schematic view of this example is shown in Figure 2-18. Figure 2-18. WLAN_802_11ag_BER_test Schematic View WLAN_802_11ag_IQ and WLAN_802_11ag_BER_IQ are imported ADS Ptolemy subnetwork models. DATALEGNTH, BW (BandWidth), DATARATE, IDLE, and GI (GuardInterval) are design variables. Figure 2-19 shows the Analog Design Environment after loading the saved state for ESG test. WLAN IEEE 802.11a/g ESG Test Example 2-23

ADS Ptolemy AMS Examples Figure 2-19. ADE with Saved BER Measurement State The ESG instrument must be configured before any simulation. The instrument connectivity for this product is called Connection Manager (CM). CM supports two different kinds of computers: CM server and CM client. CM server runs on Windows PC only, which talks directly with the instruments; CM client runs on all platforms supported by ADS or RFDE. Note For details regarding Connection Manager, including CM server and CM client, refer to the RFDE Connection Manager documentation. The CM_ESG_E4438C_Sink_IQ in this example uses CM client. 2-24 WLAN IEEE 802.11a/g ESG Test Example

Figure 2-20 shows part of the CM_ESG_E4438C_Sink_IQ property form. The string for the Instrument parameter is used to locate the ESG instrument. Click Select Instrument to access the Instrument Explorer window that will guide you through ESG instrument setup. Figure 2-20. CM_ESG_E4438C_Sink_IQ Parameters After clicking Select Instrument, a Set Server window (Figure 2-21) will pop up to ask for the CM server name and port. Enter the server name or its IP address; in most cases, the server port should be default port 4790. Figure 2-21. CM Server Selection Window WLAN IEEE 802.11a/g ESG Test Example 2-25

ADS Ptolemy AMS Examples When CM is set up, the Remote Instrument Explorer window will list the available instruments. Figure 2-22. Remote Instrument Explorer Select the ESG instrument from the list (you can query the instrument ID to identify the instruments), then click OK to finish the ESG instrument setup. This message will appear in the simulation log window during simulation: WLAN_802_11ag_ESG_test.ESG.ESG_Interface: Scaling IQ data by scaling factor... WLAN_802_11ag_ESG_test.ESG.ESG_Interface: Beginning streaming download of IQ... WLAN_802_11ag_ESG_test.ESG.ESG_Interface: Download 100% complete Figure 2-23 shows the ESG display (LCD on the ESG box) after simulation. It shows that the downloaded waveform (ADS_WAVEFORM) has 8000 sample points and has been loaded and modulated to the RF carrier (2.4 GHz, -20 dbm). Figure 2-23. ESG Waveform Segments Display after Downloading 2-26 WLAN IEEE 802.11a/g ESG Test Example

Note You may need several key strikes on the ESG front panel to get to this Waveform Segments display. For more information about the Agilent ESG instruments, visit http://www.agilent.com/find/esg. If the parameter CollectData is set to YES in CM_ESG_E4438C_Sink_IQ, the downloaded signal will be collected by TimedSink in CM_ESG_E4438C_Sink_IQ. When launching ADS Data Display, simulation results will be displayed as shown in Figure 2-24. Figure 2-24. ESG Downloading Data Display WLAN_802_11ag_ESG_test WLAN IEEE 802.11a/g ESG Test Example 2-27

ADS Ptolemy AMS Examples WLAN_802_11ag_IQ WLAN_802_11ag_IQ is an imported ADS Ptolemy AMS model. It was created in ADS as subnetwork WLAN_802_11ag_IQ.dsn. Figure 2-25 shows the WLAN_802_11ag_IQ subnetwork design in an ADS DSP schematic. Design parameters for this subnetwork are shown in Figure 2-26. Components used in this subnetwork are described in the following paragraphs. Figure 2-25. ADS Ptolemy Design WLAN_802_11ag_IQ.dsn 2-28 WLAN IEEE 802.11a/g ESG Test Example

Figure 2-26. WLAN_802_11ag_IQ Subnetwork Parameters WLAN_802_11a_RF This ADS WLAN Design Library model is the core signal generation model in this subnetwork design. USampleRF This is used to achieve high fidelity signal when the native ADS Ptolemy time step is not small enough to satisfy the designer s needs. When OutputUpsample is greater than 1, PolyPhaseFilter will be used for interpolation. As a result, the output signal will be delayed. Please see USampleRF component documentation for more details. AMS_Interface The ADS Ptolemy AMSD-ADE integration infrastructure requires the AMS_Interface model to be used for every port of the subnetwork design. AMS_Interface has two functions to the user: specify the PortType and specify the TStep. PortType must be correctly set for each of the AMS_interface models. In this subnetwork, Port II and QQ are set to electrical; Port PSDU is set to wreal. Setting TStep for AMS_interface is optional. TStep needs to be set at only one place in the subnetwork design; in this design, TStep is set in WLAN_802_11a_RF. For more details, refer to AMS_Interface component documentation. TimedSink and ActivatePath TimedSink is used for every port with ActivatePath to collect the data on demand. When CollectData=YES, ActivatePath will enable TimedSink to collect the data. Data collected by TimedSink can be used and displayed in the ADS Data Display after simulation. VAR The VAR block contains the equations to convert SignalIQrms voltage and NoiseIQrms voltage to signal power and resistor temperature. WLAN IEEE 802.11a/g ESG Test Example 2-29

CM_ESG_E4438C_Sink_IQ CM_ESG_E4438C_Sink_IQ is an imported ADS Ptolemy AMS model. It was created in ADS as a subnetwork - CM_ESG_E4438C_Sink_IQ.dsn. The design parameters and ADS symbol are shown in Figure 2-27. Figure 2-27. WLAN_802_11ag_BER_IQ Subnetwork Parameters WLAN IEEE 802.11a/g ESG Test Example 2-31

ADS Ptolemy AMS Examples Using this Example Project in AMSD-ADE The example project demonstrates the following steps for using ADS Ptolemy designs in AMSD-ADE. ADS Building ADS Ptolemy designs (pre-configured models). Building ADS top-level schematic to test pre-configured models. Exporting pre-configured models. AMSD-ADE Importing pre-configured ADS Ptolemy models Building AMSD-ADE top cellviews, which use imported pre-configured ADS Ptolemy models. All intermediate files are kept during the above steps; therefore, the example project can be used to: Run (or modify and run) the top cellviews then observe the simulation results in both Wavescan and ADS Data Display. Import pre-configured ADS Ptolemy models into different libraries. Modify the pre-configured ADS Ptolemy models, then export the modified models. 2-32 Using this Example Project in AMSD-ADE

Using Pre-Configured AMSD-ADE Top Cellviews and Pre-Imported Library Table 2-1 identifies the libraries defined in WLAN_ExportToAMSD_prj/cdsLibs/cds.lib. Table 2-1. Libraries Defined in WLAN_ExportToAMSD_prj/cdsLibs/cds.lib Library Name Library Location Comments adswlan_test./adswlan_test top cellviews adswlanexamplelib./adswlanexamplelib pre-configured ADS Ptolemy models sic_modules./sic_modules RF DUT veriloga rflib./rflib RF DUT schematic To set up the pre-configured cellviews and libraries: 1. Copy $HPEESOF_DIR/examples/Tutorials/WLAN_ExportToAMSD_prj to local area. 2. Include WLAN_ExportToAMSD_prj/cdsLibs/cds.lib in the cds.lib file, which is used to start RFDE. 3. Copy directory adswlan_test under WLAN_ExportToAMSD_prj/artist_states to Cadence State Save Directory (by default, $HOME/.artist_states) Note For more information about the State Save Directory, refer to Cadence Product Documentation Virtuoso Analog Design Environment User Guide, Environment Setup. 4. Copy files under WLAN_ExportToAMSD_prj/adsptolemy/templates to $HOME/hpeesof/circuit/templates. Using this Example Project in AMSD-ADE 2-33

ADS Ptolemy AMS Examples To open top cellviews and load the save state: 1. Start RFDE 2. In the CIW window, click File > Open to open the Open File form. 3. Select the top cellview you want in adswlan_test library, the View Name should be config. 4. Click OK and another form will open; ensure the Top Cell View is selected, click OK. 5. Access the Analog Design Environment (ADE) window from the Schematic Editing window and select ams as the Simulator. 6. Load the saved state; there is only one saved state for each pre-configured top cellview. You are required to use these pre-configured states to simulate the pre-configured cellviews. For the WLAN_802_11ag_BER_test cellview especially, the corresponding state for this cellview is pre-configured to include a few Verilog compiler directives to be used in one of the veriloga.va files used in the DUT for this cell. 2-34 Using this Example Project in AMSD-ADE

Results can be displayed in both Cadence Wavescan and ADS Data Display. To view the results: 1. Launch ADS Data Display: click Results > ADS Ptolemy > Launch Data Display from the ADS window. 2. The pre-configured ADS Ptolemy models use OutputOption to enable automatic data display template insertion when the ADS display is launched. Using this Example Project in AMSD-ADE 2-35

ADS Ptolemy AMS Examples Importing Pre-Configured ADS Ptolemy Models to Different Libraries The pre-configured ADS Ptolemy Models have been imported to adswlanexamplelib for easy access. The pre-configured top cellviews have demonstrated how to use the adswlanexamplelib library. However, pre-configured ADS Ptolemy models can easily be imported into other libraries to meet different requirements. 1. Start RFDE. 2. Click Tools > Import ADS Ptolemy AMS Models to access this form. for the ADS Project input, Browse to WLAN_ExportToAMSD_prj for AMS Models, select Import all models or an individual model to be imported. for Destination Library, select the library to hold the imported model(s) for AMS View, accept verilogams. 3. Click OK. 4. The model(s) will be imported into the specified library and ready to use. Note The import process will also import (copy) the data display templates (under <xxx>_prj/adsptolemy/templates) to the $HOME/hpeesof/circuit/templates area. Any existing files with the same name will be overwritten. 2-36 Using this Example Project in AMSD-ADE

Modifying Pre-Configured ADS Ptolemy Models Modifying pre-configured ADS Ptolemy models is a good starting point for building customized ADS Ptolemy designs. (Refer to Creating ADS Ptolemy Designs for Use in AMSD-ADE on page A-1 for the basic requirements.) When modifying pre-configured models, adhere to the following guidelines (these guidelines were followed in the pre-configured ADS models). Integer pin (yellow), float pin (blue), baseband timed pin (black), and anytype pin (red) can be connected to AMS_Interface model directly; no other converters are required. Set the simulation time step at one place only. Place ActivatePath and TimedSink for each port to enable easy debugging; ActivatePath should not be activated by default to reduce the dataset size. Use USampleRF with Type=PolyPhaseFilter in the signal source when needed. Use OutputOption. After testing the customized ADS Ptolemy design in ADS, it can be exported for use in AMSD-ADE. Refer to Exporting ADS Ptolemy Designs for Use in AMSD-ADE on page A-2. Every electrical output port will be associated with a transition function during the export process. The default transition time is set to 10% of the time step. This transition function can be changed by manually modifying the generated.vams file under <xxx>_prj/adsptolemy/ams. The shipped example WLAN_802_11ag_IQ_AMS.vams has the following code segment that is related to the transition function: analog begin V(II) <+ transition(real_ii, 0, ADSPtolemy_II_TStep/10); V(QQ) <+ transition(real_qq, 0, ADSPtolemy_QQ_TStep/10); end Note ADSPtolemy_II_TStep and ADSPtolemy_QQ_TStep (in general, ADSPtolemy_<port_name>_TStep) in the above code segment are internal variables. The value of these variables will be set properly during simulation. Changing the initial values or assigning other values to these variables in the.vams file does not take effect. Using this Example Project in AMSD-ADE 2-37

ADS Ptolemy AMS Examples References [1] Cadence Virtuoso Custom Design Platform System/IC Flow Workshop Manual, V1.0. [2] Cadence Product Documentation, Virtuoso Analog Design Environment User Guide, Product Version 5.1.41. 2-38 References

Chapter 3: Using ADS Ptolemy AMS Models in AMSD-ADE Introduction Ptolemy models can be used in AMSD-ADE (Cadence Analog Mixed-Signal Designer integrated into Cadence Analog Design Environment) to perform complex wireless system measurements using wireless test bench models. System designers can create AMS Ptolemy models using ADS. Ptolemy components in an AMSD-ADE schematic will launch ADS simulation and communicate with the AMSD simulator using inter-process communication. The AMSD-ADE schematic can contain any AMS components. The user must set up a tran analysis in AMSD-ADE to control analog simulation. Importing ADS Ptolemy AMS Models System designers can create ADS Ptolemy source and sink models in ADS and export them to AMSD-ADE. SystemIC designers can import these models into AMSD-ADE to perform complex wireless system measurements. For details about creating and exporting WTB models, refer to Appendix A, Creating and Exporting ADS Ptolemy AMS Models. To import the content into AMSD-ADE, SystemIC designers use the Import ADS Ptolemy AMS Models form. Introduction 3-1

Using ADS Ptolemy AMS Models in AMSD-ADE To import ADS Ptolemy AMS models from a project: 1. Launch RFDE (Cadence Design Framework II with RFDE installed) 2. From the Cadence CIW window, select menu item Tools > Import ADS Ptolemy Design as AMS Model to launch a dialog box to import the Ptolemy models. 3. Specify a directory path to ADS Project that contains Ptolemy models created and exported by system designers. Alternatively, click Browse to open the File Browser window. Locate the path to the project containing exported Ptolemy model(s). Click OK or Apply. The selected path appears in the Path Editor s field ADS Project. 4. If there are any Ptolemy AMS models found in the project, the AMS Models list will be updated. Select Import all models to import everything under the project or select an individual model to import. 5. Select the Library to place the Ptolemy content into. Only those libraries that have write permission for the user will be listed. 6. Select the AMS View to place the Ptolemy AMS wrapper content into. By default, the AMS view will be verilogams. 7. Turn ON/OFF Overwrite Symbol View to overwrite on an existing symbol. If one does not exist a new symbol will be created. Users can have their own symbol and/or their own verilogams view. To avoid overwriting the user-created symbol and/or verilogams views, turn off the button to overwrite the symbol and type in a new name for the AMS view, respectively. This is useful if you have a different VerilogAMS representation of the Ptolemy model with the same pin configuration. 3-2 Importing ADS Ptolemy AMS Models

Simulating ADS Ptolemy AMS Models Imported AMS Ptolemy models are just like any other AMS components that can be placed on a schematic. The user must create the corresponding config view. If the user has renamed the AMS view during import for an imported component, the new AMS view name must be selected in the Cadence Hierarchy Editor for including Ptolemy components in the simulation. All digital pins are mapped as wreal ports. They can only be connected to other wreal ports. Viewing Simulation Results for ADS Ptolemy AMS Models Simulation of imported Ptolemy models will produce a dataset under the data directory created under the simulation hierarchy. Users can then use Results > ADS Ptolemy > Launch Data Display to launch ADS Data Display to view the Ptolemy simulation results. If the ADS Ptolemy AMS models were created with OutputOption components (which specify the templates to automatically insert) then the Data Display that pops up will have the listed templates inserted automatically. The dataset results can also be merged with the PSF data created by AMS simulation using Results > ADS Ptolemy>Translate Dataset to PSF. After every simulation, if the Data Display window is already up, the user must manually invoke menu item Results > ADS Ptolemy > Launch Data Display to update the automatically inserted templates in the Data Display. The same is true for the PSF content; after every simulation the user must manually launch Results > ADS Ptolemy > Translate Dataset to PSF to update the PSF content. ADS Ptolemy AMS models can be used in a distributed simulation. Each simulation might generate completely dataset, and could contain completely different set of templates to be inserted in the Data Display. Each simulation will generate a dataset with configurations and data display template information in which to view results. At the end of simulation the dataset is copied under the data directory under the parent simulation project directory. From AMSD-ADE one can launch data display, as mentioned earlier, using Results > ADS Ptolemy > Launch Data Display. If the data directory under the parent simulation project directory contains more than one dataset, the Prompt for Dataset window opens containing the list of datasets generated from a given Analog Design Simulating ADS Ptolemy AMS Models 3-3

Using ADS Ptolemy AMS Models in AMSD-ADE Environment session; datasets in the list include the results of distributed and individual simulations. Select a dataset to use for automatic plotting, and click OK. The selected dataset will contain the data display template names that must be used for automatic plotting. Each different dataset selection will update the final automatic plot window. Setting Random Seed for ADS Ptolemy Models To control the random seed for random number generators used in imported Ptolemy models, use the menu item on ADE Setup > ADS Ptolemy Variables to launch a dialog box to modify the seed. The modified number is added as a design variable ADSPtolemySeed. You can either modify the design variable directly or use the above-mentioned dialog box. ADSPtolemySeed is used by all random number generators in the Ptolemy simulator, except those components that use their own specific seed parameter. ADSPtolemySeed initializes the random number generation. The same seed value produces the same random results, thereby giving predictable simulation results. To generate repeatable random output from simulation to simulation, use any positive seed value. For the output to be truly random, enter a seed value of 0. Using Instrument Connectivity If the exported ADS Ptolemy AMS model contains a parameter that is of the type Instrument, then the imported model will contain a button to select an instrument. For more details on instrument connectivity, refer to Chapter 4, Using Instrument Connectivity, in the Wireless Test Bench Simulation manual. Limitations ADS Ptolemy content in AMSD-ADE is not supported for use in either remote or distributed simulation. 3-4 Setting Random Seed for ADS Ptolemy Models

Distributed simulation in Cadence AMSD-ADE does not properly set the environment variables (LD_LIBRARY_PATH/SHLIB_PATH) used for loading of shared libraries on a distributed machine. These items are planned for a future release of Cadence AMSD-ADE. Limitations 3-5

Using ADS Ptolemy AMS Models in AMSD-ADE 3-6 Limitations

Appendix A: Creating and Exporting ADS Ptolemy AMS Models Introduction Using ADS Ptolemy, a system designer can create a DSP system design that is available to a SystemIC designer as a source or a measurement model in AMSD-ADE (Cadence Analog Mixed Signal Designer integrated in Cadence Analog Design Environment). A system designer can then make complex signal generation and system measurements available to a SystemIC designer. The SystemIC designer can then validate and verify the SystemIC design or device under test (DUT) in Cadence IC Design Tool or Design Framework II. This appendix describes how to create and export ADS Ptolemy designs to AMSD-ADE. Creating ADS Ptolemy Designs for Use in AMSD-ADE The design must be created in a DSP Schematic window using only DSP components. A/RF cosimulation sub-circuits can be embedded inside the design. Any A/RF components or resistors that are adjacent to the input or output port will have no impact on the SystemIC DUT. Currently, we only support exporting ADS Ptolemy source designs with all output ports and ADS Ptolemy sink designs with all input ports. ADS Ptolemy source design requirements for use in AMSD-ADE are: The ADS Ptolemy design must contain all output ports. The design should generate a timed baseband signal appropriate for stimulating the SystemIC DUT. Ports must be appropriately named, and cannot be VerilogAMS keywords. An AMS_Interface (refer to AMS_Interface documentation) component must be placed adjacent to and connected to the output port of the design. Each port can be exported as an analog (electrical) or a digital (wreal) port. A-1

Creating and Exporting AMS Models ADS Ptolemy sink design requirements for use in AMSD-ADE: The ADS Ptolemy design must contain all input ports. The design reads only timed baseband signals from the SystemIC DUT. Ports must be appropriately named and cannot be VerilogAMS keywords. An AMS_Interface (refer to AMS_Interface documentation) component must be placed adjacent to and connected to the input port of the design Each port can be exported as an analog port (electrical) or a digital port (wreal). Each design can have parameters as required. These parameters will be available for modification in the AMSD-ADE environment. Parameters can be added using the File > Design Parameters in an ADS Schematic window. Before Exporting ADS Ptolemy Designs for Use in AMSD-ADE It is required that you verify the source and sink designs by placing the instance of these designs in another top-level design, and connecting appropriate components and a DF controller. This top-level design must simulate successfully before attempting to export Sink and Source designs to AMSD-ADE. Exporting ADS Ptolemy Designs for Use in AMSD-ADE After creating an ADS Ptolemy design as described in Creating ADS Ptolemy Designs for Use in AMSD-ADE on page A-1, export the design so it can be used in AMSD-ADE. To export the design, save it and select Tools > Export ADS Ptolemy Design >As AMS model to AMSD-ADE in the schematic window containing the design. An Export Status/Error/Warning dialog box appears showing the exporting progress. A temporary design window will open where the design will be instantiated before the export starts. A successful export process generates the files <Design name>_ams.cdf, <Design name>_ams.vams and <Design name>_ams.net. These files are saved with the exported design under the project directory..._prj/adsptolemy/ams. A-2

Creating a Results Display for ADS Ptolemy Designs Used in AMSD-ADE An ADS Ptolemy design may have complex data that the SystemIC designer will not know how to interpret. To help simplify data analysis, the System designer must use the following steps: 1. System designer must perform verification of the design as mentioned earlier to create a dataset in ADS. 2. Open a new DDS window. Add one or more new pages and name them appropriately. 3. Add correct equations/plots/configurations on the new pages. 4. Save this DDS file as a template by choosing File > Save as Template on the DDS window. Select the User category to save the template. 5. The template file is saved under $HOME/hpeesof/circuit/templates. 6. Copy the template file to _prj/adsptolemy/templates. 7. Place an OutputOption controller in the design s schematic window. (The OutputOption component can be placed at any level of hierarchy in the design.) 8. Add the data display template name, created above, to the list of names. More than one data display template is allowed for a given design. 9. Re-export the design. Now, when this design is used in an AMSD-ADE simulation, the templates listed in the OutputOption controller will be inserted in the DDS window that users can launch via Results>ADS Ptolemy>Launch Data Display menu item. A-3

Creating and Exporting AMS Models A-4

Index A AMSD-ADE, 1-1 D description, feature, 1-1 design collateral, 1-1 distributed, 3-4 F feature, 1-1 S simulation remote, 3-4 system test benches, 1-1 SystemIC, 1-2 V virtual prototype, 1-2 Index-1

Index-2