9-82; Rev 2; 5/ Evaluation Kit General Description The evaluation kit (EV kit) is a fully assembled and tested circuit board that contains all the components necessary for evaluating the. The is a dual,0-bit, 00Msps digital-to-analog converter (DAC) with x/2x/x-configurable interpolation filters. The also features a phase-locked-loop (PLL) clock multiplier that generates and distributes all internally synchronized high-speed clock signals required by the input data latches, interpolation filters, and DAC cores. The EV kit requires CMOS-compatible data and clock inputs, and three separate V power supplies. The EV kit can also evaluate the MAX5858 (no PLL) and the 8-bit MAX585A (with PLL). DESIGNATION QTY DESCRIPTION C, C2, C9, C0, C5, C C, C, C, C2, C7, C8 C5, C22, C2, C25, C28 5 C, C7, C8, C9 C, C 2 C2, C2 2 0µF ±20%,.V tantalum capacitors (20) Panasonic ECS-T0JY0R AVX TAJA0M00RNJ µf ±0%, 0V X5R ceramic capacitors (00) TDK C08X5RA05K 0.µF ±0%, 25V X7R ceramic capacitors (00) TDK C08X7RE0K 0.µF ±0%,.V X5R ceramic capacitors (020) TDK C00X5R0J0K 0.µF ±0%, 0V X5R ceramic capacitors (002) TDK C005X5RA0K 5pF ±0.25pF, 50V C0G ceramic capacitors (00) TDK C08C0GH050C Features Allows Fast Evaluation and Performance Testing V and 2V CMOS Logic-Level-Compatible Inputs Also Evaluates MAX5858/MAX585A (with IC Replacement) Configurable, Integrated x or 2x Interpolation Filters Interleaved Data Mode On-Board Differential to Single-Ended Output Conversion Circuitry SMA Coaxial Connectors for Clock Inputs and DAC Outputs Proven PCB Layout Fully Assembled and Tested PART EVKIT Ordering Information TYPE EV Kit Component List DESIGNATION QTY DESCRIPTION C29 CLK, CLKIN, CLKOUT, OUTA, OUTB 00pF ±0%, 50V C0G ceramic capacitor (00) TDK C08C0GH0K 5 Edge-mount SMA connectors J 2 x 2-pin header JU JU 2-pin headers L, L2, L 9Ω at 00M H z fer r i te b ead s ( 80) Panasonic EXC-ML5A90H R, R 0 Not installed, resistors (00) R2, R, R, R27 kω ±5% resistors (00) R5, R, R8 R2, R2 7 9.9Ω ± resistors (00) R7, R22 2 00Ω ± resistors (00) R2, R25 2 2.9Ω ± resistors (00) R2, R29, R0 0kΩ ±5% resistors (00) R28.2kΩ ± resistor (00) R.9kΩ ± resistor (0805) Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at -888-29-2, or visit Maxim s website at www.maxim-ic.com.
DESIGNATION QTY DESCRIPTION T, T, T5, T T2, T 2 U Transformers Mini-Circuits ADTL-2+ Transformers Mini-Circuits ADTT-+ 0-bit DAC (8 TQFP EP) Maxim ECM Component Suppliers SUPPLIER PHONE WEBSITE AVX Corporation 8-9-028 www.avxcorp.com Mini-Circuits 78-9-500 www.minicircuits.com Panasonic Corp. 800--22 www.panasonic.com TDK Corp. 87-80-00 www.component.tdk.com Texas Instruments Inc. 972--5580 www.ti.com Note: Indicate that you are using the when contacting these component suppliers. Quick Start (PLL Disabled) Note: To evaluate PLL-enabled mode, see the Quick Start (PLL Enabled) section. Recommended Equipment EV kit DC power supplies: Digital V, 500mA Analog V, 00mA Clock V, 200mA Two RF signal generators with low phase noise and low jitter for the clock input (e.g., HP 82A) Data generator (e.g., Sony/Tektronix DG2020A) Two variable output PODs (e.g., Sony/Tektronix P20) Spectrum analyzer Oscilloscope Digital voltmeter Procedure The EV kit is a fully assembled and tested surface-mount board. Follow the steps below for board operation. Component List (continued) DESIGNATION QTY DESCRIPTION U2 Quadruple bus buffer gate with three-state outputs ( TS S O P - P W ) Texas Instruments SN7ALVC25PWR None Shunts (JU, JU0, JU any one pin), (JU2 JU9 pins -2) None PCB: EVALUATION KIT Caution: Do not turn on power supplies or enable signal generators until all connections are completed (Figure ). ) Verify that a shunt is not installed on jumper JU (the CLKIN SMA connector on the EV kit is not used for evaluating the in PLL disabled mode). 2) Verify that a shunt is installed on jumper JU2 (no DC offset at single-ended analog outputs OUTA and OUTB). ) Verify that a shunt is installed on jumper JU (IDE disabled). ) Verify that a shunt is installed on jumper JU (PLL disabled). 5) Verify that a shunt is installed on jumper JU5 (REN enabled, internal reference enabled). ) Verify that shunts are installed on jumpers JU JU9 (single-ended output mode). 7) Verify that no shunts are installed on jumpers JU0 and JU. (CLKXP and CLKXN are used for evaluating the in PLL disabled mode). 8) Connect the RF OUTPUT of the master HP 82A (data clock) to the clock input on the back side of 2
INT* EXT* MASTER HP 82A SLAVE HP 82A the data generator (Sony/Tektronix DG2020A). (See Figure for the equipment setup connections.) 9) Connect the RF OUTPUT of slave HP 82A (EV kit clock) to the CLKD SMA connector on the EV kit. 0) Synchronize master HP 82A to the slave HP 82A on the back side by connecting the INT of the master to the EXT of the slave generator. ) Verify that the data generator is programmed for CMOS-level outputs, which transition from 0 to V. 2) Connect data generator POD A to the first variable output POD (). Connect output channels CH9 VARIABLE POD EV KIT RF OUTPUT RF OUTPUT through CH0 of variable output POD to the EV kit connector J, as indicated in Table. ) Connect data generator POD B to the second variable output POD (2). Connect output channels CH9 through CH0 of the variable output POD 2 to EV kit connector J, as indicated in Table 2. ) Connect the spectrum analyzer to the OUTA or the OUTB SMA connector. 5) Connect the V, 500mA power supply to. Connect the ground terminal of this supply to. ) Connect the V, 00mA power supply to AVDD. Connect the ground terminal of this supply to. 7) Connect the V, 200mA power supply to PVDD. Connect the ground terminal of this supply to. 8) Turn on all three power supplies. 9) With a voltmeter, verify that.2v is measured at the REFO pad on the EV kit. 20) Enable the signal generators and the data generator. Set both HP 82As for an output amplitude of 2V P-P and identical frequencies (f CLK ) of 5MHz. 2) Adjust the phase of the master HP 82A RF source, to meet the data timing specifications. 22) Use the spectrum analyzer to view the output spectrum, or view the output waveforms using an oscilloscope on the outputs. CH9 CH8 CH7 CH CH5 CH CH CH2 CH CH0 DA9/PD CLKD VARIABLE OUTPUT POD 2 VARIABLE OUTPUT POD DG2020A POD A* POD B* CLOCK INPUT* EV KIT DA8/ DACEN 0 (DA0 DA9) (DB0 DB9, CW) *THESE CONNECTORS ARE LOCATED ON THE BACK SIDE OF THE EQUIPMENT. Figure. Quick Start Setup for PLL Disabled Mode Table. Connector J J DA7/ F2EN DA/ FEN DA5/G DA/G2 DA/G DA2/G0 DA DA0 J- J-9 J-7 J-5 J- J- J-29 J-27 J-25 J-2 Table 2. Connector J VARIABLE POD 2 EV KIT CH CH9 CH8 CH7 CH CH5 CH CH CH2 CH CH0 CW DB9 DB8 DB7 DB DB5 DB DB DB2 DB DB0 J- J-2 J-9 J-7 J-5 J- J- J-9 J-7 J-5 J-
Detailed Description of Hardware The EV kit is designed to simplify the evaluation of the 0-bit, dual, 00Msps DAC with PLL. The board contains all circuitry necessary to evaluate the dynamic performance of this high-speed converter, including circuitry to convert the DAC s differential output into a single-ended output. The EV kit provides PCB connector pads for power supplies AVDDIN, IN, and PVDDIN. SMA connectors are included for clock functions CLKIN, CLK- OUT, CLKD, and DAC outputs OUTA and OUTB connections. The four-layer PCB is a high-speed design that optimizes the dynamic performance of the DAC by separating the analog and digital circuitry, which implements impedance matching for the differential output signal PCB traces. The PCB traces have been designed for 50Ω impedance. Power Supplies The EV kit requires separate analog, digital, and PLL power supplies. Connect a V power supply to the AVD- DIN PCB pad to power the analog portion of the DAC. Connect the second V power supply to the IN PCB pad to power the digital portion of the DAC. Connect the third V power supply to the PVDDIN PCB pad to power the PLL portion of the DAC. Digital Inputs The EV kit provides connector J for the two 0-bit input data buses. Data bits DA[9:2] of channel A share a dual function for data and control word. The control word is latched by the CW bit (J-). The control word is latched on the falling edge of CW. Refer to the IC data sheet for a detailed description of the control and data word functions. The data word is latched on the rising edge of the CLK output, pin 20 of the. DAC Output The EV kit is designed to provide two pairs of analog outputs. The outputs can be configured for either differential or single-ended mode of operation. In singleended mode and with transformer-coupled output and 50Ω external termination, the delivers a -2dBm output signal. In differential mode, the output amplitude is VP-P at both positive and negative DAC outputs. To configure the for differential output operation, remove jumpers JU JU9, and measure the outputs at the A+, A-, and B+, B- 2-pin headers. To configure the for single-ended output operation, install shunts on jumpers JU JU9, and measure the outputs at the OUTA and OUTB SMA connectors. Table. DAC Output Mode (Jumpers JU JU9) SHUNT POSITION Installed Not installed DAC OUTPUT MODE Single-ended mode Differential mode ANALOG OUTPUT LOCATIONS OUTA and OUTB SMA connectors A+, A- and B+, B- 2-pin headers Table. Interleaved Data Mode (Jumper JU) SHUNT POSITION Not installed IDE PIN Connected to with R2 INTERLEAVED DATA MODE Enabled Installed Connected to Disabled Table 5. Reference Voltage Option (Jumper JU5) SHUNT POSITION Not installed REN PIN Connected to AVDD with R0 REFERENCE VOLTAGE OPTION External reference Installed Connected to Internal reference Table lists the jumper configuration for the DAC output mode selection. Output DC Offset The EV kit features an option to add a DC offset to the analog output signals. To add a DC offset, remove jumper JU2 and connect an appropriate DC source across jumper JU2. The DC source has to be able to sink at least 0mA of DC current. The DC offset must be within 0 to.25v. Interleaved Data Mode The, MAX5858, and MAX585A feature an interleaved data mode that multiplexes the data inputs of both channels through port A. This feature allows the user to reduce the bit width of the input data bus. In interleaved data mode, channel B data is latched on the falling edge of the clock (CLK), and channel A data is latched on the following rising edge of the clock (CLK). Jumper JU sets the interleaved data mode option. Table lists the jumper selection.
Table. MAX585A Data Bits DA7 Through DA0 on the EV Kit MAX585A EV KIT Table 8. PLL Clock Multiplier (Jumper JU) for and MAX585A CLOCK MODE CLKIN mode CLKD mode DA7/PD DA/ DACEN DA5/ F2EN Table 9. Input Clock Selection JUMPER SETTINGS or MAX585A PLL enabled; JU, JU0, and JU installed; JU not installed DA/ FEN MAX5858 or, or MAX585A PLL disabled; JU, JU0, and JU not installed; JU installed Reference Voltage Options The EV kit supports both internal and external reference configurations. The internal reference voltage can be accessed at the REFO pad. The EV kit also accepts an external reference voltage at the REFO pad to set the full-scale analog-output signal level. Jumper JU5 selects the reference voltage options for the EV kit. Table 5 lists the jumper selection. Evaluating the MAX5858 The EV kit also evaluates the pin-compatible MAX5858. Refer to the MAX5858 IC data sheet for more details on the MAX5858 functions. To evaluate the MAX5858, replace U with the MAX5858 and install a shunt on jumper JU. DA/G DA2/G2 DA/G DA0/G0 SHORT TO SHORT TO J- J-9 J-7 J-5 J- J- J-29 J-27 J-25 J-2 Table 7. MAX585A Data Bits DB7 Through DB0 on the EV Kit MAX585A EV KIT SHUNT POSITION DB7 DB DB5 DB DB DB2 DB DB0 SHORT TO SHORT TO J-2 J-9 J-7 J-5 J- J- J-9 J-7 J-5 J- J- PLLEN PIN PLL CLOCK MULTIPLIER Not installed Connected to PVDD with R29 Enabled Installed Connected to Disabled CW Evaluating the MAX585A The EV kit also evaluates the MAX585A. Refer to the MAX585A IC data sheet for more details on the MAX585A functions. To evaluate the MAX585A, the following component changes on the EV kit are necessary: Replace U with the MAX585A. Install a shunt on J- and J-. Install a shunt on J-5 and J-. Install a shunt on J-2 and J-2. Install a shunt on J-25 and J-2. See Tables and 7 for the data bits of the MAX585A, with respect to header J on the EV kit. PLL Clock Multiplier ( and MAX585A only) The (0 bit) and MAX585A (8 bit) feature a PLL clock multiplier that generates and distributes all internally synchronized high-speed clock signals required by the input data latches, interpolation filters, and DAC cores. Jumper JU sets the PLL clock multiplier options. Table 8 lists the jumper selection. Clock The EV kit features two input clock options: a singleended input clock applied to CLKIN or a differential clock applied to CLKD. When evaluating the or the MAX585A, CLKIN is used in PLL enabled mode, and CLKD is used in PLL disabled mode. The clock signal applied to the CLKIN SMA input connector has to meet CMOS logic-level requirements. When evaluating the MAX5858, only the CLKD SMA input connector is used. Jumpers JU, JU, JU0, and JU set the input clock mode for the. Table 9 lists the jumper configurations. 5
Table 0. Connector J VARIABLE POD MAX585A EV KIT CH9 CH8 CH7 CH CH5 CH CH CH2 CH CH0 DA9/PD DA7/PD DA8/ DACEN DA/ DACEN Table. Connector J VARIABLE POD 2 MAX585A EV KIT DA7/ F2EN DA5/ F2EN DA/ FEN DA/ FEN Quick Start (PLL Enabled) Recommended Equipment DC power supplies: Digital V, 500mA Analog V, 00mA Clock V, 200mA Pulse generator for the clock inputs (e.g., HP 8A) Data generator (e.g., Sony/Tektronix DG2020A) Two variable-output PODs (e.g., Sony/Tektronix P20) Spectrum analyzer Oscilloscope Digital voltmeter Procedure Caution: Do not turn on power supplies or enable signal generators until all connections are completed (Figure 2). ) Verify that a shunt is installed on jumper JU. (CLKIN SMA connector on the EV kit is used for evaluating the in PLL enabled mode). 2) Verify that a shunt is installed on jumper JU2 (no DC offset at the single-ended analog outputs OUTA and OUTB). DA5/G DA/G2 DA/G DA2/G0 DA DA0 DA/G DA2/G2 DA/G DA0/G0 Short to Short to J- J-9 J-7 J-5 J- J- J-29 J-27 J-25 J-2 CH CH9 CH8 CH7 CH CH5 CH CH CH2 CH CH0 CW DB9 DB8 DB7 DB DB5 DB DB DB2 DB DB0 CW DB7 DB DB5 DB DB DB2 DB DB0 Short to Short to J- J-2 J-9 J-7 J-5 J- J- J-9 J-7 J-5 J- ) Verify that a shunt is installed on jumper JU (IDE disabled). ) Verify that a shunt is not installed on jumper JU (PLL enabled). 5) Verify that a shunt is installed on jumper JU5 (REN enabled, internal reference enabled). ) Verify that shunts are installed on jumpers JU JU9 (single-ended output mode). MUST BE ABLE TO ADJUST DELAY BETWEEN TRIG OUTPUT AND OUTPUT HP 8A TRIG OUTPUT OUTPUT CLKIN VARIABLE OUTPUT POD 2 VARIABLE OUTPUT POD DG2020A POD A* POD B* CLOCK INPUT* EV KIT 0 (DA0 DA9) (DB0 DB9, CW) *THESE CONNECTORS ARE LOCATED ON THE BACK SIDE OF THE EQUIPMENT. Figure 2. Quick Start Setup for PLL Enabled Mode J
7) Verify that shunts are installed on jumpers JU0 and JU (CLKXP and CLKXN are not used for evaluating the in PLL enabled mode). 8) Connect the TRIG OUTPUT (clock synchronize signal) of the HP 8A to the clock input on the back side of the data generator (Sony/Tektronix DG2020A). See Figure 2 for the equipment setup connections. 9) Connect the OUTPUT signal of the HP 8A to the CLKIN SMA connector on the EV kit. 0) Verify that both the pulse generator and the data generator are programmed for CMOS level outputs, which transition from 0 to V. ) Connect data generator POD A to the first variable output POD (). Connect output channels CH9 through CH0 of the variable output POD to the EV kit connector J, as indicated in Table 0. 2) Connect data generator POD B to the second variable output POD (2). Connect output channels CH9 through CH0 of the variable output POD 2 to the EV kit connector J, as indicated in Table. ) Connect the spectrum analyzer to the OUTA or the OUTB SMA connector. ) Connect the V, 500mA power supply to. Connect the ground terminal of this supply to. 5) Connect the V, 00mA power supply to AVDD. Connect the ground terminal of this supply to. ) Connect the V, 200mA power supply to PVDD. Connect the ground terminal of this supply to. 7) Turn on all three power supplies. 8) With a voltmeter, verify that.2v is measured at the REFO pad on the EV kit. 9) Enable the pulse generator and the data generator. For x interpolation, set the HP 8A output for a square wave with a frequency (f CLK ) of 5MHz. For 2x interpolation, set the HP 8A output for a square wave with a frequency (f CLK ) of 50MHz. For x interpolation, set the HP 8A output for a square wave with a frequency (f CLK ) of 75MHz. 20) Adjust the delay between the HP 8A TRIG OUT- PUT and signal OUTPUT to meet the data timing specifications. 2) Use the spectrum analyzer to view the output spectrum, or view the output waveforms using an oscilloscope on the outputs. 7
Evaluation Kit 8 Figure. EV Kit Schematic R OPEN CLKD J- J-0 J- J-8 J-22 J-2 J-0 J-2 J-8 J- R27 kω R2 0kΩ R5 9.9Ω R OPEN R2 kω R kω J- J-9 J-5 J-7 J-2 J-25 J-29 J- J-7 J- HEADER 2 2 J J- J-2 J-8 J-20 J-2 J-28 J-2 J-0 J- J-5 J- J-7 J-9 J-2 J-27 J- J-9 J-5 R2 2.9Ω C22 C2 C25 J-2 J- JU J- J- PVDD LOCK REFO JU0 JU R kω R29 0kΩ JU PVDD AVDD AVDD AVDD PVDD CLK CLKIN CLKOUT R0 0kΩ JU5 AVDD R.9Ω JU 8 U2 2 9 5 2 0 7 Y 2Y Y Y VCC 2OE OE OE OE 2A A A A 20 0 2 7 8 8 5 2 0 28 9 8 7 7 9 2 5 8 9 0 2 5 7 22 2 2 25 2 27 2 29 5 OUTPA OUTNA OUTPB OUTNB CLKXP CLKXN LOCK REFO PLLF REFR N.C. N.C. CLK DA9/PD DA8/DACEN DA7/F2EN DA/FEN DA5/G DA/G2 DA/G DA2/G0 DA DA0 DB9 DB8 DB7 DB DB5 DB DB DB2 DB DB0 CW IDE PLLEN REN GND T R25 2.9Ω 2 5 OUTA JU2 T T2 PVDD 2 5 OUTB T5 T T T C2 5pF R 9.9Ω R7 00Ω R8 9.9Ω R9 9.9Ω A+ JU JU7 A- C2 5pF C28 C8 C7 C C C5 C2 0μF.V C μf C μf C 0μF.V R20 9.9Ω R22 00Ω R2 9.9Ω R2 9.9Ω C29 00pF R28.2kΩ B+ JU8 JU9 B- U IN L PVDD C9 C 0μF.V C8 μf C7 μf C5 0μF.V PVDDIN L AVDD C C0 0μF.V C2 μf C μf C9 0μF.V AVDDIN L2 COMMON GROUND POINT
Figure. EV Kit Component Placement Guide Component Side 9
Figure 5. EV Kit PCB Layout Component Side 0
Figure. EV Kit PCB Layout (Inner Layer 2) Ground Planes
Figure 7. EV Kit PCB Layout (Inner Layer ) Power Planes 2
Figure 8. EV Kit PCB Layout Solder Side
Figure 9. EV Kit Component Placement Guide Solder Side
REVISION NUMBER REVISION DATE DESCRIPTION Revision History PAGES CHANGED 0 2/0 Initial release 2/ Corrected terminologies for differential and single-ended modes 2,, 2 5/ Updated capacitor transformers vendor in Component List and Component, 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 20 San Gabriel Drive, Sunnyvale, CA 908 08-77-700 5 20 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.