HPS128-LT-S Hybrid pyroelectric linear array with 128 responsive elements and integrated CMOS multiplexer Description The pyroelectric linear array 128-LT is a hybrid detector with 128 responsive elements and an integrated CMOS multiplexer. The pyroelectric chip consists of lithium tantalate (Li- TaO 3 ). The size of the responsive elements is (9 x ) µm 2 with a pitch of µm (9 x µm² available on request). The multiplexer includes low-noise preamplifiers for each pixel, analogue switches and an output amplifier. The preamplifiers transform the signal charges of each pixel in a signal voltage, realize a band limiting and give the amplified signal to the sample&hold for the read-out process. The digital inputs are CMOS compatible. For the measurement of the detector temperature a sensor (type AD 9) is integrated. It provides a temperature proportional current. The pyroelectric chip and the read-out circuit are arranged in a metal hermetic package with an infrared window. It determines the spectral responsivity. For the measurement of the infrared radiation it is necessary to chop the radiation flux. Features 128 responsive elements arranged in a line Coated germanium or silicon as infrared window Broad band windows or special filters are possible on request NEP (128 Hz) = 7 nw (typical) Dynamic range > 7 db Integrated CMOS multiplexed Good long-term stability Simple mode of operation Operation at ambient temperatures Small package Readout-circuit R DR C S C F i P C P + R TP C TP C A + C H +1 +1 u A Responsive Element Q/-Converter Lowpass Amplifier Sample & Hold Multiplexer 1
Detector geometry and optical specification Package and pins 4. mm 7.9 mm DDD DGND case AD9- AD9+ n.c. AGND OUT 2.4 mm 17.78 mm 32.32 mm 27.32 mm 22.32 mm 4.8 mm 16 16. mm 9 17.78 mm z 1 16 2 1 3 14 4 13 12 6 11 7 8 9 1 8 responsive elements 17.32 mm 22.32 mm 3. mm 16 Pins,.63 Covar gold-plated CLK RES DSS ADD ASS Pins Pin number Pin name Remark 1 CLK Input clock CLK 2 RES Input clock RES 3 Input clock 4 Input clock Input clock 6 DSS Digital operating voltage DSS ( ) 7 ADD Analog operating voltage ADD (+ ) 8 ASS Analog operating voltage ASS ( ) 9 OUT Analog signal output AGND Analog ground 11 n. c. not connected 12 AD9+ Temperature sensor 13 AD9 Temperature sensor 14 case Case 1 DGND Digital ground 16 DDD Digital operating voltage DDD (+ ) Optical Specification Geometry Field of view of each pixel 1 9 Pixel width 9 µm Pitch µm Pixel length µm Distance x 4.71 4.76 4.81 mm Distance y 11.6 11.16 11.26 mm Distance z 1. 1. 1. mm 1 Perpendicular to the array 2
Position of the Pixels Transmission of the germanium window x 1. z.8 Ge* Transmission.6.4 Si* y 12.8 mm.2. 4 8 12 16 2 Wavelength (µm) Electro-optical specification Rectangular chopping with 128 Hz, array temperature 2 C Responsivity S 14 2 /W Noise U N 1. 3 m NEP 7 1 nw MTF (R = 3 lp/mm).4.6 Uniformity 1 S 1 3 % Operating temperature 1 7 C 1 No defective elements Typical responsivity Typical MTF 7 1..8 Responsivity (/W) 6 MTF.6.4 4 Hz 128 Hz.2 Hz 1 2 3 Frequency (Hz). 1 2 3 4 R (lp/mm) 3
Electrical parameters All values for DDD = ADD =, ASS = DSS = ADD, DDD 1 4.7..2 ASS, DSS 1.2. 4.7 Digital inputs Low voltage High voltage Switching threshold Leakage current.7 DDD. DDD.3 DDD DDD ±1 Current consumption I analog 8 ma Current consumption I digital 3 µa AD9 Operating voltage 2 +4 +3 1 ADD and DDD; ASS and DSS must be connect together direct at the detector, 2 See data sheet of Analog Devices Maxiumum/minimum conditions All voltages refer to ground (pin 1) Parameter Maximum/minimum value Unit DDD, ADD.3 to +7 ASS, DSS +.3 to 7 Digital inputs.3 to DDD +.3 CLK, RES,,, Chopping frequency f Ch to 3 Hz AD9+ to AD9 1 2 to +44 Analog output 2 ± ma Maximum irradiance mw/mm 2 Soldering temperature ( s) 3 C Storage temperature 2 to 8 C 1 Potential free to ground (Pin 1), 2 Not short resistent Clock parameters All values for DDD = ADD =, ASS = DSS = Chopping frequency 1 f Ch 128 2 Hz Ground clock 1 CLK f clk 34.3 khz Reset clock high-impulse duration t res 2. 4 µs Clock high-impulse duration t 1 µs Clock high-impulse duration t 2 3 µs Clock low-impulse duration t SH 1 µs Settling time at the output t out 3 µs Setup time before clock t 128SH µs Time distance t SHres µs Time distance t SH µs Time distance t SHfCh µs Time distance t fchres µs Time distance t clkres µs Time distance t resclk 1 µs Time distance t resout 1. t clk + t resclk µs Time distance t DRR µs Time distance t RDR µs 1 t Ch low = t Ch high µa 4
Clock diagram f Ch f clk t SHfCh t fchres RES t clkres t resclk Pixel128 Pixel Pixel1 t res t resout t out t SHres t t 128SH t SH t SH t t DRR t RDR Remark: pixel is an input without responsive element (dark signal) Application remarks Typical clock regime Parameter Relative value Typical value Unit Chopping frequency f Ch 128 Hz Ground clock f clk 1 / t clk 34 34 Hz Reset clock high-impulse duration t res ¼ t clk 7.3 µs Clock high-impulse duration t 3 t clk 29.2 µs Clock high-impulse duration t t clk 292 µs Clock low- impulse duration t SH ½ t clk 14.6 µs Clock diagram Clocknb. 1 2 11 13 131 132 133 f C h f clk RES Pixel Pixel8 Pixel9 Pixel128 Sample Remark: Clock 133 is for the compensation of jitter of the chopping frequency during the mechanical chopping