S.R.M. INSTITUTE OF SCIENCE & TECHNOLOGY SCHOOL OF ELECTRONICS & COMMUNICATION ENGINEERING QUESTION BANK Subject Code : EC307 Subject Name : Microprocessor and Interfacing Year & Sem : III Year, V Sem (ECE) UNIT I PART - A 1. List the components of a computer. Explain the function of each component. 2. What is a Microprocessor? What is the difference between a microprocessor and a CPU? 3. What is the basic difference between microprocessor and microcomputer? 4. What is meant by an 8 bit µp and a 16 bit µp? 5. Define bit, byte, word and instruction. 6. What are low level and high level languages? 7. What is a bus? How is it classified? 8. What is address? 9. Why address bus is unidirectional and data bus is bidirectional? 10. State the relationship between the number of address lines and physical memory space? 11. List the four operations commonly performed by µp unit. 12. Specify the four control signals commonly used by 8085 µp? 13. What is tristate logic? Why is it needed in µp system? 14. What is flag? 15. What is the function of accumulator? 16. List the components of a µp based system. 17. Why interfacing is needed for I/O devices? 18. What is the difference between CPU bus and system bus? 19. What is multiplexing and what is its advantage? 20. How address and data lines are demultiplexed in 8085? 21. List some of the applications of microcomputer system. 22. What are the advantages and disadvantages of µp based system? 23. What is the fabrication technology used for 8085? 24. What is the physical memory space in 8085? 25. What is ALE? 26. What is the function of IO/M* signal? 27. Where is READY signal used? 28. What is HOLD and HLDA and how is it used? 29. What is the use of status lines S1 and S0 in 8085? 30. What is the use of CLKOUT and RESETOUT signals in 8085?
31. What happens to 8085 µp when it is resetted? 32. What are the operations performed by ALU of 8085? 33. Write the organization of registers in 8085 µp? 34. Show the bit positions of various flags in 8085 flag register. 35. Discuss the evolution of microprocessor. 36. How the µp is synchronized with peripherals? 37. What are the hardware interrupts of 8085? How are they prioritized? 38. What are the maskable and unmaskable interrupts of 8085? 39. What are vectored and non vectored interrupts of 8085? 40. Define stack. What is the type of stack in 8085? 41. What is program counter? How is it useful in program execution? 42. What is stack pointer? 43. How µp is synchronized with peripherals? 44. What is minimum system and how is it formed in 8085? 45. What is machine cycle and instruction cycle? 46. What is fetch and execute cycle? 47. List the various machine cycles of 8085. 48. What is the need timing diagram? 49. What is T-state? 50. How many machine cycles constitute one instruction cycle in 8085? 51. Define opcode and operand? 52. What is opcode fetch cycle? 53. What operation is performed during first T-state of every machine cycle? 54. When 8085 µp checks for an interrupt? 55. What is interrupt acknowledge cycle? 56. What is wait state? When 8085 µp will enter wait state? 57. What will be the status of the processor during the bus idle signal? 58. How many instructions are available in 8085? 59. What is the instruction format of 8085? 60. What is addressing? 61. What are the addressing modes available in 8085? 62. How the instruction set is classified in 8085? 63. Which group of instructions affects the flags? 64. What are the arithmetic instructions that do not affect flags? 65. What is DAA? 66. What is DAD? 67. List the various instructions that can be used to clear accumulator. 68. What is the similarity and difference between subtract and compare instruction? 69. What is PSW? 70. What is the difference between CALL and JUMP instructions? 71. What is the difference between conditional and unconditional branching instructions?
72. Compare the following pair of instructions a. MVI A,00 and XRA b. SUB B and AMP B c. JMP 5100 and PCHL d. XTHL and SPHL e. LDA 4500 and LHLD 4500 f. RRC and RAR 73. How many times will the two JNZ instructions be executed in the following sequence? What will be the contents of H and L when program control reaches to HLT instruction? LXI H, 0503 LOOP: DCR L JNZ LOOP DCR H JNZ LOOP HLT 74. Write a note on software delays. 75. What is subroutine? How is it useful? 76. The first four instructions of a typical subroutine are: PUSH PSW PUSH H PUSH B PUSH D What will be the last five instructions of the subroutine? Explain. 77. What are the instructions related to interrupts? What are the functions performed by them? 78. What is primary purpose of 8085 H-L pair with respect to external memory? List two of ots main functions. 79. What is meant by inherent mode of addressing? 80. Identify the addressing modes of the following instructions. a. MOV A,M b. RAR c. STAX D d. LDA 4100 81. What function is performed by each of the following 8085 instructions. a. XOR A b. MOV D,D c. DAD H 82. Assume register pair BC contains 7F0216. For the following 8085 ALP, determine carry, zero, parity and sign flags after execution of the MVI A, 05 instruction. ORG 4100 LXI SP, 2050 PUSH B
MVI A, 02 ADI 03 POP PSW MVI A, 05 HLT PART B 1. List the important features of 8085 µp. 2. Draw the pin diagram of 8085 and explain different signals used by 8085. 3. Draw the functional block diagram of 8085 and explain 4. Discuss briefly the classification of instruction set of 8085 with suitable examples. 5. Explain the various addressing modes of 8085 with examples. 6. Write a short note on machine cycles of 8085. 7. Explain bus idle cycle. 8. Write a neat timing diagram, explain opcode fetch cycle with and without wait state. 9. Write a neat timing diagram, explain Memory Read cycle. 10. Write a neat timing diagram, explain Memory Write cycle. 11. Write a neat timing diagram, explain I/O Read cycle. 12. Write a neat timing diagram, explain I/O Write cycle. 13. Write a neat timing diagram, explain Interrupt acknowledge cycle of 8085 with RST n opcode. 14. Draw the timing diagrams for fetching and execution of the following instructions 15. Using the simplest possible algorithm, Write an 8085 ALP with minimum number of instructions to divide a 16 bit unsigned number in DE by 16. neglect remainder. Store result in DE. 16. Write an 8085 ALP to add 16 bit numbers in BC, DE and HL. Store the 16 bit result in DE. 17. Write an 8085 ALP to add two 32-bit numbers. 18. Write an 8085 ALP to move a block of data of length 10010 from the source block starting at 200016 to the destination block starting at 300016 19. Write a subroutine in 8085 ALP to divide an 8 bit unsigned no Xi by 2. Also write the main program in 8086 assembly language which will call the subroutine to complete 3? Xi/2 i=1 Store the result in location 500 UNIT - II PART A 1. What are the functional parts of 8086? 2. Give the register classification of 8086. 3. What are the general data registers? What are its uses? 4. What is the use of segment register? List it. 5. How the physical address is calculated?
6. What are pointers and index registers? 7. What is meant by memory segmentation? 8. Define overlapped segment area. 9. What is pipelining? 10. Draw the format of 8086 flag registers. 11. How is the stack top address calculated? 12. Differentiate macro & subroutine. 13. What is nested macro? 14. What is meant by procedure? Give its types. 15. What is the function of READ signal? 16. What is the operation performed when Test input is low? 17. What is the purpose of ALE Signal in Minimum mode? 18. What are the pins that are used to indicate the type of transfer in Minimum mode? 19. What is the operation of S0, S1 & S2 pins of Maximum mode? 20. What is the advantage of using segment registers? 21. Define addressing modes. What are its types? 22. Differentiate minimum and maximum mode. 23. How BHE & A0 is used in 8086? 24. What is the use of DEN in minimum mode? 25. What is the use of LOCK in maximum mode? 26. What is the purpose of QS0, QS1 in maximum mode? 27. What will happen when a DMA request is made while the CPU is performing a memory or I/O cycle? 28. What are the parts of flag register? 29. Give the classification of machine control flag? 30. What is segment base? 31. What is bus arbitration logic? 32. What is the purpose of instruction queue? 33. What is instruction pointer? 34. Give the function of status bit S3-S6 during first part of a bus cycle. 35. What is Queue? How Queue is implemented in 8086? 36. How clock signal is generated in 8086? What is the maximum internal clock frequency of 8086? 37. Write the special function carried by the general purpose register of 8086. 38. What is the difference between segment register and general purpose registers? 39. What is the use of status signal S3 & S4? 40. What are control bits? PART B 1. Draw the internal architecture of 8086. Explain each block. 2. Explain the addressing modes of 8086 with example. 3. Explain the control pins used in minimum mode operation. 4. Explain the operation of 8086 when the 8087 processor is connected.
5. Draw the memory read machine cycle in minimum mode and explain the operation in each T state. 6. Draw the memory write machine cycle in minimum mode and explain the operation in each T state. 7. Draw and explain the memory write machine cycle in maximum mode. 8. Draw and explain the memory read machine cycle in maximum mode. 9. Write a program to add 2 16 bit nos. 10. Write a program to multiply and divide the 2 16 bit nos. 11. Explain the following instruction with examples (i) LEA (ii) LAHF (iii) LDS (iv) LES (v) SAHF 12. Explain Shift and Rotate instructions. How it differs from each other? 13. Explain the String instructions used in 8086. 14. Explain the iteration control instruction. In what way it is used in 8086. 15. Explain the external hardware synchronization instruction. 16. Explain the Bit manipulation instruction. 17. Draw the flag format and explain each flag conditions. 18. Explain the register structure in 8086. 19. Write a program to move the string from one memory location to another memory location. UNIT III Part A 1. Define interrupt & polling. 2. Compare and contrast polling & interrupt 3. Discuss the need for interrupt structure in microprocessor? 4. In what way interrupts are classified in 8085? 5. Define a) Hardware interrupts b) Software interrupts 6. What are the hardware interrupts supported in 8085? 7. Name the software interrupts supported in 8085. 8. Which interrupt has the highest priority in 8085? 9. Define a) Maskable interrupts b) Non Maskable interrupts 10. Define a) vectored interrupts b) Non vectored interrupts 11. What is a)interrupt latency b) interrupt response time? 12. Which interrupt is not level sensitive in 8085? 13. Name the level triggering interrupts in 8085. 14. List the interrupt related instructions in 8085. 15. Is there a minimum pulse width required for the INTR signal? If so, specify the duration. 16. How long can the INTR pulse stay high? 17. Can the microprocessor be interrupted again before the completion of the first interrupt service routine? 18. Write a program to enable all the interrupts in an 8085 system. 19. Write a program a. to mask RST 5.5 b. to enable RST 6.5
20. What will happen to the interrupt system in 8085 when the processor is reset? 21. State true or false a. EI instruction is necessary to implement the TRAP interrupt, but external hardware and the SIM instruction are unnecessary. b. Instruction RIM is used to disable the interrupts 7.5, 6.5, 5.5. c. The execution of instructions MVI A,10H and SIM will enable all three RST instructions 22. Specify the function performed by a. SIM b. RIM instructions 23. List out the Restart instructions supported by 8085 and their vectored memory locations. 24. How do you mask INTR interrupt in 8085? 25. Explain the advantage of using PIC 8259A over priority encoder in connecting multiple interrupts with the INTR interrupt line. 26. Write an instruction sequence that will cause the priority of an 8259A whose even address is 8Ah to be IR4, IR5, IR6, IR6, IR7, IR0, IR1, IR2, IR3. 27. Write an instruction sequence that will mask the requests on IR3, IR4 & IR6 of 8259A whose even address is 66H. 28. List out the EOI command supported by 8259A. 29. Write down the appropriate command word data format to program 8259A a. Non specific EOI command b. Specific EOI command. 30. Write down the appropriate command word data format to program 8259A a. Automatic rotation with AEOI=1. b. To turn off the automatic rotation mode 31. Using the I/O mapped scheme, is it possible to address more than 256 i/p devices assuming that the total number of O/P devices is less than 256? 32. How do you program the IMR register in 8259A? 33. List out the different priority modes supported by 8259A. 34. Write down the data format of 8259A output when programmed in polling mode. 35. Explain polling mode of 8259A. 36. What is the difference between fully nested mode and special fully nested mode of 8259A? 37. Explain fully nested mode of 8259A. 38. What is the difference between automatic rotation mode and specific rotation mode? 39. What is the different between special mask mode and masking interrupt using IMR? 40. Calculate the address lines required for addressing a. 8KB memory b. 2 MB memory 41. Calculate the number of memory chips needed to design 1 MB memory if the memory chip size is 1024 X 4. 42. How many memory locations can be addressed by a microprocessor with 14 address lines? 43. Specify the number of memory cells and registers in a 128X4 memory chip.
44. How many bits are stored by a 256X4 memory chip? Can this chip be specified as 128 KB memory? 45. The memory map of a 4K byte memory chip begins at the location 2000H. Specify the address of the last location on the chip and the number of pages in the chip. 46. The memory address of the last location of a 1K byte memory chip is given as FBFFH. Specify the starting address. 47. How many address lines are used to identify an I/O port in the peripheral I/O and in the memory mapped I/O methods? 48. List out the advantages and disadvantages of absolute & linear address decoding. 49. What are interfacing devices? 50. Assume that memory location 2075h has a data byte 47H, specify the contents of the address bus A15- A8 and the multiplexed bus AD7-AD) when microprocessor asserts the RD signal. 51. Explain why the number of output ports in the peripheral mapped I/O is restricted to 256 ports. 52. In the peripheral mapped I/O, can an input port and an output port have the same port address? 53. Specify the 8085 signals that are used to latch data in an output port. 54. Specify the 8085 signals that are used to enable an input port. 55. What are the control signals necessary in the memory mapped I/O? 56. Explain why a latch is used for an output port but a tri state buffer can be used for an input port. 57. What are tri-state devices and why are they necessary in a bus oriented system? 58. If the input to an octal buffer is 4FH and the enable lines 1G and 2G are low, what is the output of the buffer? 59. In a bidirectional buffer, if enable and DIR signal are low, specify the direction of data flow. 60. Specify the output line that goes low if input to 3 to 8 decoder 74LS138 is A7 A6 A5 A4 A3 A2 A1 A0 1 1 1 1 0 1 1 1 61. What is transparent latch? Why is it necessary to use a latch with output devices such as LEDs? 62. Why AD0-AD7 lines are multiplexed? 63. What is the use of ALE signal? PART -B 1. Explain the instructions EI, DI, RST, RIM, SIM and their functions in the 8085 interrupt process. 2. Design and implement the following interrupts a. RST 4 b. RST 2 c. RST 7 3. Explain how to connect multiple interrupts with the INTR line using priority encoder and also list out the disadvantage of using priority encoder. 4. Explain the interrupt structure of 8085 with a neat sketch depicting vectored memory locations and also describe how the 8085 performs interrupt handling. 5. Draw the 8085 timing diagram for a. Interrupt acknowledge machine cycle. b. Execution of RST.
6. Explain the interrupt types available in 8086 with their priority levels and specify the action when an interrupt is executed and also write short notes on software interrupts supported. 7. Draw the functional pin diagram of 8279 and explain the function of different pins. 8. Draw and explain the internal block diagram of 8279. 9. Give the schematic arrangement using 8259A PICs to serve 15 interrupts. 8 interrupts are level triggered and 7 are edge triggered. Use rotating priority and non specific EOI command. Write the initializing program 10. Explain the interfacing of stand alone 8259A with 8085 with a neat sketch. 11. Explain the interfacing of stand alone 8259A with 8086 with a neat sketch. 12. Discuss the data formats of the initialization and operation command words supported by 8259a. 13. List out the sequence of events when one or more interrupt request lines go high in 8259A. and also explain the initialization process of 8259A. 14. Explain the appropriate command words and initialization sequence to program 8259A in the following priority modes a. Fully nested mode b. Polling method c. Specific rotation mode d. Special maskable mode 15. Draw the schematic for master-slave architecture of 8259A interrupt system. 16. Write a program to initialize 8259A to meet the following specifications a. Edge triggered, single b. Mask interrupts IR1 and IR6 c. Interrupt vector address for IR0 is 7280H and call address interval is 4 bytes. 17. Write the initialization instructions for master slave configuration to meet the following specifications. a. The INTR of slave is routed through IR2 of the master 8259A to the 8085. b. Master and slave are both level triggered c. Master vector interrupt address for IR0 is 4260H. d. Slave vector interrupt address for IR0 is 5260H. e. Modes: Automatic rotation and AEOI f. Address of master are 68H and 69H and the slave are 96H and 98H. g. Buffers are not used. 18. a. Define and illustrate absolute and linear address decoding with example. b. What are interfacing devices? Explain any three with neat sketch. 19. Compare and contrast memory mapping and peripheral mapping. 20. Explain the interfacing for 8085 processor using I/O mapping. Assume DIP switches for eight i/p and simple display of binary data with LED. 21. Design an address decoding logic circuit for interfacing 4096 X 8-2732 EPROM with 8085 a. using partial address decoding mode- leave out A13.List the possible address range for the chip. b. Using absolute address decoding mode 22. Design an address decoding logic circuit for interfacing 256 X 8-8155 RAM with 8085 a. Using partial address decoding mode- leave out A14.List the possible address range for the chip. b. Using absolute address decoding mode
UNIT IV PART-A 1. List the operating mode of the 8255 PPI. 2. Write down the internal components for a programmable Interface device? 3. What are handshake signal? Explain its function. 4. Give example for handshake signals and explain them. 5. In a programmable device, how does the MPU differentiate between the control register and status register, if both register have same port address? 6. Give the I/O port addresses of 8255A? 7. Give the features of the mode-0 in 8255A. 8. Give the features of the mode-1 in 8255A. 9. Give the features of the mode-2 in 8255A 10. What are the steps to communicate with the peripherals through 8255A. 11. What is meant by BSR mode. 12. Draw the BSR control word format. 13. What are 6 different modes of 8254. 14. What is the relation between 8254 and 8253 PIT? 15. What is the advantage of 8279 Keyboard hardware approach than the software approach? 16. Briefly write about 8279 programmable keyboard interface. 17. What are initialization commands in 8279? 18. What are most common type of switches? 19. What are the 3 major tasks for getting meaningful data from keyboard? 20. What is DMA controller? 21. What is meant by key bouncing and Debouncing in 8279? PART B 1. Describe about simple I/O strobed I/O and Handshake I/O? 2. Draw the 8255A programmable parallel port and Explain. 3. Explain the 8255A Programming model. 4. What are different modes in 8255A and Explain. 5. Explain the PIT architecture with diagram. 6. Explain the different modes in 8253 PIT. 7. Describe rate generator and square wave generator modes in 8253. 8. Explain initialization of 8254 PIT device. 9. Explain the mode-2 Timed Interrupt generator in 8254 PIT. 10. Briefly explain the software and hardware triggered strobe in 8254 PIT. 11. Explain how DMA controller operates in micro computer system. 12. Explain the modes under which DMA execution has been processed. 13. Explain DMA controller with internal Register Diagram. 14. Draw the logic block diagram of 8279 and Explain. 15. List the major components of 8279 keyboard display Interface and Explain their function.
UNIT - V Part-A 1. What is the input to the stepper motor for rotation in clockwise and anticlockwise direction? 2. What is the use of PORT A in stepper motor? 3. What is ZCD? 4. Draw the flow chart for calibration of equipment in frequency measurement. 5. Write the formulae for finding frequency in frequency measurement system. 6. What do you understand the term temp control. 7. Give the difference between hardware and software system. 8. What is the use of sensor circuit for temp control? 9. Explain the functions of alphanumeric display. 10. What is alphanumeric display? Give two examples. 11. What is GPIB? 12. What is EPROM? 13. Give the types of EPROM. 14. What are the READ cycles parameters for EPROM? 15. What is RS232? 16. Give the voltage levels of RS232. 17. Give two features of RS232. Part-B 1. What is stepper motor? Draw the flow chart of stepper motor control. Write the program for Stepper motor, if the rotation in clock direction and anticlockwise direction. 2. Draw the hardware for frequency measurement and find the time period of an ac wave of unknown frequency. 3. Draw the system hardware for temp control. 4. Draw the flow chart for temp control & explain system software. 5. Write the program for temp control. 6. Explain how LED display in interface with microcomputer. 7. Draw the timing diagram for programming the EPROM. 8. Explain RS-232C to TTL interfacing.