Engineering 1630 Fall 2016 Simulating XC9572XL s on the ENGN1630 CPLD-II Board You will use the Aldec Active-HDL software for the required timing simulation of the XC9572XL CPLD programmable logic chips that you use for the early labs. At your option, you may also do functional simulations before you try to implement the design. The difference between timing and functional simulations is the estimation of delays caused by the gates in the device that implements your design. As such, timing simulation is done only after the circuit itself has been put into your CPLD or FPGA. Timing simulation obviously requires data back from the design tools with the internal layout of the design and with the characteristic delays of the internal gates. This data comes in the form of two files generated by the Xilinx place and route tool. The files are found in the \netgen\fit or \netgen\par directory. They are called <your-project-name>_timesim.v and <your-project-name>_timesim.sdf. (The.v file has the netlist in structural Verilog format while the.sdf file has the timing information in an industry-standard format. Take a look at them in WORDPAD just to see what they look like.) You may also simulate labs B and C that use Xilinx FPGA s. The PROMs and SRAM realized in the Spartan FPGAs simulate in exactly the same way as the CPLD simulations. This handout discusses how to do functional simulations for an entire project that is written just in Verilog modules. It also covers timing simulation whether the source code is strictly Verilog modules or is a mix of a schematic wrapper with Verilog. Incidentally, the Aldec environment offers a way to do design entry of HDL files and block diagrams within the simulator. The procedure is independent of the vendor of the CPLD or FPGA. Frequently companies use several different FPGAs from different vendors for different purposes. Having a single design entry tool that serves for all of them can help simplify the design operations. The Aldec tool has a nicer schematic entry tool than the one included in the Xilinx ISE package and has a tool for GUI entry of state machines based on transition diagrams. I have not set up the software to work that way because it is difficult to get reliable with our system software. To set up a full timing simulation: 1. When you process your Verilog and ucf files to make the programming files for any Xilinx device including CPLDs, be sure you also run the process to Generate Post-Fit Simulation Model. (After you have the programming file ready, go to the Design/Processes pane and expand the Optional Implementation Processes until you see the Generate Post- choice. Run that process by double clicking it.) This makes two files, one with the structure as it fits in the device and one with the timing information. 1
2. Start Aldec s Active HDL by the menu sequence Start/All Programs/Electrical/Active-HDL/Active-HDL 10.2 (32-bit version). Accept the default License Configuration of EDU Mixed Design Entry. On the next screen, choose to create a new workspace. 3. Like many CAD tools, Active-HDL generates a large number of intermediate files and creates a workspace directory for them. The dialog in which you name the project also allows you to set where that directory will be. Please put the workspace folder somewhere convenient in your personal server space on the U:\ drive. (Either U:\ or U:\AldecProjects is a reasonable choice for most people.) 4. The next dialog will give you the choice of how to create a new design. (A design is distinct from a workspace which may contain multiple designs or blocks of Hardware Description Language code.) Choose the radio button to create an empty design. The software next gives a chance to set the design language and target technology. Choose Default HDL and Verilog for the language choices. Since you will simulate structural Verilog with complete timing information, it is not necessary to specify the target device. If you choose to do so, Xilinx and XC9500XL are the appropriate choices. At the next dialog, add a design name; it should be the same as the top-level Verilog.v file name, which will be <Your lab name>_timesim. 5. In Active-HDL go to the menu item Design/Add Files to Design and browse to the source files for the timing simulation that were produced by the Xilinx software in step 4. The files are in a directory called netgen\fit or netgen\par off the Xilinx project directory. The names have the format <your Xilinx project name>_timesim.v and <your Xilinx project name>_timesim.sdf, so you would typically go to a directory with the name U:\XilinxProjects\<your project name>\netgen\fit\... Select both the.v and.sdf files and hit Add. (Depending on how you ran the post-fit processes, these files may be in the netgen\par directory instead.) 6. You now need to connect your simulation to the Libraries with the Verilog models of the primitive blocks from which the Xilinx software builds its structural model. In the Aldec software, go to menu item for the Design/Settings dialog. When that opens go to the Category pane on the left side and click on Compilation and then on Verilog. On the right side pane is an inset with the title Verilog Libraries. Click on the little square symbol at the top right hand corner of that box. This opens an Add Library list box. Select the library simprims_ver and hit OK. 7. Go to the Category pane and select Simulation/Verilog. Repeat the process of adding the same library file to both the Verilog libraries(-pl) and Verilog libraries(-l) boxes. Then make sure the Verilog Optimization check box about halfway down the right side of this Simulation/Verilog dialog IS NOT CHECKED! 2
(A check in that box prevents the input stimulators from working with the standard waveform editor.) Close the Design/Settings dialog. 8. In the Design Browser on the left side of Active-HDL, expand the tree at the name of your <>_timesim.v file. There will be two modules there, one with the same name as your Verilog file and the other called "glbl". The latter is a module that simulates the power on reset condition and the action of certain global signals. Holding down the shift key, click on each of these lines in turn so both are highlighted as being selected. Right click on them and select Set As Top Level. The names will turn to boldface type. 9. Go back up the tree to the.v file name and right click and select Compile. It should run and give you a green check mark on the name. 10. Go again to the menu item for Design/Settings dialog. When that opens select the Simulation/SDF item from the categories pane. The right pane will show the name of the sdf file and the words Average and No. Click on No and change it to Yes. Hit OK. Then go to the instructions for checking simulator settings and then doing the simulation itself. (See sections below the functional setup instructions.) To set up an optional functional simulation: 1. Start Aldec s Active HDL by the menu sequence Start/Electrical/Active- HDL/Active-HDL 10.2 (32-bit version). Accept the default License Configuration of EDU Mixed Design Entry. On the next screen, choose to create a new workspace. 2. Like many CAD tools, Active-HDL generates a large number of intermediate files and creates a workspace directory for them. The dialog in which you name the project also allows you to set where that directory will be. Please put the workspace folder somewhere convenient in your personal server space on the U:\ drive. (U:\AldecProjects is a reasonable choice for most people.) 3. The next dialog will give you the choice of how to create a new design. (A design is distinct from a workspace which may contain multiple designs or blocks of Hardware Description Language code.) Choose the radio button to create an empty design. The software next gives a chance to set the design language and target technology. Choose Default HDL, Verilog, Xilinx, and XC9500XL for the four choices. Next add a design name; it should be the same as the top-level Verilog.v file name. 4. The next step is to add the Verilog file you wrote as the top-level description of the system. From the menu bar of Active-HDL choose Design/Add Files and browse to it in the dialog. Accepting this choice will copy that file to the < your project name >/src directory. That copy is the one that is simulated. You need to 3
remember that this copy is the one that is run by Active-HDL and not the original file in your Xilinx workspace. If you modify your Xilinx design, you will have to copy the new.v file to the src directory. (It is also possible to start your Verilog in an Active-HDL directory and have the program send the file to the Xilinx synthesis and programming tools after simulation. In that case the file in the Aldec source directory is the master file.) 5. If you have multiple Verilog modules in your design, repeat this process to copy and add those to your project or include those files in the initial selections. 6. In the Design Browser window on the left side of the screen, hit the files tab beneath the window to select Files. Expand the design name in this window to reach the Verilog file name. ( Expand in this context means left click on the little + sign to the left of the design name on the file tree to open more entries on the tree.) Right click on file name and choose Compile. If there are multiple such files, choose Compile All. This procedure converts the Verilog to an internal representation suitable for simulation. If necessary fix any errors that are detected. 7. The Verilog files do not specify which signals represent pins with access to the outside world. Instead you must tell Active-HDL which module is the one with external connections. Expand the Verilog file name and select the line labeled just below the file name. Right click on this and choose Set as Top-Level. To check the simulator set up: 1. Before doing either a timing or functional simulation, check that the correct choice of waveform display is set. In the dialog that opens from the Tools/Preferences menu, go into the Category pane on the left and choose Waveform Viewer/Editor. Select Accelerated Waveform Editor in the drop down box on the right. 2. While still in the Tools/Preference/Waveform Viewer/Editor dialog window, expand the Waveform Viewer/Editor tree and left click on Accelerated Waveform Viewer. Continue expanding the tree down through Behavior and Advanced until you can finally check the boxes Preserve signals when the simulation is initialized and AWC save format allows using AWC with any ASDB. 3. Use the menu action: Design/Settings and select the Category/Simulation/Access to Design Objects. To the right of the Category pane is a set of check boxes. Check all of them EXCEPT Limit read access to top-level only. You do not need to enter anything in the text boxes. To run the simulation: 4
1. Before you can run a simulation, you need to set up both a suitable display for the results and a set of input signals to exercise the system. 2. Open a display window by the menu sequence File/New/Waveform. 3. Initialize the simulation by menu action Simulation/Initialize. Then left click on the Structure tab at the bottom of the Design Browser panel. The Browser window has two panes. In the top one, expand the top-level module name to set the top level of the design. In the bottom pane select (left click) a signal and drag it, holding the left mouse button down, onto the timing diagram at the left side of the waveform window. (If you receive a message about needing to have +access +r simply click Simulation/End Simulation followed again by Simulation/Initialize. Usually you include at least all the signals that go to actual pins on your timing diagram. To make your display easier to read, reorder the display so that inputs are at the top and so that related signals that can form buses, e.g., the state bits in lab 5, should be together in descending order. (The order determines the most and least significant bits when a hexadecimal value is given for the whole bus.) It is generally good practice to have clocks at the top, other inputs in the middle and outputs toward the bottom. Within inputs and outputs try to have signal information flow from top to bottom. Thus, in lab 5, state bits should be above display segment lines. (The signal list on the structures tab usually has both individual signals and a single line for the whole bus. The latter is easier to use.) Reordering is done by selecting the signal name in the timing diagram window with the left mouse button and dragging the name to its new position while holding the left button down. Create a bus name where appropriate by selecting all the lines in the bus and then right click on any of the names. Select Merge Signals. Rename the bus by left clicking on the bus name and typing over it. (In lab 5, you would probably want your state bits to be expressed as a bus with hexadecimal labeling.) 4. Sometimes it is necessary to reinitialize the simulator itself to get the waveform editor to recognize the members of a bus. Use the menu sequence Simulation/End Simulation followed immediately by Simulation/Initialize. 5. Often the most difficult part of simulation is setting up input signals. Input signals can be entered either interactively during simulation or with a batch command file. To set up an input in a manual interactive mode, left click on any signal in the waveform window and then right click on that same signal. A menu list opens and you choose Stimulators. This opens a dialog giving you a choice of 6 ways to enter signals, as a clock oscillator, a text function, a specified value, a randomly changing signal, a named file from an earlier entry, or a toggle-by-keystroke ( Hotkey entry) system. The choice of entry method is yours, but I recommend starting with just the clock and function modes. 5
For example, select your clock line and right click to open the Stimulators dialog. Choose the clock generator by left clicking on the clock face. You set the initial delay time, the period and the duty cycle with a combination of mouse drag and typing. Set the clock startup delay to 120 ns. (You need this delay to last past the hardware initialization that is built into the model.) Then set your period in the text box and drag the rising edge of the waveform to your duty cycle. (To change duty cycle, use the mouse to drag the rising edge of the clock waveform.) Finally check the box to the left of the signal name in the dialog box. 6. Pick another signal that requires a more irregular input, and it will be added to the list in the Stimulators dialog. Select the function entry mode by clicking on the f t symbol in the mode list. The entry panel opens two small edit boxes, one for an initial value and the other in which to type a series of value and time pairs. The syntax is very simple: a value, a <space>, and a time with the usual suffixes for units (ns, us, etc.) followed by a comma to separate the next pair. The value for a single bit is 0 or 1 and for a bus the syntax is <base>#<value>. (For example, 16#2a91 specifies a 16-bit hexadecimal number equivalent to the binary 2#0010101010010001.) If you omit the units on time, the default units are picoseconds. This entry mode is a good one for signals like the HALT line in Lab 5 that do not necessarily change on clock edges. 7. Repeat these procedures or experiment with others until all inputs are defined. You can run the simulation to see how the system is evolving and edit entries to fix problems as the simulation proceeds. For example, it may be useful to define only part of the input pattern, run the simulation, look at the results, and add onto the signals. You can also stop, edit the signals, reset the simulation to zero, and rerun to fix mistakes. 8. To make an actual simulation run, close the Stimulators window and do the menu sequence of Simulation/Initialize Simulation. Then go to the top menu bar with the mouse where there is a box with a time entered in it. Change the time to the length that you want the simulation to run and start the simulation by hitting the right-arrow button to the left of the box. (You can also set this to do a partial run and edit in further stimulus waveforms before continuing the run. This is particularly useful for the Value entry mode for waveforms.) See Note 1 below for a common problem with the sdf file. 9. When the simulation has run, you should use the mouse and zoom commands to set up clear timing diagrams for your write-up. Add time marker lines if needed. Print the timing diagrams from the File/Print menu onto one of the printers in the Hewlett Computing Facility. One small caveat: before printing or doing print preview, use Page Setup either from the File menu or the button on the tool bar to set the paper type to letter size. If the size is A4, a metric size that is not normally in the printer, printing with that selection may lock up the printer queue waiting for you to put paper in the #1 paper tray 6
10. When you want to stop work, you are given the chance to save your waveform data to a file as you exit from the waveform window. Should you want to return to the same problem, you can reopen this file, edit the waveforms or Verilog files, and rerun the simulation. NOTES: 1. There is a known problem with the link between the Aldec software and the.sdf file generated by the Xilinx package. The structural Verilog timing simulation file, <your_project_name>_timesim.v contains an initialization line that tells the simulator where to find the sdf file. It overrides the source location you specify in loading the design files into the simulator. If you receive the error message Unable to load the SDF file, then open the < >timesim.v file with WORDPAD or by double clicking on the file name in the Files list. Search down for the line that begins: initial $sdf_annotate(". Replace the argument of the annotation function with the appropriate full path and filename. If the.sdf file is copied to the src directory of the Aldec working files, then use the path and filename for that, for example, initial $sdf_annotate("u:\aldec_projects\lab5_v3_timesim\lab5_v3_timesim\src\lab5_v 3_timesim.sdf");. If the sdf file has not been copied, then you use the path and file name in the Xilinx folder. For example, in one of my files the line produced by the Xilinx ISE software was: initial $sdf_annotate("netgen/par/pov_timesim.sdf"); That line should have been: initial $sdf_annotate("u:\xilinxprojects\pov2012\netgen/par/pov_timesim.sdf"); 2. Should you wish to do functional simulation before you build your Xilinx files, you will need to initialize the flip-flops and registers in your design. That is done with an initial block of code in your Verilog file. It has no effect on your hardware, is ignored in synthesis and cannot be counted on if the initial condition is critical to the operation. The block has the form: initial begin current_state = 6 b000000; end 3. For many purposes it is better to enter the input signals using a macro text file. You write the file in any convenient text editor and give it the extension.do. The on-line help for Aldec gives the syntax of the various commands one might include in such a file. These commands include: Force a value on a signal Set a breakpoint Define a clock Release a forced signal Run to breakpoint or run for a specific time 7
To execute a macro file, you execute a series of menu commands: Menu action: Simulation/End Simulation Menu action: Waveform/Clear Waveforms Menu action: Simulation/Start Simulation Menu action: Tools/Execute macro The following lines are some excerpts from a macro file, showing some of the available commands. # Comments start with # in first column bsd all // Additional comment: this line deletes all breakpoints force -freeze /fpga2reg_oe_n 1 // This line forces the signal // /fpga2reg_oe_n high. force -freeze /reg_data 16#00 // 16#00 means hexadecimal 0x00 # Next line is a 10 MHz 50 % clock rising edge first force -freeze -r 100.0 ns /reg2fpga_clk 0 0 ns 1 50 ns run 100ns force -freeze /final_clock_back 1 // set signal after 100 ns noforce /reg_data // release, that is, stop forcing the value of // reg_data run 100ns # Set a breakpoint for when /u16/outptc takes on the value 1 bs /u16/outptc value 1 run 500us bsd all // Remove all breakpoints. 8