ME 6405 Introduction to Mechatronics

ME 6405 Introduction to Mechatronics Fall 2006 Instructor: Professor Charles Ume Microchip PIC

Manufacturer Information: Company: Website: http://www.microchip.com Reasons for success: Became the hobbyist's favorite microcontroller. (Also the microcontroller used in the popular Basic Stamps) Many microcontroller variations so developer can choose optimal microcontroller for a project.

3 major categories: 12 bit instruction core 16C5X, 12C5XX, 10F2XX family (33 instructions) (no interrupts) (2 level stack, can only make 2 nested calls) ( 10F2XX smallest microcontroller. 6-pins. 4 pins available for I/0) 14 bit instruction core 16C5XX,16C62X, 16C6X, 16C7X, 16C8X, 16F8X, 12C6XX,16C9XX, 14C000 family (35 instructions) (8 level stack) 16 bit instruction core 18FXX family (75 instructions) (31 level stack) (Only category that can execute a program from external memory and write to program memory)

Variations within a family:

Microchip PIC Samples: Samples can be ordered from Microchip every 3 months per person An order can have 3 each of 5 different micro-controllers

Device Programmer Options: Microchip ICD2 Programmer/Debugger From the makers of the microcontrollers themselves. Updatable firmware, compatible with all current products Cost: $159 Parallax PIC Programmer From the makers of the Basic Stamp PIC 16C58A can be programmed with Basic Stamp Code Cost: $199 Various Hobbyist Programmers: Many schematics for programmers on the net. Some that could be built for $10. (Note: Usually limited to one category or family)

Program Language Options: Assembly Language: Microchip allows free downloads of their assembler and simulator called MPLAB C Language: Microchip (Note:Only works on PIC18FXXX MCU s) Custom Computer Services (CCS) (Note: Probably the best) C2C (Note: Not very good but can also handle Senix SX chips) Various others (including free ones for specific families) Basic: PicBasic

CPU Registers: Microchip PIC microcontrollers have only one CPU register, W. W is one byte. This has the effect of limiting data per instruction to one byte. (Note: Program counter and Condition Code register equivalents are regular registers for Microchip PIC micro-controllers. Stack Pointer is not accessible.) Motorola HC11 microcontrollers have several CPU registers: Accumulator A, Accumulator B, Accumulator D, Index X, Index Y, Program counter PC, Stack Pointer SP, and Condition Code register C.

RISC vs. CISC: Microchip PIC microcontrollers are RISC (Reduced Instruction Set Computer). RISC keeps the number of instructions small so each op-code takes up only 1 byte of storage space. Usually each instruction takes only 1 cycle to execute. Motorola HC11 are CISC ( Complex Instruction Set Computer). These have a large instruction set that can do much more in a single instruction. A single instruction may take many byte of program space and more than 1 cycle to execute.

Memory Organization: Microchip PIC microcontrollers use Harvard Architecture for memory Harvard Architecture separates File Registers ( this includes user data ram and registers) and Program memory address space. (Note: File Registers and Program memory on two separate buses. This enables the CPU to get both an op-code and data in one clock cycle.) Usually Program memory is not addressable meaning user program cannot read or write to Program memory. (Note: EEPROM Data is also kept separate from File Registers and Program memory in Microchip PICs and can be addressed through File registers). Motorola HC11 use Von Neumann Architecture for memory All memory is kept together in one address space.( Note: one bus) All memory can be addressed by program (Note: useful for self changing code) George George W. W. Woodruff School School of of Mechanical Engineering, Georgia Georgia Tech Tech

Interrupt Vectors: Microchip PIC microcontrollers have only one Interrupt Vector for all interrupts. Programmer must determine which interrupt to service within Interrupt Service Routine. Motorola HC11 microcontrollers have an Interrupt Vector for each interrupt source.

Binary, Decimal,Hexadecimal, and ASCII Syntax: Type Syntax Example Decimal D'<digits>' D'100'.<digits>.100 (Note: does not mean 1/10 th ) Hexadecimal H'<hex_digits> H'9f' 0x<hex_digits> 0x9f Binary B'<binary_digits>' B'00111001 ASCII A'<character>' A'C' '<character> 'C

Example PIC16F84: Package and Pin outs MCLR: Master Clear VSS: Ground VDD: 5 Volts RA: Bi-Directional I/O pins RB: Bi-Directional I/O pins (Note: Edge interrupt available on RB pins 4-7. RB0 can also be used as a separate external interrupt. Timer overflow interrupt. Data EEPROM Write Complete interrupt)

Example PIC16F84 Minimum Supporting Circuitry:

Example PIC16F84: Program Memory Space Program execution starts at reset Vector One Interrupt Vector This memory cannot be addressed by user program

Example PIC16F84: File Registers This memory space is further divided into 2 banks Which bank to access is controlled by STATUS register (Bit 5 low = bank 0. Bit 5 high = bank1.) Lower 3 bits of STATUS register is equivalent to the Condition Code register math flags in HC11 PCL contains lower byte of Program counter PCLATH contains upper 5 bits of Program counter (NOTE: Program counter is only 13 bits) 0Ch 4Fh is user ram data

Example PIC16F84: File Registers (continued) TMRO is the timer. Similar to TCNT register in HC11. Option bit 7: RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled (by individual port latch values) bit 6: INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin bit 5: T0CS: TMR0 Clock Source Select bit 1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) bit 4: T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin bit 3: PSA: Prescaler Assignment bit bit 2-0: PS2:PS0: Prescaler Rate Select bits TRISA/B is for direction input (1) /output (0) control. Similar to data direction registers in HC11. FSR and 0x00 used for indirect addressing. Similar to George George W. W. Woodruff School School Index of of Mechanical CPU registers Engineering, HC11. Georgia Georgia Tech Tech

Example PIC16F84: File Registers (continued) INTCON is for interrupt Control bit 7: GIE: Global Interrupt Enable bit 1 = Enables all un-masked interrupts 0 = Disables all interrupts bit 6: EEIE: EE Write Complete Interrupt Enable bit 1 = Enables the EE write complete interrupt 0 = Disables the EE write complete interrupt bit 5: T0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt bit 4: INTE: RB0/INT Interrupt Enable bit 1 = Enables the RB0/INT interrupt 0 = Disables the RB0/INT interrupt bit 3: RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt bit 2: T0IF: TMR0 overflow interrupt flag bit 1 = TMR0 has overflowed (must be cleared in software) 0 = TMR0 did not overflow bit 1: INTF: RB0/INT Interrupt Flag bit 1 = The RB0/INT interrupt occurred 0 = The RB0/INT interrupt did not occur bit 0: RBIF: RB Port Change Interrupt Flag bit 1 = When at least one of the RB7:RB4 pins changed state George George W. W. Woodruff School School of of Mechanical Engineering, Georgia Georgia Tech Tech (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state

Example PIC16F84: EEPROM Data Memory Space Addresses available: 00h 3Fh Access is controlled by EEDATA, EEADR, and EECON1 registers. (NOTE: EECON2 is not active in this PIC) Remember the EEPROM Data memory is separated from Program memory and File Registers.

Example PIC16F84: Instructions

Example PIC16F84: Instructions

Assembly example: When RB4 transitions from low to high, copy TMRO register to user data ram at 0x0C. #define PORTB 0x06 #define TMRO 0x01 #define STATUS 0x03 #define OPTION 0x01 #define TRISB 0x06 #define INTCON 0x0B #define TEMP 0x0C ORG 0x00 GOTO MAIN ; Note for OPTION: OPTION is located at file address 0x81 ; but file instructions only take 0x00 to 0x7F. When file address bank 1 ; is selected, micro-controller automatically adds 0x80 therefore ; 0x81 0x80 = 0x01. Similar for TRISB located at 0x86 ; Start Program at reset vector ; Jump over the Interrupt Service Routine ORG 0x04 ; Interrupt Service routine beginning located at Interrupt Vector MOVF TMRO,0 ; Move timer to W CPU Register MOVWF TEMP ; Move W CPU Register to memory location 0x0C BCF INTCON,0 ; Clear RB change interrupt flag RTFIE ; Return from Interrupt George George W. W. Woodruff School School of of Mechanical Engineering, Georgia Georgia Tech Tech

Assembly example (Continued): When RB4 transitions from low to high, copy TMRO register to user data ram at 0x0C. MAIN LOOP BSF STATUS,5 BSF TRISB,5 MOVLW 0xC0 MOVWF OPTION BCF STATUS,5 MOVLW 0x88 MOVWF INTCON GOTO LOOP END ;Select Bank 1 by setting bit 5 of status register ; Make RB4 an input by setting bit 5 of Tristate B ; move 0xC0 to W CPU register ; Setup the options including RB interrupt configuration ; Select Bank 0 by clearing bit 5 of status register ; move 0x88 to W CPU register ; turn on RB change and Global interrupts also clear flag ; Infinite LOOP

C example (using CCS) for demo board: #include <16F84.h> #use Delay(clock=4000000) #define true 1 #byte PORTB = 0x06 #byte PORTA = 0x05 #int_rb rb_isr(){ delay_ms(10); if(portb & 0x80){ while(portb & 0x80){ PORTA = 0x00; } PORTA = 0x0F; } if(portb & 0x40){ while(portb & 0x40){ PORTA++; PORTA = PORTA & 0x0F; delay_ms(20); } PORTA = 0x0F; } George George W. W. Woodruff School School of of Mechanical Engineering, Georgia Georgia Tech Tech } void main(void){ set_tris_a(0x00); set_tris_a(0xc0); enable_interrupts(global); enable_interrupts(int_rb); PORTA = 0x0F; while(true); }