Power.org, September 2005 IBM PowerPC Enablement Kit: ChipBench-SLD: System Level and Design Tool Suite PowerPC SystemC Models SLD Tools PowerPC, CoreConnect IP Dr. Nagu Dhanwada, Chief System Level Design Solutions Architect, Electronic Design Automation, IBM Systems and Technology Group.
Agenda Context and Introduction ChipBench-System Level Design (SLD) Overview Examples POWER Architecture Evaluation Kit V1.0 Conclusions
System Level Design Tasks Algorithm/Specification Level System Specification and Modeling (UML, Matlab, etc) SystemC Performance Power, Timing, Area Models Design / System Architecture Exploration Level Architecture Implementation Level RTL Handoff Configuration Information Synthesis Scripts, Timing constraints, Floorplan Constraints Early design exploration, Map functions in spec to hardware blocks, Determine IP blocks, Bus architecture, etc Simulation based tools that uses high level IP models Graphical specification and visualization Generation of Configured IP (based on architecture exploration) Generate assembled system automatically Manage system configuration data Synthesis front end for detailed design (RTLdown) Generate Verification environment Early floorplanning, die-size estimation, chip-power estimation and packaging analysis Traditional RTL-GDSII Flow
Context in an SLD Flow Initial Application Specification HW/SW tradeoff, Processor selection, etc Abstract Software Specification Initial HW Architecture Software Refinement Application Code Verification HW Architecture Refinement Refined HW Architecture Architecture SystemC Performance Models, Power, Timing, Area Models ChipBench-SLD SystemC Functional Transaction Level Models ChipBench-SLD Embedded SW Hardware Design RTL GDSII Flow
ChipBench-SLD: Motivation and Goals An environment to allow early analysis of SoCs How early and how quickly? Prior to the existence of any detailed hardware specification Short turnaround time from system specification to analyzing results Accurate enough to allow decisions to be made on: Architecture Components Floorplan (Area + timing) Chip/Die Size and Cost Direct links to implementation (e.g., detailed synthesis, P&R)
ChipBench-System Level Design: Conceptual View SoC System-level Diagram SoC Integration SoC Virtual Design V1 V2 V3 v4 V5 Map Map Top-level Program Core Models Instrumentation Scheduler SoC Verification, Performance & Power w/embedded SW Power Performance Map SoC Floorplan + Die Size C1 C2 C3 C4 GL GL C6 C7 Physical Planning Fast Physical Prototyping V1 V4 V2 V3 SoC RTL design Implementation Early Timing Closure V5 Floorplanning SLD solution incorporates SW development, architectural exploration, and floorplanning in a single integrated environment
ChipBench-SLD Environment: Design and Verification Views HW Design and Development HW Verification Software Design and Development Architecture Specification Architecture and Design Performance, Power Block Diagram Floorplan, Timing SoC Netlist Generation Design (Timing, Power, ) Early Functional Verification (Transaction Level Simulation) Interconnect Verification (TOS) Software Architecture Modification Architectural Changes FP, Core Changes Detailed Netlist IBM/ External Simulators Functional Verification HW/SW Co-simulation (IC-SIM) Accelerated Simulation (AWAN) Design Implementation Design Release
ChipBench-SLD: CoreConnect SystemC TLM Simulation Platform SoC Virtual Design HSMC PLB Map DCR Arbiter DCR Bus PPC PLL MAL SoC System-level Diagram dcr_arbiter_if PLB Master dcr_bus_if PLB Master intrpt_ctr_if UIC intrpt_req_if Simulate real application software interacting with IP core models Simulation performance to run a significant software application plb_bus_if PLB_OPB Bridge OPB Slave dcr_slave_if Verify that system supports enough bandwidth and concurrency for target applications Transactions modeled as occurring over communication channels plb_arbiter_if PLB Bus plb_slave_if OPB_PLB Bridge OPB Bus opb_slave_if OPB Master Computation (inside a core) may not be modeled on a cycle-by-cycle basis, as long as input-output delays are cycle-approximate PLB Arbiter PLB Slave OPB Arbiter opb_arbiter_if opb_bus_if Software-based Instruction Set Simulator (ISS) is used for the CPU,
SystemC Modeling of IBM s CoreConnect Architecture ISS + SystemC Wrapper ICU plb_mp1 DCU plb_mp2 PLB Arbiter PLB Bus plb_arbiter_if plb_ap plb_sp1 PLB_OPB Bridge opb_mp1 OPB Bus opb_sp1 Memory Controller mem_p Address map: 0x6000 to 0x6FFF Memory Model #define Ext_Mem 0x6F00 main (..) { char *p = Ext_Mem; // ; *p = A + B; //.; } 1) Issw.plb_mp2->non_blocking_write (0x6F00, sum(a+b)) 2) plb_bus.plb_ap->arbitrate_request( ) 3) Plb queries its slaves and finds plb_opb_bridge mapped to address 0x6F00 4) plb_bus.plb_sp1->write(0x6f00, sum) 5) brg.opb_mp1->non_blocking_write (0x6F00, sum) 6) opb_bus.opb_sp1->write(0x6f00, sum) 7) mc.mem_p->write(0x6f00, sum) 8) Mem[0x6F00] = sum Source: RAB, IBM Research
Running Software on the SystemC Models Load the cross-compiled executable from the host file system using the RISCWatch debugger PowerPC 405 ISS Executables are cross-compiled to target the PowerPC 405 A linker script insures that executables map into the model s memory space 0x10000000-0x1fffffff DDR Memory Controller PLB4 I/O Device 0x20000000-0x200000ff Newlib library provides most operating system level (libc) functions executables need http://sources.redhat.com/newlib/ Newlib I/O functions work with the SystemC I/O Device model Redirect all ISS I/O operations to the host file system
ChipBench SLD - Power DMA SI_MEM_MEM_TX SoC Virtual Design V1 V3 v4 V5 V2 Map Top-level Program Core Models Instrumentation RD_FROM_PLB RD_FROM_OPB WR_TO_OPB WR_TO_PLB Power parameter Power parameter Power parameter Power parameter SoC System-level Diagram Scheduler Power Augmented Transaction Level Model (SystemC) Power Models for cores Transaction based characterization (read, write ) determines power values Transaction level simulation determines activity of each core, Power augmented systemc model, executes performance and power simulation Workload-driven power analysis
ChipBench SLD - Area SoC Virtual Design V1 V3 Map V1 V2 V2 v4 V5 V4 V3 SoC System-level Diagram V5 SoC Floorplan (Virtual Design) Hard-core: area is known Soft-core: run area-planning to estimate area Estimate number of real pins and assign locations of major cores as needed Run FP to get initial placement & pin-assignment to refine pin positions (initially in the center) Re-run FP Run global routing Compute die-size and congestion metrics SoC Floorplan (Virtual Design Level)
Mapping to Real Design (RTL) SoC Virtual Design V1 V3 v4 V5 V2 Map C1 C2 C3 C4 GL GL C6 C7 SoC System-level Diagram SoC RTL design From Virtual Design to RTL Chipbench SLD virtual design creation Map Virtual components to Real RTL components + glue logic Expand all virtual nets and pins into real nets and real pins Make RTL connections as specified by pin properties Generate RTL VHDL/Verilog Pass Virtual FP initial placements to Real FP initial placements Complete FP of RTL / Real Design Die Size Timing analysis Consistent timing-placement algorithms SLD-> Prototyping->Physical Synthesis Implementation if following with IBM RTL-GDS implementation flow
SoC Early System Experiment PLB Arbiter EBC HSMC CLOCK/RESET GEN PLL PM Clocks / resets 405 CPU MAL Private OPB PLB 64 bit UIC DMA PLB-OPB Bridge EMAC RX FIFO TX FIFO EMAC RX FIFO TX FIFO OPB Arbiter GPIO UART0 UART1 IIC GPT OPB 32 bit PPC405 Platform Based Design Ethernet Subsystem 1 EMAC 1 Madmal Real Embedded Application along with simple OS executing on TLM models to evaluate performance of Ethernet Sub-System Common example to test performance of ethernet subsystems Sets the Ethernet Macro in a loopback mode, and compares the transmitted and received packets Measure effects on performance, die-size, fp, power Change to improve performance Added an extra EMAC + Fifos Two EMAC mode of the application works with packets being transmitted from one EMAC and received by the other 30000 25000 20000 15000 10000 5000 0 System Throughput (KBytes/sec) 2 Emac 1 Emac 64 128 256 512 1024 2048 4096 Packet sizes (bytes) 120 100 80 60 40 20 0 CPU Utilization (% of total time) 2 Emac 1 Emac 64 128 256 512 1024 2048 4096 Packet sizes (bytes) 350 300 250 200 150 100 Power (mw) 2 Emac 1 Emac 64 128 256 512 102420484096 Packet sizes (bytes)
Power Evaluation Kit V1.0 Power Architecture Evaluation Kit V1.0 Description The Power Evaluation Kit (PEK) is an SoC framework which includes a toolkit and a set of architecture models that are designed to enable embedded software development and performance analysis for consumer applications based on the PowerPC Architecture Use Scenario Enables IP and tool providers to package, embed and distribute IP and knowledge that is ready for use by SoC developers Relevance Enables designers to evaluate, build and verify SoC designs using Architecture analysis models and tools using an industry standard modeling language enabling integration of third party IP. Release mechanism Will be announced at the Power.org event in Shanghai on September 26 th and to be made available through Developer works PEK V1.0 Features IBM SystemC Models for PPC4xx and CoreConnect IP Cores 60-days evaluation licensed for a limited capacity version of IBM ChipBench System Level Design tool IBM RISCWatch debugger tools Pre-integrated SoC platform optimized for architecture exploration and extensions Sample application code with tutorial Enabled for GCC tool chain Reference SW API documentation Technical support via IBM DeveloperWorks Reference technical manual PPC405 EBC UART Bridge DDR1 PLB4 Arbiter OPB Arbiter MAL User Model User Model EMAC
Conclusions Integrated tool suite along with System Level IP supporting the PowerPC and CoreConnect Architectures. Performance, power analysis of embedded software, cosimulation capability, along with core stitching & physical prototyping early in the design flow. Abstract Input Specification. Easy to write and change. Minimum complexity algorithms that understand this abstract spec (through models) Complete system optimization possibilities provided through integrated early analysis with strong links to implementation.
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