Digital Filters in Radiation Detection and Spectroscopy

Similar documents
User's Manual PIXIE-16

User's Manual Digital Gamma Finder (DGF)

User's Manual PIXIE-4

labmanual Software User Manual labzy-mca Versions 8.40 to 8.49 Rev. 1a

User's Manual. Digital Gamma Finder (DGF) PIXIE-16. Version 1.40, October 2009 XIA LLC Genstar Rd. Hayward, CA USA

labmanual Software User Manual labzy-psd Versions 2.00 to 2.49 Revision 1c

IMPLEMENTATION OF AN ADAPTIVE FIR FILTER USING HIGH SPEED DISTRIBUTED ARITHMETIC

PCI-FPGA-1B User Guide

DIGITAL SYSTEM. Technology Overview Nordco. All rights reserved. Rev C

Fatima Michael College of Engineering & Technology

D. Richard Brown III Professor Worcester Polytechnic Institute Electrical and Computer Engineering Department

EASY-NIM 928 Suite. High Performance, Multi-Function Nuclear MCA/Counter/Timer/Rate Meter

D. Richard Brown III Associate Professor Worcester Polytechnic Institute Electrical and Computer Engineering Department

Digital Gamma Finder (DGF) PIXIE-4 Manuals. Version 1.22, December X-Ray Instrumentation Associates Central Ave Newark, CA USA

Fault Tolerant Parallel Filters Based On Bch Codes

SIGNALS AND SYSTEMS I Computer Assignment 2

UCS-20. Operating Manual Macintosh Edition. Spectrum Techniques, Inc. Oak Ridge, Tennessee USA. Universal Computer Spectrometer.

CAEN. Electronic Instrumentation. MC2Analyzer User Manual. Software for digital Multi Channel Analyzer. User Manual UM3182

ECE4703 B Term Laboratory Assignment 2 Floating Point Filters Using the TMS320C6713 DSK Project Code and Report Due at 3 pm 9-Nov-2017

FPGA Design Challenge :Techkriti 14 Digital Design using Verilog Part 1

Exercises in DSP Design 2016 & Exam from Exam from

Digital Gamma Finder (DGF) PIXIE-4 Manuals

MASSACHUSETTS INSTITUTE OF TECHNOLOGY Department of Electrical Engineering and Computer Sciences

Digital Detector Emulator. This is the only synthesizer of random. Your Powerful User-friendly Solution for the Emulation of Any Detection Setup

Floating-point to Fixed-point Conversion. Digital Signal Processing Programs (Short Version for FPGA DSP)

Pixie-500 Express Manual Extension Pulse Shape Analysis Functions

GC2011A 3.3V DIGITAL FILTER CHIP DATASHEET. March 21, 2000

RUN-TIME RECONFIGURABLE IMPLEMENTATION OF DSP ALGORITHMS USING DISTRIBUTED ARITHMETIC. Zoltan Baruch

Readout Systems. Liquid Argon TPC Analog multiplexed ASICs SiPM arrays. CAEN 2016 / 2017 Product Catalog

5. Delta-Sigma Modulators for ADC

ISSN (Online), Volume 1, Special Issue 2(ICITET 15), March 2015 International Journal of Innovative Trends and Emerging Technologies

Fast data acquisition measurement system for plasma diagnostics using GEM detectors

Classification of Semiconductor LSI

UCS 10. Operating Manual. Spectrum Techniques, Inc. Oak Ridge, Tenn. USA. Universal Computer Spectrometer. August 1996

VLSI Implementation of Low Power Area Efficient FIR Digital Filter Structures Shaila Khan 1 Uma Sharma 2

Fault Tolerant Parallel Filters Based on ECC Codes

MCM Based FIR Filter Architecture for High Performance

Head, Dept of Electronics & Communication National Institute of Technology Karnataka, Surathkal, India

Analysis and Realization of Digital Filter in Communication System

Electronic Instrumentation

Advanced Design System 1.5. Digital Filter Designer

END-TERM EXAMINATION

An introduction to DSP s. Examples of DSP applications Why a DSP? Characteristics of a DSP Architectures

HIGH-PERFORMANCE RECONFIGURABLE FIR FILTER USING PIPELINE TECHNIQUE

INTEGER SEQUENCE WINDOW BASED RECONFIGURABLE FIR FILTERS.

Analog ASICs in industrial applications

FPGA Algorithm Development Using a Graphical Environment

30/05/96 V465 User's Manual CHIMERA VERSION TABLE OF CONTENTS

Scintillator-strip Plane Electronics

Hardware and Installation

FPGA Based Digital Signal Processing Applications & Techniques. Nathan Eddy Fermilab BIW12 Tutorial

Digital Signal Processing with Field Programmable Gate Arrays

Representation of Numbers and Arithmetic in Signal Processors

FPGA Implementation of Multiplierless 2D DWT Architecture for Image Compression

User's Manual. PXI Power Distribution Module

Implementing FIR Filters

Using SystemView by ELANIX to Generate Bit Error Rate (BER) Curves Maurice L. Schiff, Ph.D., Chief Scientist, ELANIX, Inc.

Analog Input Sample Rate

VME Data Acquisition System, ADC Read

CHAPTER 4. DIGITAL DOWNCONVERTER FOR WiMAX SYSTEM

Annexure: 1 SPECIFICATION FOR HPGE DETECTOR AND ACCESSORIES

International Journal for Research in Applied Science & Engineering Technology (IJRASET) IIR filter design using CSA for DSP applications

COMPARISON OF DIFFERENT REALIZATION TECHNIQUES OF IIR FILTERS USING SYSTEM GENERATOR

ASSIGNMENT ECE514 (COMPUTER ORGANIZATION) ASSIGNMENT NO. 3

Parallel FIR Filters. Chapter 5

Digital Signal Processor 2010/1/4

2015 Paper E2.1: Digital Electronics II

Vertical-Horizontal Binary Common Sub- Expression Elimination for Reconfigurable Transposed Form FIR Filter

This section gives a brief description of the MatrixB system outlining its main features and applications.

PROGRESS ON ADF BOARD DESIGN

arxiv:physics/ v1 [physics.ins-det] 18 Dec 1998

EEE 512 ADVANCED DIGITAL SIGNAL AND IMAGE PROCESSING

Digitizer products. VME NIM Desktop

REGISTER TRANSFER LANGUAGE

IOS Channel Isolated Digital Input Module with Interrupts

Digital Electronics 27. Digital System Design using PLDs

How to validate your FPGA design using realworld

Intel Stratix 10 Variable Precision DSP Blocks User Guide

Discrete models of the NLFSR generators

2008/12/23. System Arch 2008 (Fire Tom Wada) 1

Product Information Sheet PX Channel, 14-Bit Waveform Digitizer

PCI-DAS6402/16 Specifications

A Further Study on Large Size LSO and LYSO Crystal Samples

register:a group of binary cells suitable for holding binary information flip-flops + gates

Chapter 6 (Lect 3) Counters Continued. Unused States Ring counter. Implementing with Registers Implementing with Counter and Decoder

7. Integrated Data Converters

Review Study on a Design of Finite Impulse Response Filter

University of Saskatchewan 5-1 EE 392 Electrical Engineering Laboratory III

Batchu Jeevanarani and Thota Sreenivas Department of ECE, Sri Vasavi Engg College, Tadepalligudem, West Godavari (DT), Andhra Pradesh, India

VHDL MODEL OF SMART SENSOR

Hewlett-Packard HDCS-2000 CMOS Image Sensor Circuit Analysis

Fitting to a set of data. Lecture on fitting

Results of Radiation Test of the Cathode Front-end Board for CMS Endcap Muon Chambers

ADQ14-FWPD. User Guide. Author(s): Teledyne SP Devices Document ID: Classification: Public Revision: PA1 Print date:

A full digital approach in Physics Applications

MODULAR, SCALABLE ULTRASOUND DATA PROCESSING ARCHITECTURE PROVIDES A FLEXIBLE, COST-EFFECTIVE SOLUTION FOR MEDIUM-HIGH COMPLEXITY SYSTEMS

Selecting PLLs for ASIC Applications Requires Tradeoffs

PCI-DAS1602/12 Specifications

Schematic. A: Overview of the Integrated Detector Readout Electronics and DAQ-System. optical Gbit link. 1GB DDR Ram.

19. Implementing High-Performance DSP Functions in Stratix & Stratix GX Devices

Transcription:

Digital Filters in Radiation Detection and Spectroscopy Digital Radiation Measurement and Spectroscopy NE/RHP 537 1

Classical and Digital Spectrometers Classical Spectrometer Detector Preamplifier Analog Shaping Amplifier Multichannel Analyzer Histogram Memory Digital Spectrometer Detector Preamplifier High-Speed ADC Digital Pulse Processing Histogram Memory 2

Digital Spectrometers: Advantages Pulse processing algorithm is easy to edit No bulky analog electronics Post-processing Digital Spectrometer Digital pulse shaping More cost-effective The algorithm is stable and reliable, no thermal noise or other fluctuations Effects, such as pile-up can be corrected or eliminated at the processing level Detector Preamplifier High-Speed Signal capture and processing can be based more easily on coincidence criteria between different detectors or different parts of the same detector Disadvantage: Lack of expert in (Digital Systems + Nuclear Spectroscopy) ADC Digital Pulse Processing Histogram Memory 3

Signal Pulses From Scintillation Detectors Integrating Preamp R f Scintillation Detector NaI PMT Anode output 2 A C f Preamp output 1 V max 4

Digital Spectrometers: Digital Pulse Processor (Hardware) Analog Conditioning: o o o Nyquist filter (F mmm < F aaa 2 ) Offset adjustment Amplification Gain High resolution, fast Analog-to-Digital Convertor (ADC) Processing Device: o FPGA (Field-Programmable Gate Array) o DSP (Digital Signal Processor) A typical FPGA-based digital pulse processor for scintillation detector Interface: USB, PCI, Ethernet 5

Digital Spectrometers: Field-Programmable Gate Array (FPGA) FPGAs are an array of programmable logic cells interconnected by a network of wires and configurable switches. A FPGA has a large number of these cells available to form multipliers, adders, accumulators and so forth in complex digital circuits. FPGAs can be infinitely reprogrammed in-circuit in only a small fraction of a second. New FPGA devices provide integrated memory component, to be used as histogram memory. 6

Digital Spectrometers: Inside the FPGA Threshold Trigger Trigger FPGA Preamp ADC Shaping Filter Shaping Time Real Counter Detector Peak Detector Enable Control Unit (State Machine) Enable Enable Address Histogram Memory Memory Update Live Counter 7

Digital Spectrometers: Trigger Module Threshold From ADC Fast Triangular Filter A B Comparator A<B Trigger State Machine Trigger Output Trigger Module 8

Digital Spectrometers: MCA State Machine 1. STOP: wait until receiving start pulse 2. RESET: start MCA by resetting counters, buffers, 3. START: wait for a trigger pulse 4. RD-BASE: read baseline 5. CNT: wait for N clock cycles 6. PEAK: take a sample from the shaped pulse (peak) 7. AMP: calculate aaa = pppp bbbbbbbb 8. SET-ADD: locate and set memory address which corresponds to the pulse amplitude 9. RD-BIN: read current counts from the located address 10. INC-BIN: increment the count by one 11. WR-BIN: write the incremented count to the same address, go to START state 12. START: wait for another trigger TRIGGER? N? RESET START RD-BASE CNT PEAK Pileup Start? STOP AMP WR-BIN INC-BIN RD-BIN SET-ADD MCA State Machine with 11 states 9

Convolution Operation A finite impulse response (FIR) filter is a filter whose impulse response (or response to any finite length input) is of finite duration, because it settles to zero in finite time. This is in contrast to infinite impulse response (IIR) filters, which may have internal feedback and may continue to respond indefinitely. For FIR digital filters, the input-output h[n] relation involves a finite sum of products Convolution operation defines how the x[n] convolution y[n] input signal is related to the output signal 10

Convolution Operation (Sum of Products) h[n] x[n] is the input signal y[n] is the output signal x[n] convolution y[n] h[n] is impulse response (filter coefficients) n is the sample number N+1 is the filter size N y[ n] = h[ k]. xn [ k] k = 0 yn [ ] = h[0]. xn [ ] + h[1]. xn [ 1] +... + hn [ ]. xn [ N] 11

Convolution Operation Clock # 4 Filter Coefficients Input Signal h[3] h[2] h[1] h[0] x[0] x[1] x[2] x[3] x[4] x[5] x[6] x[7] x[8] x[9]... Output Signal: y[4] = h[0]. x[4] + h[1]. x[3] + h[2]. x[2] + h[3]. x[1] 5 h[3] h[2] h[1] h[0] x[0] x[1] x[2] x[3] x[4] x[5] x[6] x[7] x[8] x[9]... Output Signal: y[5] = h[0]. x[5] + h[1]. x[4] + h[2]. x[3] + h[3]. x[2] 6 h[3] h[2] h[1] h[0] x[0] x[1] x[2] x[3] x[4] x[5] x[6] x[7] x[8] x[9]... Output Signal: y[6] = h[0]. x[6] + h[1]. x[5] + h[2]. x[4] + h[3]. x[3] 12

Convolution in Hardware (Realization) x[n] x[n-1] x[n-2] x[n-3] Reg Reg Reg h[0] h[1] h[2] h[3] y[n] yn [ ] = h[0]. xn [ ] + h[1]. xn [ 1] + h[2]. xn [ 2] + h[3]. xn [ 3] 13

Moving Average Filter: Noise Reduction Consider a digital filter whose output signal y[n] is the average of the four most recent values of the input signal x[n]: y[n] = ¼ ( x[n] + x[n-1] + x[n-2] + x[n-3] ) Such a filter is referred to as a Moving Average Filter and is commonly used for noise reduction. The amount of noise reduction is equal to the square-root of the number of points in the average. For example, a 100 point moving average filter reduces the noise by a factor of 10. 14

Moving Average Filter: Noise Reduction Example of a moving average filter. In (a), a rectangular pulse is buried in random noise. In (b) and (c), this signal is filtered with 11 and 51 point moving average filters, respectively. As the number of points in the filter increases, the noise becomes lower; however, the edges becoming less sharp. 15

Moving Average Filter: Noise Reduction But how to implement a Moving Average Filter? y[n] = ¼ ( x[n] + x[n-1] + x[n-2] + x[n-3] ) Recall the convolution operation (sum of products) yn [ ] = h[0]. xn [ ] + h[1]. xn [ 1] + h[2]. xn [ 2] + h[3]. xn [ 3] In this example, h[n] should be: h = [ ¼, ¼, ¼, ¼ ] OR h = [ 1/N, 1/N, 1/N, 1/N ], where N is the number of coefficients in the filter 16

Trapezoidal Filter: Pulse Shaping (for Pre-Amp pulses) Positive Averaging over L samples Gap Negative Averaging over L samples h = [.1,.1,.1,.1,.1,.1,.1,.1,.1,.1, 0, 0, 0, 0, 0, -.1, -.1, -.1, -.1, -.1, -.1, -.1, -.1, -.1, -.1 ] Length (L) = 10 25 20 Gap (G) = 5 Peaking Time > Charge Collection Time Signal Input Filter Output 15 10 5 0 190 195 200 205 210 215 220 225 230 235 17

Triangular Filter: Trigger A triangular filter is a special trapezoidal filter with G=0. Triangular filters with peaking time of 25 nsec and 50 nsec (with T=5 nsec) are: h1 = [ -1, -1, -1, -1, -1, 1, 1, 1, 1, 1 ] h2 = [-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] Triangular Filter (20 nsec peaking time) 18

Triangular Filter: Pulse Integration (for Anode pulses) Integration Time = L. Sampling Period ; (The time over which scintillator emits most of its light ~ 99% ~ 4.6 decay time) NaI: 230 * 4.6 = 1058 nsec Anode output Preamp output G=0 (Triangle Filter) Unity Coefficients (no normalization) For pulses with negative polarity L -1 L 1 Pulse Integration Baseline Correction For pulses with positive polarity 1-1 19

Trapezoidal and Triangular Filters 40 35-1/L..0.. 1/L 30 Preamp 25 Output ADC Units 20 15 10 5 Filter Response 0 L G L Energy Filter (Trapezoidal), L=100,G=20-5 -10 Triggering Threshold Trigger Filter (Triangular), L=5,G=0-15 900 950 1000 1050 1100 1150 1200 1250 1300 1350 1400 1450 Time (nsec) 20

Trapezoidal Filters, Pile-up Inspection and Correction 40 35 30 V2 (max) ADC Units Preamp 25 Output 20 15 10 V1(max) Pile-up is OK if (t2 - t1) > L+G Peak value is sampled 5 Filter Response 0-5 -10 t2 t1-15 900 950 1000 1050 1100 1150 1200 1250 1300 1350 1400 1450 Time (nsec) 21

Trapezoidal and Triangular Filter: Response to Step Function 22

Some Convolution Practices (with pen and paper!) Pre-Amp Pulse: x = [1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 3, 3] Digital Filter: h = [ ½, ½, 0, 0, -½, -½ ] Using the Convolution equation, find y[5-11]. h[n] N y[ n] = h[ k]. xn [ k] k = 0 x[n] convolution y[n] 23

Some Convolution Practices (with pen and paper!) Y[5] = (h[0].x[5-0]) + (h[1].x[5-1]) + (h[2].x[5-2]) + (h[3].x[5-3]) + (h[4].x[5-4]) + (h[5].x[5-5]) Y[5] = (h[0].x[5]) + (h[1].x[4]) + (h[2].x[3]) + (h[3].x[2]) + (h[4].x[1]) + (h[5].x[0]) Y[5] = (0.5 * 1) + (0.5 * 1) + (0 * 1) + (0 * 1) + (-0.5 * 1) + (-0.5 * 1) = 0 Y[6] = (h[0].x[6-0]) + (h[1].x[6-1]) + (h[2].x[6-2]) + (h[3].x[6-3]) + (h[4].x[6-4]) + (h[5].x[6-5]) Y[6] = (h[0].x[6]) + (h[1].x[5]) + (h[2].x[4]) + (h[3].x[3]) + (h[4].x[2]) + (h[5].x[1]) Y[6] = (0.5 * 3) + (0.5 * 1) + (0 * 1) + (0 * 1) + (-0.5 * 1) + (-0.5 * 1) = 1 Y[7] = (h[0].x[7-0]) + (h[1].x[7-1]) + (h[2].x[7-2]) + (h[3].x[7-3]) + (h[4].x[7-4]) + (h[5].x[7-5]) Y[7] = (h[0].x[7]) + (h[1].x[6]) + (h[2].x[5]) + (h[3].x[4]) + (h[4].x[3]) + (h[5].x[2]) Y[7] = (0.5 * 3) + (0.5 * 3) + (0 * 1) + (0 * 1) + (-0.5 * 1) + (-0.5 * 1) = 2 24

Some Convolution Practices (with pen and paper!) Y[8] = (h[0].x[8-0]) + (h[1].x[8-1]) + (h[2].x[8-2]) + (h[3].x[8-3]) + (h[4].x[8-4]) + (h[5].x[8-5]) Y[8] = (h[0].x[8]) + (h[1].x[7]) + (h[2].x[6]) + (h[3].x[5]) + (h[4].x[4]) + (h[5].x[3]) Y[8] = (0.5 * 3) + (0.5 * 3) + (0 * 3) + (0 * 1) + (-0.5 * 1) + (-0.5 * 1) = 2 Y[9] = (h[0].x[9-0]) + (h[1].x[9-1]) + (h[2].x[9-2]) + (h[3].x[9-3]) + (h[4].x[9-4]) + (h[5].x[9-5]) Y[9] = (h[0].x[9]) + (h[1].x[8]) + (h[2].x[7]) + (h[3].x[6]) + (h[4].x[5]) + (h[5].x[4]) Y[9] = (0.5 * 3) + (0.5 * 3) + (0 * 3) + (0 * 3) + (-0.5 * 1) + (-0.5 * 1) = 2 Y[10] =(h[0].x[10-0]) + (h[1].x[10-1]) + (h[2].x[10-2]) + (h[3].x[10-3]) + (h[4].x[10-4]) + (h[5].x[10-5]) Y[10] = (h[0].x[10]) + (h[1].x[9]) + (h[2].x[8]) + (h[3].x[7]) + (h[4].x[6]) + (h[5].x[5]) Y[10] = (0.5 * 3) + (0.5 * 3) + (0 * 3) + (0 * 3) + (-0.5 * 3) + (-0.5 * 1) = 1 25

Some Convolution Practices (with pen and paper!) Y[11] =(h[0].x[11-0]) + (h[1].x[11-1]) + (h[2].x[11-2]) + (h[3].x[11-3]) + (h[4].x[11-4]) + (h[5].x[11-5]) Y[11] = (h[0].x[11]) + (h[1].x[10]) + (h[2].x[9]) + (h[3].x[8]) + (h[4].x[7]) + (h[5].x[6]) Y[11] = (0.5 * 3) + (0.5 * 3) + (0 * 3) + (0 * 3) + (-0.5 * 3) + (-0.5 * 3) = 0 26

Digital Filters: Infinite Impulse Response (IIR) Trapezoidal shaping using recursive algorithm Digital filters can be realized in FPGA with minimum resources using recursive algorithm. In a recursive algorithm, to synthesis a trapezoidal output y[n] from a step input x[n], we can process the input in two steps. In the first step, the step input x[n] is first converted to a bipolar rectangular pulse r[n]. In the second step, r[n] is converted to a trapezoidal output using an accumulator. 27

Digital Filters: Infinite Impulse Response (IIR) Trapezoidal shaping using recursive algorithm Z ttttttttt: H z = h [k]z k x n = A u n k= X z = A 1 z 1 r n = A {u n u n k u n l + u n l k } R z = A 1 1 z 1 z k 1 z z l z l k + 1 1 z 1 1 z 1 R z = A 1 z 1 {1 z k z l + z l k } r n = x n v[n] V z = R(z) X(z) = 1 z k z l + z l k Z ttttttttt oo aa aaaaaaaaaaa = W z = Y(z) R(z) = 1 1 z 1 28

Digital Filters: Infinite Impulse Response (IIR) Trapezoidal shaping using recursive algorithm The Z transfer function is: H z = Y(z) X(z) = V z. W z = 1 Z k Z l + Z l k 1 z 1 And finally, by a reverse Z transform we can find the recursive algorithm for the trapezoidal shaper: y n = y n 1 + (x n x n k ) (x n l x n l k ) x n x n k (x n x n k ) (x n l x n l k ) x n Z -k + - Z -l + - + + y n x n k x n l x n l k Z -1 y n 1 29