S SPLC782A 6COM/8SEG Controller/Driver JUL. 27, 2 Version. SUNPLUS TECHNOLOGY CO. reserves the right to change this documentation without prior notice. Information provided by SUNPLUS TECHNOLOGY CO. is believed to be accurate and reliable. However, SUNPLUS TECHNOLOGY CO. makes no warranty for any errors which may appear in this document. Contact SUNPLUS TECHNOLOGY CO. to obtain the latest version of device specifications before placing your order. No responsibility is assumed by SUNPLUS TECHNOLOGY CO. for any infringement of patent or other rights of third parties which may result from its use. In addition, SUNPLUS products are not authorized for use as critical components in life support devices/ systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Sunplus.
Table of Contents PAGE. GENERAL DESCRIPTION... 4 2. FEATURES... 4 3. BLOCK DIAGRAM... 4 4. SIGNAL DESCRIPTIONS... 5 5. FUNCTIONAL DESCRIPTIONS... 6 5.. OSCILLATOR... 6 5.2. CONTROL AND DISPLAY INSTRUCTIONS... 6 5.3. INSTRUCTION TABLE... 8 5.4. 8-BIT OPERATION AND 6-DIGIT -LINE DISPLAY (USING INTERNAL RESET)... 9 5.5. 4-BIT OPERATION AND 6-DIGIT -LINE DISPLAY (USING INTERNAL RESET)... 5.6. 8-BIT OPERATION AND 6-DIGIT 2-LINE DISPLAY (USING INTERNAL RESET)... 5.7. RESET FUNCTION... 5.8. DISPLAY DATA RAM (DD RAM)... 3 5.9. TIMING GENERATION CIRCUIT... 3 5.. LCD DRIVER CIRCUIT... 3 5.. CHARACTER GENERATOR ROM (CG ROM)... 3 5.2. CHARACTER GENERATOR RAM (CG RAM)... 3 5.3. CURSOR/BLINK CONTROL CIRCUIT... 7 5.4. INTERFACING TO MPU... 7 5.5. SUPPLY VOLTAGE FOR LCD DRIVE... 7 5.6. REGISTER --- IR (INSTRUCTION REGISTER) AND DR (DATA REGISTER)... 2 5.7. BUSY FLAG (BF)... 2 5.8. ADDRESS COUNTER (AC)... 2 5.9. SEGMENT DATA DIRECTION... 2 5.2. COMMON DATA DIRECTION... 2 5.2. I/O PORT CONFIGURATION... 2 6. ELECTRICAL SPECIFICATIONS... 2 6.. ABSOLUTE MAXIMUM RATINGS... 2 6.2. DC CHARACTERISTICS ( = 2.4V TO 4.5V, T A = 25 )... 2 6.3. DC CHARACTERISTICS ( = 4.5V TO 5.5V, T A = 25 )... 2 6.4. AC CHARACTERISTICS ( = 4.5V TO 5.5V, T A = 25 )... 22 6.5. AC CHARACTERISTICS ( = 2.4V TO 4.5V, T A = 25 )... 23 6.6. WRITE MODE TIMING DIAGRAM (WRITING DATA FROM MPU TO SPLC782A)... 24 6.7. READ MODE TIMING DIAGRAM (READING DATA FROM SPLC782A TO MPU)... 24 7. APPLICATION CIRCUITS... 25 7.. INTERFACE TO MPU... 25 7.2. APPLICATIONS FOR LCD... 25 8. CHARACTER GENERATOR ROM... 32 8.. SPLC782A - 6... 32 2 JUL. 27, 2 Version:.
9. PACKAGE/PAD LOCATIONS... 33 9.. PAD ASSIGNMENT... 33 9.2. SPLC782A PAD DIMENSIONS... 33 9.3. ORDERING INFORMATION... 33 9.4. PAD LOCATIONS... 34. DISCLAIMER... 36. REVISION HISTORY... 37 3 JUL. 27, 2 Version:.
6COM/8SEG CONTROLLER/DRIVER. GENERAL DESCRIPTION The SPLC782A, a dot-matrix LCD controller and driver, is a low-power CMOS integrated circuit. The SPLC782A is capable of connecting with MPU for LCD application and easily to be used for designing the low-cost products. 2. FEATURES! Character generator ROM: 88 bits Character font 5 x 8 dots: 92 characters Character font 5 x dots: 64 characters! 4 type CGROM mode, Max. 256 characters can be used.! Character generator RAM: 52 bits Character font 5 x 8 dots: 8 characters Character font 5 x dots: 4 characters! Provide connecting to 4-bit or 8-bit MPU! Direct driver for LCD: 6 COMs x 8 SEGs! 8-channel Bi-Direction segment driver! 6-channel Bi-direction common driver! Duty factor (selected by program): /8 duty: line of 5 x 8 dots / duty: line of 5 x dots /6 duty: 2 lines of 5 x 8 dots / line! LCD type-a, type-b waveform can be selected.! Built-in power on automatic reset circuit! Built-in oscillator circuit (with internal resistor)! Built-in Bias resistor! Support external clock operation! Package form: Au bump chip 3. BLOCK DIAGRAM OSC Timing Generation Circuit CL2 MOD MOD VSS V2 V3 VPP DB-DB3 DB4-DB7 RS R / W E Parallel to Serial Data Conversion Circuit 5 5 Busy Flag Character Character Generator Generator ROM RAM 8 Data 8 8 I / O Register 7 Buffer 7 8 Instruction 8 Instruction Register Decorder 7 Cursor Blink Control Circuit 8 Display Data RAM 8 Bytes 8-bit Bi-Direction Shift Register 8 8 Latch Circuit 6-bit 6 Shift Register 8 Segments x 6 Commons LCD Driver SHL D TYPE DIRC COM- COM6 SEG- SEG8 7 Address Counter 4 JUL. 27, 2 Version:.
4. SIGNAL DESCRIPTIONS Mnemonic PIN No. Type Description 9, 2, 28 I Logic Power input VSS, 2, 37 I Ground VPP 23, 24 I LCD Voltage; V LCD = VPP - VSS V2 V3 2 22 I LCD Bias Voltage Control. Open for /5 Bias, Short for /4 Bias E 27 I It is a start signal to read data or write data. R / W 25 I It is a signal to select read or write. : Read, : Write. RS 26 I It is a signal to select register. : Data register (for read and write) : Instruction register (for write), Busy flag -- address counter (for read). DB3 - DB 32-29 I/O Low-order 4 data bits DB7 - DB4 36-33 I/O High-order 4 data bits SEG8 - SEG 46-25 O Segment signals for LCD. COM6 - COM9 45-38 O Common signals for LCD. COM8 - COM - 8 O Common signals for LCD. TYPE 4 I LCD Alternate Signals. TYPE = : Type-A TYPE = : Type-B DIRC 5 I Common Scan Direction DIRC = : COM " COM2 " " COM5 " COM6 DIRC = : COM6 " COM5 " " COM2 " COM SHL 6 I Segment Shift Direction SHL = : SEG " SEG2 " " SEG79 " SEG8 SHL = : SEG8 " SEG79 " " SEG2 " SEG MOD 7 I CGROM / CGRAM Mode Select MOD 8 MODE MODE2 Function $ - $F as CGRAM $ - $7 as CGRAM, $8 - $F as CGROM $ - $3 as CGRAM, $4 - $F as CGROM $ - $F as CGROM OSC 3 For external clock operation, the clock is input to OSC; Open for normal mode. CL2 O Test Mode Clock Output; Open for normal mode. D 9 O Test Mode Data Output; Open for normal mode. 5 JUL. 27, 2 Version:.
5. FUNCTIONAL DESCRIPTIONS 5.. Oscillator The built-in RC oscillator generates suitable clock for SPLC782A operation. S = I / D = It shifts the display to the left S = I / D = It shifts the display to the right 5.2. Control and Display Instructions Control and display instructions is shown as follows: 5.2.4. Display ON/OFF control RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB DB 5.2.. Clear display Code D C B RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB DB Code It clears the whole display and sets display data RAM s address in address counter. 5.2.2. Return home D = : Display on, D = : Display off C = : Cursor on, C = : Cursor off B = : Blinks on, B = : Blinks off 5 x 8 dot character font 5 x dot character font Code RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB DB X 8th line Curso th line X: Do not care ( or ) It sets display data RAM s address in address counter and display returns to its original position. The cursor or blink goes to the left edge of the display (to the st line if 2 lines are displayed). The content of the Display Data RAM does not change. 5.2.5. Cursor or display shift Without changing DD RAM s data, it can move cursor and shift display. RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB DB Code S/C R/L X X 5.2.3. Entry mode set During writing and reading data, it sets cursor move direction and shifts the display. RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB DB Code I / D S Blink display alternately I / D = : Increment, I / D = : Decrement. S = : The display shift, S = : The display does not shift. S/C R/L Description Address Counter Shift cursor to the left AC = AC - Shift cursor to the right AC = AC + Shift display to the left. Cursor follows the display shift AC = AC Shift display to the right. Cursor follows the display shift AC = AC 6 JUL. 27, 2 Version:.
5.2.6. Function set RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB DB Display data RAM can read or write after this setting. Code DL N F X X In one-line display (N = ), (aaaaaaa) 2: () 6 - (4F) 6. X: Do not care ( or ) DL: It sets interface data length. DL = : Datas are transferred with 8-bit lengths (DB - DB7). DL = : Datas are transferred with 4-bit lengths (DB4 - DB7). (It requires two times to transfer data) N: It sets the number of the display line. N = : One-line display. N = : Two-line display. F: It sets the character font. F = : 5 x 8 dots character font. F = : 5 x dots character font. N F No. of Display Lines Character Font Duty Factor 5 x 8 dots / 8 5 x dots / X 2 5 x 8 dots / 6 In two-line display (N = ), (aaaaaaa) 2: () 6 - (27) 6 for the first line, (aaaaaaa) 2: (4) 6 - (67) 6 for the second line. 5.2.9. Read busy flag and address RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB DB Code DL N F X X When (BF = ) indicates that the system is busy now; it will not accept any instruction until no busy (BF = ). At the same time, the address counter contents (aaaaaaa) 2 is read out. 5.2.. Write data to character generator RAM or display data RAM RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB DB It cannot display two lines with 5 x dot character font. Code d d d d d d d d 5.2.7. Set character generator RAM address RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB DB It writes data (dddddddd) 2 to character generator RAM or display data RAM. Code a a a a a a 5.2.. Read data from character generator RAM or display data RAM It sets character generator RAM address (aaaaaa) 2 to the address counter. Character generator RAM data can read or write after this setting. Code RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB DB d d d d d d d d 5.2.8. Set display data RAM address RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB DB Code a a a a a a a It sets display data RAM address (aaaaaaa) 2 to the address counter. It reads data (dddddddd) 2 from character generator RAM or display data RAM. To get the correct data readout is shown belows: ). Set the address of the character generator RAM or display data RAM or shift the cursor instruction. 2). Send the Read instruction. 7 JUL. 27, 2 Version:.
5.3. Instruction Table Instruction Instruction Code RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB DB Description Execution time (fosc = 27KHz) Clear Display Write "2H" to DDRAM and set DDRAM address to "H" from AC Return Home - Set DDRAM address to "H" from AC and return cursor to its original position if shifted. The contents of DDRAM are not changed. Entry Mode I/D S Assign cursor moving direction Set and enable the shift of entire display Display ON/ D C B Set display(d), cursor(c), and OFF Control blinking of cursor(b) on/off control bit. Cursor or S/C R/L - - Set cursor moving and display Display Shift shift control bit, and the direction, without changing of DDRAM data. Function Set DL N F - - Set interface data length (DL: 8-bit/4-bit), numbers of display line (N: 2-line/-line) and, display font type (F:5x dots/5x8 dots) Set CGRAM AC5 AC4 AC3 AC2 AC AC Set CGRAM address in address Address counter. Set DDRAM AC6 AC5 AC4 AC3 AC2 AC AC Set DDRAM address in address Address counter Read Busy Flag BF AC6 AC5 AC4 AC3 AC2 AC AC Whether during internal operation and Address or not can be known by reading Counter BF. The contents of address counter can also be read. Write Data to D7 D6 D5 D4 D3 D2 D D Write data into internal RAM RAM (DDRAM/CGRAM). Read Data from D7 D6 D5 D4 D3 D2 D D Read data from internal RAM RAM (DDRAM/CGRAM). Note: -- : don t care.52ms.52ms 38µs 38µs 38µs 38µs 38µs 38µs 38µs 38µs 8 JUL. 27, 2 Version:.
5.4. 8-Bit Operation and 6-Digit -Line Display (Using Internal Reset) NO. Instruction Display Operation Power on. (SPLC782A starts initializing) Power on reset. No display. 2 Function set RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB DB Set to 8-bit operation and select -line display line and character font. X X 3 Display on / off control _ Display on. Cursor appear. 4 Entry mode set _ 5 Write data to CG RAM / DD RAM W_ Increase address by one. It will shift the cursor to the right when writing to the DD RAM/CG RAM. Now the display has no shift. Write " W ". The cursor is incremented by one and shifted to the right. 6 Write data to CG RAM / DD RAM WE_ Write " E ". The cursor is incremented by one and shifted to the right. 7 : : 8 Write data to CG RAM / DD RAM WELCOME_ Write " E ". The cursor is incremented by one and shifted to the right. 9 Entry mode set Write data to CG RAM / DD RAM Write data to CG RAM / DD RAM WELCOME_ ELCOME _ LCOME C_ Set mode for display shift when writing Write " "(space). The cursor is incremented by one and shifted to the right. Write " C ". The cursor is incremented by one and shifted to the right. 2 : : 3 Write data to CG RAM / DD RAM COMPAMY _ Write " Y ". The cursor is incremented by one and shifted to the right. 4 Cursor or display shift X X 5 Cursor or display shift X X 6 Write data to CG RAM / DD RAM 7 Cursor or display shift X X 8 Cursor or display shift X X 9 Write data to CG RAM / DD RAM COMPAMY _ COMPAMY _ COMPAMY _ COMPAMY _ COMPAMY _ OMPANY _ Only shift the cursor's position to the left (Y). Only shift the cursor's position to the left (M). Write " N ". The display moves to the left. Shift the display and the cursor's position to the right. Shift the display and the cursor's position to the right. Write " " (space). The cursor is incremented by one and shifted to the right. 2 : : 2 Return home WELCOME Both the display and the cursor return to the original position (address ). 9 JUL. 27, 2 Version:.
5.5. 4-Bit Operation and 6-Digit -Line Display (Using Internal Reset) NO. Instruction Display Operation Power on. (SPLC782A starts initializing) Power on reset. No display. 2 Function set RS R/W DB7 DB6 DB5 DB4 Set to 4-bit operation. 3 Function set Set to 4-bit operation and select -line display line and character font. X X 4 Display on / off control 5 Entry mode set 6 Write data to CG RAM / DD RAM W_ Display on. Cursor appears. Increase address by one. It will shift the cursor to the right when writing to the DD RAM/CG RAM. Now the display has no shift. Write " W ". The cursor is incremented by one and shifted to the right. 5.6. 8-Bit Operation and 6-Digit 2-Line Display (Using Internal Reset) NO. Instruction Display Operation Power on. (SPLC782A starts initializing) Power on reset. No display. 2 Function set RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB DB X X 3 Display on / off control 4 Entry mode set Set to 8-bit operation and select 2-line display line and 5 x 7 dot character font. Display on. Cursor appear. Increase address by one. It will shift the cursor to the right when writing to the DD RAM/CG RAM. Now the display has no shift. 5 Write data to CG RAM / DD RAM W_ Write " W ". The cursor is incremented by one and shifted to the right. 6 : : 7 Write data to CG RAM / DD RAM WELCOME_ Write " E ". The cursor is incremented by one and shifted to the right. 8 Set DD RAM address 9 Write data to CG RAM / DD RAM Write data to CG RAM / DD RAM Write data to CG RAM / DD RAM WELCOME _ WELCOME T_ WELCOME TO PART_ WELCOME TO PART_ It sets DD RAM's address. The cursor is moved to the beginning position of the 2nd line. Write " T ". The cursor is incremented by one and shifted to the right. Write " T ". The cursor is incremented by one and shifted to the right. Write " T ". The cursor is incremented by one and shifted to the right. JUL. 27, 2 Version:.
NO. Instruction Display Operation 2 Entry mode set 3 Write data to CG RAM / DD RAM WELCOME TO PART_ ELCOME O PARTY_ When writing, it sets mode for the display shift. Write " Y ". The cursor is incremented by one and shifted to the right. 4 : : 5 Return home WELCOME TO PARTY Both the display and the cursor return to the original position (address ). 5.7. Reset Function At power on, it starts the internal auto-reset circuit and executes the initial instructions. There are the initial procedures shown as belows: Power On Wait time > 5 ms after Vdd > 4.5V [ 8-Bit Interface ] Wait time > 4ms After > 2.7V RS R/W DB7 DB6 DB5 DB4 DB3 DB3 DB DB X X X X BF cannot be checked before this instruction. Function set ( Interface is 8 bits length. ) Wait time > 4. ms RS R/W DB7 DB6 DB5 DB4 DB3 DB3 DB DB X X X X BF cannot be checked before this instruction. Function set ( Interface is 8 bits length. ) Wait time > us RS R/W DB7 DB6 DB5 DB4 DB3 DB3 DB DB X X X X BF cannot be checked before this instruction. Function set ( Interface is 8 bits length. ) RS R/W DB7 DB6 DB5 DB4 DB3 DB3 DB DB N F X X I/D S Initialization Ends BF can be checked after the following instructions. Function set ( Interface is 8 bits length. Specify the number of display lines and character font. ) The number of display lines and character font cannot be changed afterwards. Display off Display clear Entry mode set JUL. 27, 2 Version:.
Power On [ 4-Bit Interface ] Wait time > 5 ms after Vdd > 4.5V RS R/W DB7 DB6 DB5 DB4 Wait time > 4ms After > 2.7V BF cannot be checked before this instruction. Function set ( Interface is 8 bits length. ) Wait time > 4. ms RS R/W DB7 DB6 DB5 DB4 BF cannot be checked before this instruction. Function set ( Interface is 8 bits length. ) Wait time > us RS R/W DB7 DB6 DB5 DB4 RS R/W DB7 DB6 DB5 DB4 N F X X I/D S Initialization Ends BF cannot be checked before this instruction. Function set ( Interface is 8 bits length. ) BF can be checked after the following instructions. Function set ( Set interface to be 4 bits length) Interface is 8 bits length. Function set ( Interface is 4 bits length. Specify the number of the display lines and character font. ) The number of display lines and character font cannot be changed afterwards. Display off Display clear Entry mode set 2 JUL. 27, 2 Version:.
5.8. Display Data RAM (DD RAM) The DD RAM stores display data and its RAM size is 8 bytes. The area in DD RAM that is not used for display can be used as a general data RAM. Its address is set in the address counter. There are the relations between the display data RAM s address and the LCD s position shown belows. -line display, 8 display characters 2 3 4 5 6 2 3 4 5 ( Example ) -line display, 8 display characters 2 3 4 5 6 7 8 2 3 4 5 6 7 79 8 4E 4F Display position Display data RAM address Display position Display data RAM address When the display shift operation is performed, the display data RAM's address moves as : ( i ) Left shift 2 3 4 5 6 6 7 ( ii ) Right shift 8 4F 2 3 4 5 6 5.9. Timing Generation Circuit The timing generation circuit can generate needed timing signals to the internal circuits. To prevent the internal timing interface, the MPU access timing and the RAM access timing are separately generated. 5.. Character Generator ROM (CG ROM) Using 8-bit character code, the character generator ROM generates 5 x 8 dot or 5 x dot character patterns. It also can generate 6 5 x 8 dot character patterns and 32 5 x dot character patterns. 5.. LCD Driver Circuit There are 6 commons x 8 segments signal drivers in the LCD driver circuit. When a program specifies the character fonts and line numbers, the corresponding common signals will output drive waveforms and the others still output unselected waveforms. 5.2. Character Generator RAM (CG RAM) Using the programs, users can easily change the character patterns in the character generator RAM. It can be written with 5 x 8 dots, 8 character patterns or written with 5 x dots, 4 character patterns. 3 JUL. 27, 2 Version:.
Here are the SPLC782A s character patterns shown as belows: Correspondence between Character Codes and Character Patterns. 4 JUL. 27, 2 Version:.
The relations between character generator RAM addresses, character generator RAM data (character patterns) and character codes are shown as belows: 5.2.. 5 x 8 dot character patterns Character Code ( DD RAM Data ) CG RAM Address Character Patterns ( CG RAM Data ) b7 b6 b5 b4 b3 b2 b b b5 b4 b3 b2 b b b7 b6 b5 b4 b3 b2 b b X X X X X X X X Character Pattern Example () Cursor Position Character Pattern Example (2) Note: It means that the bit~2 of the character code correspond to the bit3~5 of the CG RAM address. Note2: These areas are not used for display, but can be used for the general data RAM. Note3: When all of the bit4-7 of the character code are, CG RAM character patterns are selected. Note4: " ": Selected, " " : No selected, " X " : Do not care ( or ). Note5: For example (), set character code (b2 = b = b =, b3 = or, b7-b4 = ) to display T. That means character code () 6,and (8) 6 can display T character. Note6: The bits -2 of the character code RAM is the character pattern line position. The 8th line is the cursor position and display is formed by logical OR with the cursor. 5 JUL. 27, 2 Version:.
5.2.2. 5 X dot character patterns Character Code ( DD RAM Data ) CG RAM Address Character Patterns ( CG RAM Data ) b7 b6 b5 b4 b3 b2 b b b5 b4 b3 b2 b b b7 b6 b5 b4 b3 b2 b b Character Pattern Example () X X X X X Cursor Position X X X X X X X X Note: It means that the bit~2 of the character code correspond to the bit4~5 of the CG RAM address. Note2: These areas are not used for display, but can be used for the general data RAM. Note3: When all of the bit4-7 of the character code are, CG RAM character patterns are selected. Note4: " : Selected, " : No selected, " X : Do not care ( or ). Note5: For example (), set character code (b2 = b =, b3 = b = or, b7-b4 = ) to display U. That means all of the character codes () 6, () 6, (8) 6,and (9) 6 can display U character. Note6: The bits -3 of the character code RAM is the character pattern line position. The th line is the cursor position and display is formed by logical OR with the cursor. 6 JUL. 27, 2 Version:.
5.3. Cursor/Blink Control Circuit It can generate the cursor or blink in the cursor / blink control circuit. The cursor or the blink appears in the digit at the display data RAM address set in the address counter. When the address counter is (7) 6, the cursor s position is shown as follows: b6 b5 b4 b3 b2 b b AC In a -line display digit 2 3 4 5 6 7 8 9 2 3 4 5 6 7 8 9 Display position Display data RAM address ( Hexadecimal ) In a 2-line display the cursor position digit st line 2nd line 2 3 4 5 6 7 8 9 2 3 4 5 6 7 8 9 4 4 42 43 44 45 46 47 48 49 Display position Display data RAM address ( Hexadecimal ) the cursor position 5.4. Interfacing to MPU There are two types of data operations: 4-bit operation and 8-bit operation. Using 4-bit MPU, the interfacing 4-bit data is transferred by 4 bus lines (for 8-bit operation, DB7 to DB4). The bus lines of DB - DB3 are not used. Using 4-bit MPU to interface 8-bit data needs two times. First, the higher 4-bit data is transferred by 4-busline (for 8-bit operation, DB7 to DB4). Secondly, the lower 4-bit data is transferred by 4 bus lines (for 8-bit operation, DB3 to DB). Using 8-bit MPU, the interfacing 8-bit data is transferred by 8 bus lines (DB - DB7). 5.5. Supply Voltage for LCD Drive LCD bias can be selected by open/short V2 and V3 pins. Duty Factor Supply Voltage /8, / /4 /6 /5 V2, V3 Short Open SPLC782A SPLC782A V2 V2 short open V3 V3 /4 Bias (/8, / Duty) /5 Bias (/6 Duty) 7 JUL. 27, 2 Version:.
5.5.. The relations between LCD frame s frequency and oscillator s frequency (Assume the oscillation frequency is 25KHz, clock cycle time = 4.µs) 5.5.2. /8 Duty, type-a waveform 4 clocks COM VPP V V2(V3) V4 VSS 2 3 4 8 2 frame frame = 4 (µs) x 4 x 8 = 28 (µs) = 2.8 ms Frame frequency = = 78. (Hz) 2.8 (ms) 5.5.3. / Duty, type-a waveform 4 clocks COM VPP V V2(V3) V4 VSS 2 3 4 frame 2 frame = 4 (µs) x 4 x = 76 (µs) = 7.6 ms Frame frequency = = 56.8 (Hz) 7.6 (ms) 5.5.4. /6 Duty, type-a waveform 2 clocks COM VPP V V2 V3 V4 VSS 2 3 4 6 2 frame frame = 4 (µs) x 2 x 6 = 28 (µs) = 2.8 ms Frame frequency = = 78. (Hz) 2.8 (ms) 8 JUL. 27, 2 Version:.
5.5.5. /8 Duty, type-b waveform 4 clocks COM VPP V V2(V3) V4 VSS 2 7 8 2 7 8 2 7 8 2 7 8 Frame Frame frame = 4(µs) x 4 x 8 = 28(µs) = 2.8ms Framefrequ ency = = 78.(Hz) 2.8(ms) 5.5.6. / Duty, type-b waveform 4 clocks COM VPP V V2(V3) V4 VSS 2 2 Frame Frame 2 frame = 4(µs) x 4 x = 76(µs) = 7.6ms Framefrequency = = 56. 8(Hz) 7.6(ms) 5.5.7. /6 Duty, type-b waveform 2 clocks COM VPP V V2 V3 V4 VSS 2 5 6 2 Frame Frame 5 6 2 frame = 4(µs) x 2 x 6 = 28(µs) = 2.8ms Framefrequ ency = = 78.(Hz) 2.8(ms) 9 JUL. 27, 2 Version:.
5.6. Register --- IR (Instruction Register) and DR (Data Register) SPLC782A has two 8-bit registers - IR (instruction register) and DR (data register). In the followings, we can use the combinations of the RS pin and the R/W pin to select the IR and DR. 5.2. Common Data Direction TYPE is the common data shift direction control pin. LCD common scan sequence from COM to COM6 by connecting TYPE to VSS, and is reversed by connecting TYPE to. 5.2. I/O Port Configuration RS R/W Operation IR write (Display clear, etc.) Read busy flag (DB7) and address counter (DB - DB6) DR write (DR to Display data RAM or Character generator RAM) DR read (Display data RAM or Character generator RAM to DR) 5.2.. Input port: E PMOS NMOS 5.7. Busy Flag (BF) When RS = and R/W =, the busy flag is output to DB7. As the busy flag =, SPLC782A is in busy state and does not accept any instructions until the busy flag =. 5.8. Address Counter (AC) The address counter assigns addresses to display data RAM and character generator RAM. When an instruction for address is written in IR, the address information is sent from IR to AC. After writing into (or reading from)display data RAM or character generator RAM, AC is automatically incremented by + (or decremented by -). AC contents are output to DB - DB6 when RS = and R/W =. 5.2.2. Input port: R/W, RS PMOS 5.2.3. Output port: CL2, D PMOS NMOS 5.9. Segment Data Direction PMOS SHL is the segment data shift direction control pin. LCD data is shifted from SEG to SEG8 by connecting SHL to VSS, and is reversed by connecting SHL to. NMOS 5.2.4. Input / Output port: DB - DB7 Enable PMOS PMOS NMOS Data 2 JUL. 27, 2 Version:.
6. ELECTRICAL SPECIFICATIONS 6.. Absolute Maximum Ratings Characteristics Symbol Ratings Operating Voltage -.3V to +7.V Driver Supply Voltage V PP -.3V to +7.V Input Voltage Range V IN -.3V to +.3V Operating Temperature T A -2 to +75 Storage Temperature T STO -55 to +25 Note: Stresses beyond those given in the Absolute Maximum Rating table may cause operational errors or damage to the device. For normal operational conditions see AC/DC Electrical Characteristics. 6.2. DC Characteristics ( = 2.4V to 4.5V, T A = 25 ) Characteristics Symbol Limit Min. Typ. Max. Unit Test Condition Operating Voltage 2.4-4.5 V Operating Current I DD -.8. ma Internal clock (Note) Input High Voltage V IH 2.2 - V Pins:(E, RS, R/W, DB - DB7) Input Low Voltage V IL -.3 -.6 V Input High Current I IH - - 2. µa Pins: (RS, R/W, DB - DB7) Input Low Current I IL -5. -3-6 µa = 3.V Output High Voltage (TTL) V OH 2.2 - V I OH = -.ma, Pins: DB - DB7 Output Low Voltage (TTL) V OL - -.4 V I OL =.ma, Pins: DB - DB7 Voltage Drop V DCOM - -. V I O =.ma, Pins: COM - COM6 V DSEG - -. V I O =.ma, Pins: SEG - SEG8 LCD Voltage V PP 4. - 6. V /4 bias or /5 bias Note: Pin E = L, RS, R/W, DB - DB7 are open, all outputs are no loads. 6.3. DC Characteristics ( = 4.5V to 5.5V, T A = 25 ) Characteristics Symbol Limit Min. Typ. Max. Unit Test Condition Operating Voltage 4.5-5.5 V Operating Current I DD -.8. ma Internal clock (Note) Input High Voltage V IH 2.2 - V Pins:(E, RS, R/W, DB - DB7) Input Low Voltage V IL -.3 -.6 V Input High Current I IH - - 2. µa Pins: (RS, R/W, DB - DB7) Input Low Current I IL -3-8 -25 µa = 5.V Output High Voltage (TTL) V OH 2.2 - V I OH = -.ma, Pins: DB - DB7 Output Low Voltage (TTL) V OL - -.4 V I OL =.ma, Pins: DB - DB7 Voltage Drop V DCOM - -. V I O =.ma, Pins: COM - COM6 V DSEG - -. V I O =.ma, Pins: SEG - SEG8 LCD Voltage V PP 4. - 6. V /4 bias or /5 bias Note: Pin E = L, RS, R/W, DB - DB7 are open, all outputs are no loads. 2 JUL. 27, 2 Version:.
6.4. AC Characteristics ( = 4.5V to 5.5V, T A = 25 ) 6.4.. Internal clock operation Characteristics Symbol Limit Min. Typ. Max. Unit OSC Frequency F OSC 9 27 35 KHz 6.4.2. LCD bias resistor Characteristics Symbol Limit Min. Typ. Max. Unit Bias Resistor R - R5 3. 5. 7. K-ohm 6.4.3. Write mode (Writing data from MPU to SPLC782A) Characteristics Symbol Limit Min. Typ. Max. Unit Test Condition E Cycle Time t C 5 - - ns Pin E E Pulse Width t PW 23 - - ns Pin E E Rise/Fall Time t R, t F - - 2 ns Pin E Address Setup Time t SP 4 - - ns Pins: RS, R/W, E Address Hold Time t HD - - ns Pins: RS, R/W, E Data Setup Time t SP2 8 - - ns Pins: DB - DB7 Data Hold Time t HD2 - - ns Pins: DB - DB7 6.4.4. Read mode (Reading Data from SPLC782A to MPU) Characteristics Symbol Limit Min. Typ. Max. Unit Test Condition E Cycle Time t C 5 - - ns Pin E E Pulse Width t W 23 - - ns Pin E E Rise/Fall Time t R, t F - - 2 ns Pin E Address Setup Time t SP 4 - - ns Pins: RS, R/W, E Address Hold Time t HD - - ns Pins: RS, R/W, E Data Output Delay Time t D - - 6 ns Pins: DB - DB7 Data hold time t HD2 5 - - ns Pins: DB - DB7 22 JUL. 27, 2 Version:.
6.5. AC Characteristics ( = 2.4V to 4.5V, T A = 25 ) 6.5.. Internal clock operation Characteristics Symbol Limit Min. Typ. Max. Unit OSC Frequency F OSC 9 27 35 KHz 6.5.2. LCD bias resistor Characteristics Symbol Limit Min. Typ. Max. Unit Bias Resistor R - R5 3. 5. 7. K-ohm 6.5.3. Write mode (Writing data from MPU to SPLC782A) Characteristics Symbol Limit Min. Typ. Max. Unit Test Condition E Cycle Time t C - - ns Pin E E Pulse Width t PW 45 - - ns Pin E E Rise/Fall Time t R, t F - - 25 ns Pin E Address Setup Time t SP 6 - - ns Pins: RS, R/W, E Address Hold Time t HD 2 - - ns Pins: RS, R/W, E Data Setup Time t SP2 95 - - ns Pins: DB - DB7 Data Hold Time t HD2 - - ns Pins: DB - DB7 6.5.4. Read mode (Reading data from SPLC782A to MPU) Characteristics Symbol Limit Min. Typ. Max. Unit Test Condition E Cycle Time t C - - ns Pin E E Pulse Width t W 45 - - ns Pin E E Rise/Fall Time t R, t F - - 25 ns Pin E Address Setup Time t SP 6 - - ns Pins: RS, R/W, E Address Hold Time t HD 2 - - ns Pins: RS, R/W, E Data Output Delay Time t D - - 36 ns Pins: DB - DB7 Data hold time t HD2 5. - - ns Pin DB - DB7 23 JUL. 27, 2 Version:.
6.6. Write Mode Timing Diagram (Writing Data from MPU to SPLC782A) RS VIH VIL tsp VIH VIL thd R / W VIL VIL tpw tf thd E VIH VIL VIH VIL VIL tr tsp2 thd2 DB - DB7 VIH VIL Valid Data VIH VIL tc 6.7. Read Mode Timing Diagram (Reading Data from SPLC782A to MPU) RS R / W VIH VIL tsp VIH VIH VIL thd VIH tpw tf thd E VIH VIL VIH VIL VIL tr td thd2 DB - DB7 VIH VIL Valid Data VIH VIL tc 24 JUL. 27, 2 Version:.
7. APPLICATION CIRCUITS 7.. Interface to MPU 7... Interface to 8-bit MPU (685) 685 PA PA7 PB PB PB2 8 DB DB7 E RS R / W COM COM6 SPLC782A SEG SEG8 6 8 LCD PANEL 6 COMMONS X 8 SEGMENTS 7..2. Interface to 8-bit MPU (Z8) Z8 D D7 A A7 A IORQ WR 7 8 DB DB7 E RS R / W COM COM6 SPLC782A SEG SEG8 6 8 LCD PANEL 6 COMMONS X 8 SEGMENTS 7.2. Applications for LCD 7.2.. Chip bottom & lower view (DIRC = "", SHL = "") LCD Panel 6 characters x line SEG COM8 SPLC782A BOTTOM VIEW SEG8 COM DIRC SHL V2 V3 ( Example ) : 5 x 8 dots, 6 characters x line [ / 4 Bias, / 8 Duty ] 25 JUL. 27, 2 Version:.
LCD Panel 6 characters x line SEG COM8 SPLC782A BOTTOM VIEW SEG8 COM COM SHL V2 V3 DIRC COM9 ( Example 2 ) : 5 x dots, 6 characters x line [ / 4 Bias, / Duty ] LCD Panel 6 characters x 2 line SEG COM8 COM SPLC782A BOTTOM VIEW DIRC SHL V2 V3 SEG8 COM6 COM9 ( Example 3 ) : 5 x 8 dots, 6 characters x 2 lines [ / 5 Bias, / 6 Duty ] 26 JUL. 27, 2 Version:.
7.2.2. Chip bottom & upper view (DIRC = "", SHL = "") V3 V2 SHL DIRC COM SEG8 SPLC782A BOTTOM VIEW COM8 SEG LCD Panel 6 characters x line ( Example 4 ) : 5 x 8 dots, 6 characters x line [ / 4 Bias, / 8 Duty ] COM9 V3 V2 SHL DIRC COM COM SEG8 SPLC782A BOTTOM VIEW COM8 SEG LCD Panel 6 characters x line ( Example 5 ) : 5 x dots, 6 characters x line [ / 4 Bias, / Duty ] 27 JUL. 27, 2 Version:.
COM9 V3 V2 SHL DIRC COM COM6 SEG8 SPLC782A BOTTOM VIEW COM8 SEG LCD Panel 6 characters x 2 line ( Example 6 ) : 5 x 8 dots, 6 characters x 2 lines [ / 5 Bias, / 6 Duty ] 7.2.3. Chip top & lower view (DIRC = "", SHL = "") LCD Panel 6 characters x line SEG8 SPLC782A TOP VIEW SEG COM8 V3 V2 SHL DIRC COM ( Example 7 ) : 5 x 8 dots, 6 characters x line [ / 4 Bias, / 8 Duty ] 28 JUL. 27, 2 Version:.
LCD Panel 6 characters x line SEG8 COM SPLC782A TOP VIEW SEG COM8 COM9 V3 V2 SHL DIRC COM ( Example 8 ) : 5 x dots, 6 characters x line [ / 4 Bias, / Duty ] LCD Panel 6 characters x 2 line SEG8 COM6 SPLC782A TOP VIEW SEG COM8 COM9 V3 V2 DIRC COM ( Example 9 ) : 5 x 8 dots, 6 characters x 2 lines [ / 5 Bias, / 6 Duty ] 29 JUL. 27, 2 Version:.
7.2.4. Chip top & upper view (DIRC = "", SHL = "") COM DIRC SHL V2 V3 COM8 SEG SPLC782A TOP VIEW SEG8 LCD Panel 6 characters x line ( Example ) : 5 x 8 dots, 6 characters x line [ / 4 Bias, / 8 Duty ] COM DIRC SHL V2 V3 COM9 COM8 SEG SPLC782A TOP VIEW COM SEG8 LCD Panel 6 characters x line ( Example ) : 5 x dots, 6 characters x line [ / 4 Bias, / Duty ] 3 JUL. 27, 2 Version:.
COM DIRC SHL V2 V3 COM9 COM8 SEG SPLC782A TOP VIEW COM6 SEG8 LCD Panel 6 characters x 2 line ( Example 2 ) : 5 x 8 dots, 6 characters x 2 lines [ / 5 Bias, / 6 Duty ] 3 JUL. 27, 2 Version:.
8. CHARACTER GENERATOR ROM 8.. SPLC782A - 6 32 JUL. 27, 2 Version:.
9. PACKAGE/PAD LOCATIONS 9.. PAD Assignment 9.2. SPLC782A PAD Dimensions Item Pad No. X Size Y Unit Chip Size - 52 69 PAD Pitch - 8 38-45 6.2 46-25 6.2-8 Bumped PAD Size 38-45 85. 4.3 46-25 4.3 85. 9-37 59.2 2. Bumped PAD Height All PAD 7 Note: Chip size included scribe line. Note2: To ensure that the IC functions properly, please bond all of and VSS pins. Note3: The.µF capacitor between and VSS should be placed to IC as close as possible. µm 9.3. Ordering Information Product Number SPLC782A-nnnnV-C Note: Code number (nnnnv) is assigned for customer. Note2: Code number (nnnn = - 9999); version (V = A - Z). Package Type Chip form(cog) 33 JUL. 27, 2 Version:.
9.4. PAD Locations PAD No. PAD Name X Y PAD No. PAD Name X Y COM8-2394 4 45 COM6 2386 33 2 COM7-2394 53 46 SEG8 2438 689 3 COM6-2394 -7 47 SEG79 2376 689 4 COM5-2394 -68 48 SEG78 235 689 5 COM4-2394 -3 49 SEG77 2254 689 6 COM3-2394 -9 5 SEG76 293 689 7 COM2-2394 -252 5 SEG75 232 689 8 COM -2394-33 52 SEG74 27 689 9 D -2327-694 53 SEG73 29 689 CL2-275 -694 54 SEG72 948 689 VSS -24-694 55 SEG7 887 689 2 VSS -959-694 56 SEG7 826 689 3 OSC -825-694 57 SEG69 764 689 4 TYPE -744-694 58 SEG68 73 689 5 DIRC -568-694 59 SEG67 642 689 6 SHL -487-694 6 SEG66 58 689 7 MOD -7-694 6 SEG65 52 689 8 MOD -99-694 62 SEG64 458 689 9-799 -679 63 SEG63 397 689 2-78 -679 64 SEG62 336 689 2 V3-584 -694 65 SEG6 275 689 22 V2-53 -694 66 SEG6 24 689 23 VPP -3-688 67 SEG59 52 689 24 VPP -229-688 68 SEG58 9 689 25 RS -94-694 69 SEG57 3 689 26 RW -3-694 7 SEG56 969 689 27 E 222-694 7 SEG55 98 689 28 49-679 72 SEG54 846 689 29 DB 583-694 73 SEG53 785 689 3 DB 7-694 74 SEG52 724 689 3 DB2 963-694 75 SEG5 663 689 32 DB3 9-694 76 SEG5 62 689 33 DB4 344-694 77 SEG49 54 689 34 DB5 47-694 78 SEG48 479 689 35 DB6 726-694 79 SEG47 48 689 36 DB7 853-694 8 SEG46 357 689 37 VSS 225-693 8 SEG45 296 689 38 COM9 2386-294 82 SEG44 234 689 39 COM 2386-233 83 SEG43 73 689 4 COM 2386-72 84 SEG42 2 689 4 COM2 2386-85 SEG4 5 689 42 COM3 2386-49 86 SEG4-9 689 43 COM4 2386 87 SEG39-7 689 44 COM5 2386 72 88 SEG38-32 689 34 JUL. 27, 2 Version:.
PAD No. PAD Name X Y PAD No. PAD Name X Y 89 SEG37-93 689 8 SEG8-356 689 9 SEG36-254 689 9 SEG7-47 689 9 SEG35-35 689 SEG6-478 689 92 SEG34-377 689 SEG5-539 689 93 SEG33-438 689 2 SEG4-6 689 94 SEG32-499 689 3 SEG3-662 689 95 SEG3-56 689 4 SEG2-723 689 96 SEG3-62 689 5 SEG -784 689 97 SEG29-683 689 6 SEG -845 689 98 SEG28-744 689 7 SEG9-97 689 99 SEG27-85 689 8 SEG8-968 689 SEG26-866 689 9 SEG7-229 689 SEG25-927 689 2 SEG6-29 689 2 SEG24-989 689 2 SEG5-25 689 3 SEG23-5 689 22 SEG4-223 689 4 SEG22-689 23 SEG3-2274 689 5 SEG2-72 689 24 SEG2-2335 689 6 SEG2-233 689 25 SEG -2396 689 7 SEG9-295 689 35 JUL. 27, 2 Version:.
. DISCLAIMER The information appearing in this publication is believed to be accurate. Integrated circuits sold by Sunplus Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. SUNPLUS makes no warranty, express, statutory implied or by description regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement. FURTHER, SUNPLUS MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. SUNPLUS reserves the right to halt production or alter the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. Products described herein are intended for use in normal commercial applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by SUNPLUS for such applications. Please note that application circuits illustrated in this document are for reference purposes only. 36 JUL. 27, 2 Version:.
. REVISION HISTORY Date Revision # Description Page MAY. 4, 2. Original JUL. 24, 2.. Delete PRELIMINARY 2. Renew to a new document format 37 JUL. 27, 2 Version:.