Computer Organization: Basic Processor Structure

Computer Organization: Basic Processor Structure James Gil de Lamadrid April 17, 2018

Chapter 1: Overview Computer Science students start by learning a high-level language. We study what is below the high-level code they write. We break our study into two areas: Computer Organization - the study of the implementation of the computer. Computer Architecture - the study of he interface to the computer.

High-Level Laguages Programming languages are classified by level. Low level languages are closer to the hardware. High level languages manipulate more abstract data structures. Examples Haskell - a functional language. C++ - an object-oriented language.

Machine Language Machine language is numeric. A machine instruction is a collection of fields, or numbers the represent the information given in the instruction. Instruction format: op-code, destination, source, constant Machine instructions operate on registers

Machine Language (cont.) Examples Source code: x = 5 + y * 3; Machine code: 1, 1, 2, 3 14, 1, 1, 5 Meaning: (Registers R1, and R2 are used to represent the variables x, and y, respectively.) R1 = R2 * 3 R1 = R1 + 5

Assembly Language Assembly language is a symbol version of machine language. Numbers forming parts of the machine instruction, are given symbolic names. The programmer is relieved of remembering the meanings of numbers. Examples Assembly code: mult R1, R2, #3 add R1, R1, #5

Compilers & Assembly Language High-level source code must be translated into machine code, to able to execute on hardware. Translation is done in several stages. In the first stage. Source code is often translated into Assembly code. The translation Process 1. Parse - the source code is translated into an abstract representation, often an abstract syntax tree (AST). 2. Generate Code - the AST is traversed, and as it is, code for each node assembly code for each node is written.

Compilers & Assembly Language (cont.) Examples = x + 5 * y 3 Example AST

Assemblers & Object Code The assembler translates assembly code to object code Object code is incomplete machine code. The assembler has trouble completing the machine code because of external references. A module containing a reference to a definition from another module has an external reference.

External References Module Q contains: extern int x; x = 5; Module Driver contains: int x; In assembly language, this would be Q: store x, #5 Driver (Allocate a word in memory for the variable x.): x:.word

External References (cont.) Translating the store into machine language might yield the following (We assume the op-code for store is 19, and x has been allocated memory location 50.): 19, 50, 5 But, the assembler only analyses one module at a time, and and cannot determine what memory location has been allocated to x. Instead the assembler produces the following object code instruction, with a blank left for the address of x, when it is eventually calculated. 19, x?, 5

Compiler vrs. Assembler The compiler parsing activity is complex. The code generation is complex, often producing several assembly instructions for each high-level statement. Assembler translation is little more than looking up symbols in a symbol table. The numeric field values are assembled into a full instruction.

The Linker & Executable Code The input to the linker is a set of object code files. The output is a single executable code file. Linker tasks: Resolve external references. Library search. Relocation of object code modules.

The Linker & Executable Code (cont.) Resolving External references: The linker sees both the module Q, and Driver. It can calculate the address of x in Driver, and fill in the blank in the Q module. Library searches: The linker pulls in modules from the library, and adds them to the executable code, in order to resolve some external references. Relocation: Modules are assigned an order in memory. The addresses in the module must be adjusted to reflect the module s position.

Library Search Example Examples (A0 is the argument register, used to pass an argument to a function, and RV is the return value register, used to pass a value back from a function.) Source code: z = sqrt(y); Assembly code: load A0, y call sqrt store z, RV

Relocation Example Module Driver has addresses 0-2,999. Module Q has addresses 0-1,999. Module q is placed after Mudule Driver. The base address of module Q is now 3,000. All addresses from Module Q must be modified by adding 3,000 to them.

The Loader The loader: Relocates the executable code. Initializes registers. The loader loads an executable program into its own section of memory called its workspace. Several programs (processes) can be active simultaneously. The processor executes small pieces of each process (called quanta) in rapid succession, making it appear that all processes in memory are running simultaneously. Depending on the location of the program workspace, addresses in the executable code will need to be altered yet again. Several registers, with special uses must be initialized before the program is started.

Initializing the PC Register The Program Counter (PC) is a register that contains the memory address of the next instruction to be executed. It must be updated each time an instruction is executed. Initially, it must be set to point to the base address of the program workspace. Current Instruction 2349 PC 2350 Memory 2000 workspace

Translation Summary

The Processor Levels of abstraction for Hardware The register transfer level (RTL), or behavioral level. The gate level, or structural level. Processor Behavior The processor repeatedly executes the machine cycle, that reads a single instruction from memory, and executes it. Steps in the machine cycle. 1. Fetch an instruction from memory. 2. Decode the instruction. (Split the instruction into fields.) 3. Execute the instruction.

Processor Structure The processor contains registers for storage. Collectively they are referred to as the register file. An arithmetic logic unit (ALU) performs operation of data stored in registers. The way the devices in the processor are connected is called the data-path. The circuit that controls the data-path, and all devices is the control unit.

The Data-Path Examples (Simple 2-register data-path.) R1 R1 + R2 R2 0 Corresponding circuit: R1 + 0 R2 Operations performed: 1. Add the contents of R1, and R2, and put the result in register R1. 2. Set register R2 to zero. Input the registers is calculated by circuitry called a computational unit.

Control Circuitry Examples (Simple 2-input control.) S 1 : R1 R1 + R2 S 2 : R2 0 Corresponding circuit: S 1 R1 LD + S 2 0 R2 LD Registers are opened for input when the load (LD) line is triggered by the control inputs. These descriptions are register transfer level (RTL). RTL shows a collection of connected devices.

Digital Circuitry Below the RTL level is the digital circuit level, or gate level. Gate level circuits are composed of gates. Digital circuits represent Boolean values as voltages (maybe 0V for false, and 5V for true). Gates compute Boolean functions, from input signals. Examples (AND gate: computes z = a b.) a b z

Combining Gates into Larger Functions Examples (Circuit that computes z = a b c) a b c z (Uses an OR gate, a NOT gate, or inverter.)

Chapter 2: Number, and Logic Systems Topics covered: Computer systems use the base two (binary) number system. This system is cumbersome for people. A system that is less for people, but still easily translatable to binary is hexadecimal. The circuitry in computer systems is based on Boolean algebra.

Numbers Binary has two digits: 0, and 1. A binary digit is called a bit. Numbers are stored in a collection of bits, of fixed width. The collection of bits is called a processor word. A 13 in a 4-bit word would be 1101. In an 8-bit word, it would be 00001101. Decimal expansion: 365 = 3 10 2 + 6 10 1 + 5 10 0. Digits: The leftmost digit is referred to as the high-order digit, and the rightmost digit is the low-order digit. Decimal is base 10 (the radix in the expansion is ten), and has ten digits: 0 through 9.

Binary Numbers Binary expansion: 00110101 = 0 2 7 + 0 2 6 + 1 2 5 + 1 2 4 + 0 2 3 +1 2 2 + 0 2 1 + 1 2 0 = 2 5 + 2 4 + 2 2 + 2 0 Converting from binary to decimal: simple do the calculations in the binary expansion in decimal. 00110101 = 2 5 + 2 4 + 2 2 + 2 0 = 32 + 16 + 4 + 1 = 53

Binary Numbers (cont.) Converting from decimal to binary. Examples (Converting 365 to binary using successive division.) Calculation Quotient Remainder 365 2 182 1 182 2 91 0 91 2 45 1 45 2 22 1 22 2 11 0 11 2 5 1 5 2 2 1 2 2 1 0 1 2 0 1

Understanding Successive Division Successive division in decimal: Examples Calculation Quotient Remainder 365 10 36 5 36 10 3 6 3 10 0 3 Each division pulls off one digit of the number. Low-order digits are extracted first. Division by 10 extracts decimal digits. Division by 2 extracts bits. To form a binary number outof the results of successive division, list the remainders from last extracted to first extracted, left to right. For the example that would be 365 = 101101101.

Hexadecimal Numbers Hexadecimal is base 16, with 16 digits: 0, 1, 2, 3, 4, 5, 6, 7, 8,, A, B, C, D, E, F. (A - F represent the digits 10-15.) To convert from hexadecimal to decimal, use the hex expansion. A3F = 10 16 2 +3 16 1 +15 2 0 = 2, 560+48+15 = 2, 623

Hexadecimal, & Binary Converting hex from/into binary. A single hex digit is four binary digits. To convert from hex to binary, replace each hex digit with its corresponding 4-bit representation. To convert from binary to hexadecimal, replace each group of four bits by the corresponding hex digit. Examples A3F = 1010 0011 1111 0010111010001011 = 0010 1110 1000 1011 = 2E8B

Adding Binary Numbers Examples (Decimal addition) 0 1 0 1 3 0 6 0 5 +1192 2557 You add column by column. In each column, you add two operand digits, and a carry-in digit. Each addition results in a sum digit, and a carry-out digit.

Adding Binary Numbers (cont.) Examples (Binary addition) 0 0 1 1 0 1 1 0 1 +0011 1110 Carry-in to the low-order column is 0. A carry-out of 1 occurs when the column sum is greater than or equal to 2. When a carry-out occurs, the sum digit is the sum minus 2.

Representing Negative Numbers Computers support two numbering systems: Unsigned integers - all bit configurations of teh word are used to represent non-negative integers. Signed integers - half of the processor word bit configurations are used to represent negative integers, and half are used to represent non-negative integers. For signed integers, the top bit is the sign bit. A 0 bit indicates a non-negative number. A 1 bit indicates a negative number.

Signed Notations Notation 107-107 Sign-magnitude 0 1101011 1 1101011 One s Compliment 0 1101011 1 0010100 Two s Compliment 0 1101011 1 0010101 Notations: Sign-magnitude - formed by writing the magnitude in binary, and tacking on the correct sign bit. One s compliment - formed by inverting every bit in the number. Two s compliment - formed by adding 1 to the one s compliment.

Signed Notations (cont.) Problem: sign-magnitude has two values of 0: +0: 00000000-0: 10000000 Problem: one s compliment also has two values of 0: +0: 00000000-0: 11111111 Examples (Two s compliment of +107 = 01101011.) One s compliment: 10010100 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 +1 10010101

Desirable Properties of Two s Compliment 1. There is only one representation of 0. (This can be seen by taking the 2 s comp. of 0.) (Taking the 1 s comp. of 0 and adding 1.) 1 1 1 1 1 1 1 1 0 11111111 +1 00000000 2. Negation is idempotent. ( a = a) 2 s-comp(00011010) = 11100110 2.s-comp(11100110) = 00011010 3. The negative of a number is it s additive inverse. (a + a = 0) As an example, we do 26 + 26. 1 1 1 1 1 1 1 0 0 00011010 +11100110 00000000

Shortcut 2 s Comp. Calculation A copy transformation is used to calculate the 2 s comp. of a binary number. rest 11001 1st 1 1 trail. 0's 00 00110 1 00 1's comp. as is as is

Boolean Algebra Boolean algebra is an algebra, like arithmetic algebra, in which we form expressions from operators, and operands. Arithmetic algebra, the expressions are used to describe functions that operate on numbers. In Boolean algebra the expressions operate on Boolean values: false, written a 0, and true, written as 1. Examples Arithmetic expression: x + 2 y Boolean expression: a b + a b ( + is the OR operator, and is the AND operator.)

AND, OR, and NOT Operations Truth tables: a b a b a + b 0 0 0 0 0 1 0 1 1 0 0 1 1 1 1 1 a a 0 1 1 0 The truth table shows the output of a Boolean function, for every possible value of input. It is split into an input half, and an output half. To produce all input values, count in binary, with each row having a different count in the input half. (In the table for AND, and OR, this would give 2-bit counts of 00, 01, 10, and 11.)

Other Common Boolean Operators Operators XOR, XNOR, NAND, and NOR. a b a b a b a b a + b 0 0 0 1 1 1 0 1 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 0

Operation Summary a b (AND): outputs 1 iff all of its operands are 1. a + b (OR): outputs 1 if any of its operands are 1. a (NOT): outputs 1 only if its operand is 0. a b (XOR): outputs 1 iff its operands are not equal. a b = a b (XNOR): outputs 1 iff its operands are equal. a b (NAND): outputs 1 only iff at least one of its operands is 0. a + b (NOR): outputs 1 iff all of its operands are 0.

Boolean Expressions, & Truth Tables Examples g = (ab + c) (ac + b) a b c ab ab ab + c c ac b ac + b g 0 0 0 0 1 1 1 0 1 1 0 0 0 1 0 1 1 0 0 1 1 0 0 1 0 0 1 1 1 0 0 0 1 0 1 1 0 1 1 0 0 0 0 1 1 0 0 0 1 1 1 1 1 1 0 1 0 1 0 1 1 0 0 1 1 0 1 1 0 1 0 0 1 1 0 1 1 1 1 1 1 0 1 0 0 0 0 1 Boolean operators are combined to form Boolean expressions. To build a truth table from a Boolean expression, form columns for intermediate subexpressions.

Boolean Expressions, & TruthTables (cont.) Examples (Converting from table to equation.) a b c h 0 0 0 0 0 0 1 0 0 1 0 1 0 1 1 0 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 1 h = abc + abc + abc + abc

Table to Equation h is 1 only if a is 0, b is 1, and c is 0, or a is 1, b is 0, and c is 1, or a is 1, b is 1, and c is 0, or a is 1, b is 1, and c is 1. These correspond to the rows in the truth table that have output of 1. The multiplicative terms that contain all input variables are called minterms. Minterms correspond to rows in the truth table. They are often referred to by there number. Reading the input values of a row as a binary number yields the number. For example for a = 0, b = 1, and c = 1, we get the minterm number 011, so abc is Minterm 3.

Don t Care Conditions An analogous incomplete function. B(n 1, k) + B(n 1, k 1), 0 < k n B(n, k) = 1, n = k 1, k = 0 When k = 0, the value of n doesn t matter - we don t care what it is; the function always returns 1. In Boolean algebra, we indicate don t care conditions with the symbol X.

Don t Care Conditions (cont.) Examples a b c f g 0 0 X 0 1 0 1 0 1 X 0 1 1 X 1 1 0 0 0 1 1 0 1 1 0 1 1 X 1 0 When the don t care is on the output, we do not care what the output is, and the designer can choose what to output, to optimize a circuit. When the don t care is on the input side, the given output is for both a 0, and a 1 value of the input. (The last line of the table is for both Minterm 110, and Minterm 111.)

Boolean Simplification using Identities Identities allow us to transform expressions into equivalent expressions. Examples (Arithmetic expression transformation using the distributive law.) (2a + 6) (2a 6) = (2a + 6) 2a (2a + 6) 6 = 2 2 a 2 + 6 2a (6 2a + 6 2 ) (Distributive Law: a(b + c) = ab + ac.) There are other identities that allow further transformation.

Boolean Identities Simplifying Boolean expressions allows us to build circuits that have fewer components, consume less power, are faster, and take less physical space. Identities: 1. Double negation: a = a 2. Contradiction: a a = 0 3. Tautology: a + a = 1 4. Commutativity: a + b = b + a, a b = b a 5. Associativity: a + (b + c) = (a + b) + c, a (b c) = (a b) c 6. Identity elements: a + 0 = a, a 1 = a 7. Zero elements: a + 1 = 1, a 0 = 0 8. Idempotency: a + a = a, a a = a

Boolean Identities (cont.) Identities: 9. Distributive: a (b + c) = a b + a c, a + bc = (a + b) (a + c) 10. DeMorgan s: a + b = a b, a b = a + b 11. Definition of XOR: a b = a b + a b DeMorgan s Law specifies how to bring a negation into a group. It also specifies two algebraic forms for the NAND, and NOR operators. The XOR operator has an algebraic equivalent. So does the XNOR operator: a b = ab + ab

Example Simplification using Identities Examples (ab + c) bc = ab + c bc + (ab + c) bc (R11) = (ab c)(b + c) + (ab + c)bc (R10) = (ab c)(b + c) + (ab + c)bc (R1) = (a + b) c)(b + c) + (ab + c)bc ((R10) = (a + b) c(b + c) + (ab + c)bc (R1) = c (a + b)(b + c) + bc (ab + c) (R4) = (c a + cb)b + (c a + cb)c + cabb + bc (R8, R4, R10) = b(c a + cb) + c(c a + cb) + 0 + bc (R4,R2, R7) = bc a + bcb + c c a + c cb + bc (R6, R9)

Example Simplification Using Identities (cont.) Examples = bc a + 0 + c a + cb + bc (R8, R4, R2, R7) = c a(b + 1) + b(c + c) (R6, R4, R9) = c a 1 + b 1 (R3, R7) = c a + b (R6) Algebraic simplification is difficult, requiring strategic planning. To allow automation of simplification, a more mechanical method is needed.

Boolean Simplification using Karnaugh-Maps There are only four Boolean functions with less than two parameters. 1. f 0 = 0 2. f 1 = 1 3. f identity (x) = x 4. f inverse (x) = x The smallest interesting functions have two independent variables. K-maps come in differing sizes, depending on the number of independent variables.

K-Maps of Two Variables Examples g = ab + ab + ab a b g 0 0 1 0 1 0 1 0 1 1 1 1 g 0 a 1 b 0 1 1 0 1 1 g = a + b

Combining Cells in the K-Map The 2-variable K-mapr is a square with one variable on each axis. Cell combination: 1. Adjacent cells that contain 1 can be combined. 2. Combined cells must form a rectangular group. 3. The size of a group must be a power of two. 4. The groups copied out must cover all cells that are 1. (Notice, however, that cells may be covered by several groups.) 5. The group names are ORed together, to form a simplified equation. 6. Group names are the AND of all variables that do not change their value, in the group. 7. The covering groups must be as large as possible.

K-Maps for Functions of Three Variables Examples a b c h 0 0 0 1 0 0 1 0 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0 h a 0 1 bc 00 01 11 10 1 0 0 1 1 1 0 1 h = c + ab

K-Maps for Functions of Three Variables (cont.) The 3-varaible K-Map is two 2-varaible K-maps stuck together.. The vertical axis is one of the variables, and the horizontal axis is both of the other two variables. The horizontal coordinates are listed in Gray code sequence. Between elements of the Gray code sequence, only one bit changes. K-Maps wrap around, both vertically, and horizontally. This means that the cells on the let are next to the cells on the right of the Karnaugh-map.

K-Maps for Functions of Four Variables Examples (Four variable) a b c d z 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 0 1 0 1 0 1 0 0 1 1 0 1 0 1 1 1 0 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 0 0 1 1 0 1 0 z 00 01 ab 11 10 cd 00 01 11 10 1 1 1 1 1 0 0 1 0 0 0 1 1 1 1 1

K-Maps for Functions of Four Variables (cont.) Examples (Four variable (cont.)) z = b + cd + a cd More than 4-variable K-maps become large, and it is best to use a software authoring tool to do simplification, rather than draw a map by hand.

Don t Care Conditions in Karnaugh-Maps Examples a b c m 0 0 0 1 0 0 1 X 0 1 0 0 0 1 1 1 1 0 0 X 1 0 1 1 1 1 0 X 1 1 1 0 m 0 a 1 bc 00 01 11 10 1 X 1 0 X 1 0 X

Don t Care Conditions in Karnaugh-Maps (cont.) Don t cares in the output can be assigned either a value of 0, or 1, to yield the best simplification, allowing larger groups to be pulled out of the K-map. Without using the don t cares. m = abc + abc + abc Using the don t cares. m = b + ac.

Chapter 3: Digital Circuitry Processors are digital circuits. Digital circuits have wires that carry one of two possible signals. low: a low voltage, like 0V. high: a high voltage, like 5V. we are not concerned with the actual voltage, and so we call these signals 0, and 1. How 0, and 1 are assigned to voltage is irrelevant to us. Types of digital circuits: Combinational circuits: they have no memory. The outputs can change immediately when the inputs are changed. Sequential circuits: they have memory. The outputs may not change when the circuit is remembering a previous value.

Combinational Circuits Logical gates: a b ab a b a + b a a a b a + b a b ab a b a + b a b a b (AND, OR, NOT (inverter), XOR, NAND, NOR, XNOR)

Using Gates Examples Boolean function. f = (a b)(b + c) Schematic. a b f c

Using Gates (cont.) Examples (cont.) Alternate drawing. a b f c

Buffers The triangle on the inverter is a buffer, and the open circle is the inversion element. Inverter types: a a a a a m c (inverter, simple buffer, tri-state switch)

Simple Buffer It boosts power. It is use in fanout situations, where splitting a signal weakens it. x x x x x x x x

Tri-State Switch The control line, c, when cleared, turns the flow off (sets the output to a state of high impedance, Z). The output has three states: Z, 0, and 1. a c m 0 0 Z 0 1 0 1 0 Z 1 1 1

Common Combinational Circuits The decoder - transforms a numeric code into trigger signals. The encoder - translates trigger signals into a code. The multiplexer - routes multiple inputs imnto a single output line. The adder - Adds binary signals that represent numbers.

The Decoder x 1 x 0 Dec 2-4 p 0 p 1 p2 p 3 A decoder is a switch. It turns on (sets) one of several output lines, and turns off (clears) the rest. The code x gives the index of the line to turn on. As an example, if x = 01, p 1 would be 1, and all other outputs would be 0. Decoder sizes: k 2 k. k is the number of inputs, 2 k is the number of outputs.

The Decoder (cont.) Examples (4-1 decoder) x 1 x 0 p 0 p 1 p 2 p 3 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 0 0 0 1 p 0 = x 1 x 0 p 1 = x 1 x 0 p 2 = x 1 x 0 p 3 = x 1 x 0 p 0 x 1 p 1 x 0 p 2 p 3

The Encoder p 0 p 1 p 2 p 3 Enc 4-2 x 1 x 0 An encoder checks several circuits, with only one circuit on (set), and reports a code indicating which circuit is. The code, x, gives the index of the line that is on. As an example, if p 0 = 0, p 1 = 0, p 2 = 1, and p 3 = 0, then the output x would be 10. Encoder sizes: 2 j -j.

The Encoder (cont.) Examples p 0 p 1 p 2 p 3 x 1 x 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 1 0 0 0 0 1 1 1 (Rows that are not shown are don t cares.) x 1 = p 2 + p 3 x 0 = p 1 + p 3 x 1 p 2 p 3 00 01 11 10 x 0 p 2 p 3 00 01 11 10 00 X 1 X 1 00 X 1 X 0 01 p 0 p 1 11 0 X X X X X X X 01 p 0 p 1 11 1 X X X X X X X 10 0 X X X 10 0 X X X

Encoder Schematic Examples (cont.) p 0 p 1 x 0 p 2 x 1 p 3

The Multiplexer (MUX) i 1 i 0 i 3 i 2 MUX 4-1 p s 1 s 0 A MUX routes one of several inputs to a single output. Only one input is allowed to pass through. The other inputs are stopped. The input allowed through is specified by the code s. As an example if s = 11, the output p would be whatever is on the line i 3. MUX sizes: 2 k 1. Width of the selector line s: k bits.

The Multiplexer (cont.) Examples i 0 i 1 i 2 i 3 s 1 s 0 p 0 X X X 0 0 0 1 X X X 0 0 1 X 0 X X 0 1 0 X 1 X X 0 1 1 X X 0 X 1 0 0 X X 1 X 1 0 1 X X X 0 1 1 0 X X X 1 1 1 1 p = i 0 s 1 s 0 +i 1 s 1 s 0 +i 2 s 1 s 0 +i 3 s 1 s 0 (Simplification is either by K-map, or by copying out each minterm, ignoring the don t care conditions.)

MUX Schematic Examples (cont.) i 0 i 1 i 2 i 3 s 1 s 0 p

MUX Composition Examples (4-1 MUX from 2-1 MUX s) i 0 i 1 MUX 2-1 The MUX s are structured into a tournament, in the process called interleaving. i 2 i 3 MUX 2-1 MUX 2-1 s 0 s 1 p The low-order bit, s 0, is used to choose the between odd, and even indexes, in the first round. The high-order bit, s 1, chooses between the two first-round-heats, in the final round.

The Adder c in 0 1 a 0 1 +b +1 +1 sc out 01 11 a b c in + s c out An adder adds three 1-bit numbers, a, b, and c in, to form a sum bit, s, and a carry bit, c out.

The Adder (cont.) c in a b c out s 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 s = c in a b c out = c in a + c in b + ab Checkerboard pattern for c out : XOR - odd parity cell coordinates (the odd function). XNOR - even parity cell coordinates (the even function). c out c in ab s 00 01 11 10 ab 00 01 11 10 0 0 0 1 0 0 0 1 0 1 1 1 cin 1 0 1 1 1 0 1 0

Adder Schematic a b c out c in s

The Ripple-Carry Adder To add multi-bit numbers we use several adders, one per column of the long addition problem, to add the a operand, b operand, and the carry-in. The carry-out becomes the carry-in of the next column. 1 1 1 1 0 1 1 0 1 +1101 1000 Notice that the carry ripples up from the bottom column, to the top. (The calculation of one column has to wait until the calculation of the previous column is complete.)

The Ripple-Carry Adder (cont.) c in a 0 + 0 s 0 b 0 a 1 + 1 s 1 c in b 1 a 2 + 2 s 2 a b 4 4 + 4-bit 4 s b 2 c out a 3 b 3 + 3 s 3 c out (4-bit bus line in the interface diagram indicate inputs of four lines.)

Sequential Circuits Sequential circuits are called sequential because the flow through a sequence of states. Code example: sum = 0 for i = 1 to n do sum = sum + i The state is the variables, and their values.

The Clock The clock is a device that produces regular beat type signal. 1 period 0 t The signal has a rising edge, and a falling edge. The time for one cycle is called the period. The frequency is the number of cycle per second. F = 1 P, where F is the frequency, and P is the period. The unit of measurement for frequency is a Hertz. 1 Htz = (1 cycle) / (1 second). (50MHtz = 50,000,000 cycles per second.)

The Clock (cont.) The clock is used to synchronize the state changes of sequential circuits. On of the two signal edges is designated as the trigger edge. All all state changes occur on the trigger edge. This simplifies the interaction between circuits. In our discussion we assume that the trigger edge is the rising edge. Although must circuitry in the processor are synchronized, there are a small number of asynchronous circuits. Not having to wait for the trigger edge for a state change helps speed up asynchronous circuitry.

Storage Devices Types: The latch - an unclocked device that stores one bit. The flip-flop - a 1-bit clocked storage device. Device subtypes: D-type J-K-type

The D-latch D C D-latch Q Q The D-latch is controlled by the input C. When C = 1, the latch is loaded with the value D. When C = 0 the latch locks its current value, ignoring D. The output Q is the value stored in the latch. D-latch exitation table: D C Q (1) X 0 Q (0) 0 1 0 1 1 1 (Q (0) - old latch value, Q (1) - new latch value)

The D-latch (cont.) Examples Example timing diagram for the D-latch. D C Q

The D-flip-flop D Clk > D Q Q On the D-flip-flop, the control signal is the clock. The flip-flop only loads exactly at the trigger edge. D-flip-flop excitation table: D Clk Q (1) X / Q (0) 0 0 1 1 (Arrows indicate passing trigger edge.)

The D-flip-flop (cont.) Examples Example timing diagram for the D-flip-flop. D Clk Q

The J-k Storage Devices J K J-K-latch Q Q J K Clk > J-K Q Q J-K excitation tables. J K Q (1) 0 0 Q (0) 0 1 0 1 0 1 1 1 Q (0) J K Clk Q (1) X X / Q (0) 0 0 Q (0) 0 1 0 1 0 1 1 1 Q (0)

The J-K Storage Device (cont.) Operations of the J-K Device: Lock: The device keeps its current value. This operation is specified with J = K = 0. Set: The value of the device changes to 1. This operation is specified with J = 1, K = 0. Reset: The value of the device changes to 0. This operation is specified with J = 0, K = 1. Compliment: The value of the device is toggled from 0 to 1, or from 1 to 0. This operation is specified with J = K = 1.

Flip-Flops with Extra Pins LD D Clk > D Q Q ST CL The set pin (ST) is asynchronous (changes do not wait for the clock pulse, but occur instantly). It initializes the flip-flop to 1. The clear pin (CL) is also asynchronous, and initializes the flip-flop value to 0. The load pin (LD) disables the clock signal, locking the value of the flip-flop.

Flip-Flops with Extra Pins (cont.) It is possible to implement the LD line on flop-flops that do not have a load input, using a feedback loop. D 1 0 Clk > D Q Q LD

Sequential Design using the FSM The tool for sequential circuit design is the finite state machine (FSM). The state diagram is a graphical representation of an FSM. Examples (FSA0) 1 00/1 0 11/0 1 0 1 0 01/1 10/1 1 0 States are the circles. Their labels are S/P, where S is the state number, and P is the output. Transitions are the arrows. They are labeled with I, the input. Transitions from a given state must have mutually exclusive labels.

The FSM and State Diagrams Examples (FSA0 (cont.)) The interface for FSA0. i FSA0 p Clk > Examples (FSA1) The FSM shows the output at each state, and the transition form one state to the next, on the clock pulse, and based on the input. 01, 10 0/10 1/01 01, 11 00, 10 00, 11 a b Clk > FSA1 c 0 c 1

The FSM and the State Transition Table The state transition table is a tabular representation of the state diagram. Examples (FSA0) i Q (0)1 Q (0)0 Q (1)1 Q (1)0 p 0 0 0 0 1 1 0 0 1 0 1 1 0 1 0 0 0 1 0 1 1 0 0 0 1 0 0 0 0 1 1 0 1 1 0 1 1 1 0 1 1 1 1 1 1 1 1 0

The FSM and the State Transition Table (cont.) The table has an input half, and an output half. In the input half you list the circuit inputs, and the bits of the current state number, Q (0). In the output half you list the next state, Q (1), and the circuit outputs. Each row represents a transition. Circuit output is based on the current state.

The FSM and the State Transition Table (cont.) Examples (FSA1) The transition table for FSA1. a b Q (0) Q (1) c 1 c 0 0 0 0 0 1 0 0 0 1 1 0 1 0 1 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 0 1 1 1 0 1 1 0 1 1 1 1 0 1

State Diagrams, and Transition Tables; Building One Representation from the Other From table to diagram. Lay down states using numbers from the current state column. Fill in outputs from the output columns. Draw arrows, one per row in the state table, from the current state to the next state. Fill in the input labels on the diagram, from the input columns in the table.

State Diagrams, and Transition Tables; Building One Representation from the Other (cont.) From diagram to table. Create the state table heading, listing out the input variables, the bits of the current state number, the bits of the next state number, and the output variables. Fill in all possible bit configurations on the input half of the table. On each row, fill in the output for the current state. On each row, fill in the next state, using the arrow in the state diagram corresponding to the row in the transition table. Bits in the state number: for m states, you will have log m bits.

Moore versus Mealy Machines A Moore machine associates output with the current state only. A Mealy machine associates output with the current state, and the input. The result, in the Mealy diagram, is that the output label is on the transition, and not the state. Examples (Mealy machine for FSA1) 00/10, 10/10 01/10, 10/10 0 01/01, 1 11/01 00/01, 11/01

Implementing a Sequential Design The Structure of a sequential circuit. Input Control Q (1) Register > Output Q (0) The register is a collection of flip-flops that store the current state number. The control circuit is a combinational circuit that calculates the output, and the next state.

Implementing a Sequential Design (cont.) Examples (FSA0) Equations for next state, and output are derived using K-maps, in he usual way. Q (1)1 = iq (0)0 + iq (0)1 = i(q (0)0 + Q (0)1 ) Q (1)0 = i Q (0)1 + iq (0)1 + Q (0)1 Q (0)0 p = Q (0)1 + Q (0)0 Use one flip flop to stoer each bit of the current state number. The input of the flip-flop is the next state, and the output of the flip-flop is the current state.

Implementing a Sequential Design (cont.) Examples (FSA0 (cont.)) Schematic of FSA0. Q (1)0 Q (0)0 i > Q (1)1 > D 0 D 1 Q (0)1 p

Implementing a Sequential Design (cont.) Examples (FSA1) Equations. Q (1) = ab + aq (0) b + aq (0) b = ab + a(q (0) b) c 1 = Q (0) c 0 = Q (0) Schematic. a b > D c 0 c 1

Sequential Circuit Analysis Going from schematic to FSM. Reverse the procedure used in design. Examples Schematic: z > D 0 p > D 1

Sequential Circuit Analysis (cont.) Examples (cont.) Equations (by following connections in the schematic): p = Q (0)0 Q (0)1 Q (1)0 = zq (0)0 Q (1)1 = Q (0)0 +zq (0)1 Table: z Q (0)1 Q (0)0 Q (1)1 Q (1)0 p 0 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 0 1 1 0 1 1 1 0 0 1 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 1 1 0 1

Sequential Circuit Analysis (cont.) Examples (cont.) State Diagram (copy out rows as transitions): 1 00/1 01/0 0 0,1 0 11/1 1 10/0 0,1

Common Sequential Circuits Used to store multiple bit binary numbers. They use one flip flop to store each of the bits. Bit numbering: x = 1100 = x 3 x 2 x 1 x 0 Register types. Parallel load register. Shift register. Counter.

The Parallel-Load Register It s a multi-bit flip-flop. The LD input causes the MUX s to feed the value back, for a lock operation, or feed in a new value, for a load operation. Q 3 Q 2 Q 1 Q 0 D 3 D 2 D 1 D > > 0 > > 0 0 0 0 d 3 1 d 2 1 d1 1 d 0 1 LD

The Shift Register The input SH controls the operation: SH = 0, to lock the register, and SH = 1 to perform a shift. Input MUX s implement the operations with feedback loops, or the output of the adjacent bit. Shift-left c out C in Shift-right c in cout

The Shift Register (cont.) SH c in > Shl-Reg 4-bit 4 Q c out c out Q 3 Q 2 Q 1 Q 0 D 3 D 2 D 1 D > > 0 > > 0 0 0 0 1 1 1 1 SH c in

The Counter An input IN chooses an operation: IN = 0, the register is locked, and IN = 1, the register increments. The increment takes the register through the sequence 0000, 0001, 0010,..., 1111, 0000,..., one value per clock cycle. It uses an adder to increment. The input MUX now chooses between a feedback, or the adder.

The Counter (cont.) IN > Count 4-bit 4 Q c out Q 3 Q 2 Q1 Q 0 D 3 D 2 D 1 D > > 0 > > 0 0 0 0 0 0 0 0 + 1 1 + + 1 1 + 1 c out IN

The Standard Register LD IN CL d Reg 4 > 4-bit 4 Q c out 4 4 0000 d 4 4 0 1 2 3 4 > D 4 4 4 4 + Enc 2 Q 0001 c out CL IN LD

The Standard Register (cont.) We combine an increment, a load, and a clear operation to form a register that we use regularly. All 4-bit inputs are are shown by abrevieted notation, using a bus. A MUX chooses between one of four computation units that calculate one of the operations. An encoder turns the three trigger lines into a code that can be used to operate the MUX.

Chapter 4: Devices and the Bus Devices that interact with the processor are mostly external to the processor, but on the motherboard Device types (collectively knwn as external devices): Memory devices. Peripheral devices. Connection: Direct connection - the processor can be connected to each device using dedicated connections. Bus connection - the processor is connected via a single shared line to all devices. Comparison: Wiring complexity - Bus connection produces simpler wiring. Concurrent communication - Direct connection allows several devices to communicate with the processor, simultaneously.

Devices and the Bus (cont.) CPU Mem IO Dev IO Dev Bus

Memory Stores multi-bit values. Each storage device is called a word. The memory unit has a size: l w, where l is the length of the unit (number of words), and w is the width of the unit (number of bits per word). Words are given addresses (numbers) to identify them. Address 0 1 2 3 4 5 6 7 Memory 8x4

Memory (cont.) Memory operations: Read: produce the contents of a particular memory location. Write: store a given value in a particular memory location. Memory types: Read Only Memory (ROM). (Allows a read operation only) Random Access Memory (RAM). (does both read and write operations) A D in 3 4 RAM 8x4 4 D out A 3 ROM 8x4 4 D out W E E

Memory Types ROM s are used, for example, to provide manufacturer information to an OS. (like the BIOS) RAM s are the standard working memory in a computer. Inputs A - the address of the word. D in - the input data for a write operation. W and E - control the operation on a RAM unit. Assert W for a write operation, and assert E for a read operation. Dout - the output data for a read operation.

Memory Types (cont.) Performing a read operation. 1. Assert he desired address on the A port. 2. Strobe the E line, and allow time for the data to present itself on the D out port. Performing a write operation. 1. Set up the inputs. 1.1 Assert the desired address on the A port. 1.2 Assert the desired data on the D in port. 2. Perform the operation by strobing (setting and the then resetting) the W line.

Memory Composition The size of a memory unit is 2 k m, where 2 k is its length, and m is its width. The unit would have a k-bit address port, to represent addresses between 0 and 2 k. Examples An 8 4 memory has eight 4-bit words. An address is 3 bits (8 = 2 3 ). to specify addresses between 0 and 7 (000-111). Composition types: Horizontal - Creating a wider memory unit out of thinner units. Vertical - Creating a longer memory unit out of shorter units.

Horizontal Composition Examples (Building an 8 4 RAM from two 8 2 RAMs.) RAM 8x4 3 2 1 0 RAM 2x(8x2) 3 2 1 0 2 D out,3-2 A D in 3 4 RAM 8x4 4 D out A D in,2-3 3 RAM 8x2 RAM 8x2 2 D out,1-0 D in,1-0 E 3 W E

Vertical Composition Examples (Building an 8 4 ROM from four 2 4 ROMs.) ROM 8x4 ROM 4x(2x4) 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 A 3 ROM 8x4 4 D out A 0 ROM 2x4 4 E A 2 0 Dec 1 ROM 2x4 4 A 1 2-4 2 3 ROM 2x4 4 ROM 2x4 4 4 E D out

Vertical Composition (cont.) The ROM is split into four sections. Each section is covered by a small ROM unit. We number the small units, 0-3, for our example. The 3-bit address is split into a unit number, and an internal address. Unit # (The field sizes depend on the composition being performed.) A 2 A 1 A 0 Int. Address The unit number is used to enable the correct ROM, and the internal address is fed into the ROM as its address signal. This, where the unit number is the high-order part of the address, is called high-order interleaving. When the unit number is the low-order part of the address, that is called low-order interleaving.

Internal Memory Structure D in 2 LD 2 Reg 0 A 2 Dec 2-4 0 1 2 LD Reg 1 2 3 LD Reg 2 2 LD Reg 3 2 2 D out W E

Internal Memory Structure (cont.) Shown is a 4 2 RAM. Each word is stored in a register. An address decoder turns an address into trigger lines. AND gates check for the the selected row, and the correct operation. The input, D in, presents itself at each register, and enters the register only if its LD input is triggered. The output, from each row is allowed onto the output bus, D out, only if the tri-state switch is opened. A ROM has the same output structure, and no input.

RAM Types RAM units can be classified as follows. Dynamic RAM (DRAM). It uses capacitors to store bits. (Charged is a 1, and depleted is a 0.) Capacitors leak over time. A capacitpor memory has to be rewritten (refreshed) to persist. Static RAM (SRAM). It uses latches to store Boolean values. Comparison: Access Speed: DRAM units tend to be slower than SRAM. This is because charging capacitors requires a latency. Density: Capacitors can be built much smaller than gates, and the DRAM can be built more compactly than the SRAM. Cost: Storage using capacitor technology is cheaper to build than storage using the technology used in gates.

ROM Types ROM: Standard read-only memory. Contents are burnt in on creation. PROM: Programmable ROM. Chips are originally blank. Using a PROM burner you ip;oad its contents. Once burnt, it is permanent. EPROM: Erasable PROM. The chip contains a window, through which you shine UV light, which erases the chip contents. So, the chip can be reprogrammed. EEPROM: Electrically EPROM. The chip is erasable, like the EPROM, only with a special high voltage input pin.

Word and Byte Addressing The same memory is used o store both integers, and characters, which have radically different sizes. A character requires 8 bits (1 byte) to represent 256 possible keyboard characters. Use a combined memory. For a 16-bit integer, each word would be 16 bits. It would be split into 4 bytes, allowing us to store 4 characters in it. Each byte has an address. Word addresses are multiples of 4. Byte addresses are multiples of 1

Word and Byre Addressing (cont.) Addressing for a 16 4 memory: RAM 8x16 0 2 4 6 8 10 12 14 1 0 byte Instructions to store data into a byte movb M[7], R0 or a word movw M[6], R0

Machine Byte Order Addressing Schemes little-endian big-endian little-endian big-endian 3 2 1 0 0 1 2 3

Peripheral Devices Input devices. These are devices from which the processor reads data. The keyboard and pointer devices like the mouse are examples of input devices. Output devices. These are devices to which the processor writes data. The monitor and printer are examples of such devices. I/O devices. These are devices that combine both an input element and an output element. The processor can write to, and read from, these devices. An example of such a device is a disk drive.

Peripheral Device Types LD Reg Out Output Device E D in In Input Device D out Reg I/O I/O Device D out D in LD E

Device Interface The output device has a register that is loaded with the output value. The input device has a switch that lets the input out of the output port. The I/O device has both interfaces.

Device Polling Problem: There is no way to determine when a device is ready with new input/output. Solution: Every device has a READY bit associated with it. The READY bit is raised to a 1 by the device, when the device is free. When the read/write operation is performed, the RFEADY bit is lowered to 0 by the processor. Before the processor accesses the device, it checks the READY bit to see if it is 1, indicating the device is ready.

Interrupts When using device polling, the processor spends a lot of time busy waiting. (In a loop where it checks the READY bit, over and over and over.) With interrupts, the processor is sent a signal when the READY bit is raised. It no longer needs to busy wait. The processor can now work on another process, while processing I/O. When an in interrupt is received, the processor suspends the process it is executing, and jumps to an Interrupt Service Routine (ISR). The ISR handles the interrupt request. When the ISR is done, the processor jumps back to where it left off in the other process.

Interrupts (cont.) Interrupts have many causes. A CAUSE register is used by the device to pass the ISR a cause code, so that the ISR knows how to Memory ISR PC User Program handle the interrupt.

Software Interrupts Even a user program can request to be interrupted. (A software interrupt.) Why? System security: User mode The process in user mode is limited in what operations it can perform. Kernel mode The process in kernel mode is unlimited. To do a kernel operation, the user program (operating in user mode) it requests a service of the OS by asking to be interrupted, and passing the ISR information on its request.

The CPU The processor is a device that executes the machine cycle over and over. Each time the machine cycle is executed, a single machine instruction is executed. Machine cycle: 1. Fetch. The PC contains the address of the next instruction to be executed. The instruction indicated by the PC is fetched into the CPU from memory, and the PC is updated. 2. Decode. The processor determines the operation to be performed, and the location of the operands required. 3. Execute. Any operands are fetched, the operation is performed, and the result is written to the destination.

Bus Communication Bus structure: A D Ct Rd Wt bus

Bus Use There are three buses: The data bus carries data from the processor to the device. It also carries data from a device to the CPU. The address bus carries addresses to memory units. The control bus carries the control signals read, to input devices, and write, to output devices. How does a bus device know if a message is for it, or some other device?

Bus Addressing Every device has a collection of bus addresses that belong to it. The bus address is split into two fields: The unit number every device on the bus is given a number that identifies it. The internal address memory units are sent addresses for read and write operations.

Bus Addressing Example An 8 4 RAM unit; addresses range from 0000000 to 0000111. A 16 4 ROM unit; addresses range from 0010000 to 0011111. An input device with address 0100000. An output device with address 0110000. An I/O device with address 1000000.

Bus Addressing Example (cont.) Deduce: The unit number is 3 bits (there are 5 devices). The internal address is 4 bits (the largest memory unit is of length 16). The bus address is 7 bits. This is the size of the address bus. The data bus is of width 4 (all units are at must 4 bits wide). The RAM should perform a read operation only if the CPU sends a unit number of 000, and a read request. The RAM should perform a write operation only if the CPU sends a unit number of 000, and a write request.

Bus Addressing Example (cont.) The ROM performs a read when the CPU asks for a read operation on Unit 001. The input device performs a read when the request is for a read from Unit 010. The output device performs a write operation when the request is for a write operation on Unit 011. The I/O device performs a read or write when the that operation is requested on Unit 100. For each device control input we use 2 gates: 1. Addressing gate checks for proper unit number. 2. operation gate checks for the proper operation (read or write).

Example Memory Connection A D in RAM 8x4 W E D out A ROM 16x4 D out E A 3-0 A 3-0 A 7 4 A 6-4 4 4 D 4 A 6,5 A 4 Rd Wt

Example Peripheral Connection In E Reg LD Out 4 4 A D 7 4 A 6,4 A 5 A 6 A 5,4 Rd Wt A 6 A 5,4 4 4 Reg LD I/O E

Chapter 5: The Register Transfer Language Level RTL (register transfer langauge) provides a tool for describing circuitry at a higher level than the FSM or truth-table. The tools we have developed so far are structural descriptions. They describe the structure of a circuit. RTL is a behaviorla description. It describes the behavior of a circuit. An RTL description is a collection of µ-instructions. Each µ-instruction describes a circuit. A µ-instruction is composed of one or more µ-operations.

RTL Design A µ-instruction has two parts (separated by a colon): A data-path specification, describing how data flows through the circuit. A control part indicating when the µ-operations are performed. Examples (RTL implementation) T : R1 R2 > R2 > R1 LD T

RTL Design (cont.) Examples (Use of trigger gates to generate control.) ab + c : R1 0 CL a b c > R1

RTL Design (cont.) Examples ab : R1 R1 + R2, R2 3 LD a b > R1 + 3 > LD R2

RTL Design (cont.) Examples (RTL with input choice, using a MUX and OR gate.) ab : R1 R1 + R2 ab : R1 3 a b 3 0 1 > R1 LD + > R2

A Larger Example Examples (Use of decoder instead of trigger gates.) x y : R1 R1 + R3, R2 0 xy : R3 R3 + 1 xy : R2 R1, R0 R3 xy : R1 R0, R3 5 x y 0 1 Dec 2 3 LD LD R0 0 > 1 R1 > + 5 R3 R2 > > LD IN LD CL

RTL Analysis To generate an RTL description from a schematic: 1. Write down control signals, using the decoder values. For the previous example, Option 0 gives us xy, Option 1 gives us xy, and so on. 2. Follow the decoder trigger lines to determine the µ-operations performed. For example for Option 2, the trigger line triggers the LD line on R0, and the IN line on R3. This means that a µ-operation is performed on R0, and Another is performed on R3. 3. Follow the data-path lines to determine the exact µ-instruction. In the example the input port of R0 is connected to R3, giving us the µ-instruction xy : R0 R3, R3 R3 + 1 4. Repeat the procedure for all decoder options.

From Structural to Behavioral Description The method of transforming from circuit diagram to RTL is not universal. Here is a universal method. i Q (0)1 Q (0)0 Q (1)1 Q (1)0 p 0 0 0 0 1 1 0 0 1 0 1 1 0 1 0 0 1 1 0 1 1 0 0 0 1 0 0 0 0 1 1 0 1 1 0 1 1 1 0 1 1 1 1 1 1 1 1 0

Structural to Behavioral (cont.) Copy of each row as a µ-instruction. i Q 1 Q 0 : Q 1, p 1 i Q 1 Q 0 : Q 1, p 1 iq 1 Q 0 : Q 1, p 1 iq 1 Q 0 : Q 0, p 0 iq 1 Q 0 : Q 0, p 1 iq 1 Q 0 : Q 2, p 1 iq 1 Q 0 : Q 3, p 1 iq 1 Q 0 : Q 3, p 0

Problems with Reverse Engineering Building a circuit from this µ-program, with data-path and control, yields a poor design, compared to the original design. The mechanical translation looses semantic information.) Q 0 1 2 3 4 5 6 7 p 0 1 2 3 4 5 6 7 1 1 1 1 1 1 0 0 0 1 2 1 3 1 3 0 > i 2 2 2 2 2 2 2 2 2 2 LD 1

Common Processor µ-instructions RTL is good at describing high-level circuitry, but it can be used at all levels. Examples (Combinational Circuit: the MUX) s 1 s 0 : p i 0 s 1 s 0 : p i 1 s 1 s 0 : p i 2 s 1 s 0 : p i 3 Examples (Sequential Circuit: the J-K flip-flop) JK : Q 0 JK : Q 1 JK : Q Q Examples (Sequential Circuit: the counter) IN : Q Q + 1

Processor µ-instructions Arithmetic 1. Addition: X X + Y 2. Subtraction: X X Y 3. Increment: X X + 1 4. Decrement: X X 1 5. Transfer: X Y 6. Clear: X 0 Logic 1. AND: X X Y 2. OR: X X Y 3. NOT: X X 4. XOR: X X Y

Processor µ-instructions (cont.) Shift 1. Logic Shift left: X shl X 2. Logic Shift right: X shr X 3. Circular shift left: X cir X 4. Circular shift right: X cil X 5. Arithmetic shift left: X ashl X 6. Arithmetic shift right: X ashr X Memory 1. Read: X M[AR] 2. Write: M[AR] X

Processor µ-instructions (cont.) Logic operations are bitwise. (they are done column by column.) 0110 0 1 1 0 0101 0 1 0 1 0100 0 1 0 0 Shifts of 1110 1. shl: 1100 2. shr: 0111 3. cil: 1101 4. cir: 0111 5. ashl: 1100 6. ashr: 1111 Memory addresses are specified using the address register (AR). To fetch an instruction from the location specified by the PC requires two µ-operations. AR PC X M[AR]

Shift types Left Right shl c out 0 0 shr c out cil cir c out cout ashl ashr c out 0 cout

Algorithmic Machines RTL is typically considered a declarative language: it specifies how a circuit is put together. We can, however, use it as a procedural language: specifying a sequence of steps, or actions. Examples (The Teapot Example) Design a control circuit for a teapot. S T > tea X H