CPLD board www.matrixtsl.com EB020
Contents About this document Board layout General information Circuit description Protective cover Circuit diagram 2 4 5 7 Copyright
About this document This document concerns the EB020 E-blocks CPLD board. 1. Trademarks and copyright PIC and PICmicro are registered trademarks of Arizona Microchip Inc. E-blocks is a trademark of Matrix Technology Solutions Ltd. 2. Disclaimer The information provided within this document is correct at the time of going to press. Matrix TSL reserves the right to change specifications from time to time.. Testing this product It is advisable to test the product upon receiving it to ensure it works correctly. Matrix provides test procedures for all E-blocks, which can be found in the Support section of the website. 4. Product support If you require support for this product then please visit the Matrix website, which contains many learning resources for the E-blocks series. On our website you will find: How to get started with E-blocks - if you are new to E-blocks and wish to learn how to use them from the beginning there are resources available to help. Relevant software and hardware that allow you to use your E-blocks product better. Example files and programs. Ways to get technical support for your product, either via the forums or by contacting us directly. Board layout 1 20 6 7 4 5 2 9 1 14 10 12 11 19 15 16 17 1 Copyright 1. Power connector 2. USB connector. Power LED indicator 4. USB LED indicator 5. USB host device 6. Programming buffer 7. CPLD crystal. Bridge rectifier 9. Power screw terminals 10. Power switch 11. Power mode switch (PSU/USB) 12. ALTERA CPLD and socket 1. Port - CPLD1 14. Port - CPLD2 15. Port - CPLD 16. Port - CPLD4 17. Port - CPLD5 1. Port - CPLD6 19. Port - CPLD7 20. ALTERA JTAG header
General information This CPLD board connects to your PC via a standard USB cable to provide you with a low cost CPLD development board and programmer. The board is fully compatible with a wide range of E-blocks which makes it an extremely flexible platform for learning and developing projects. Please note the EB020 only works with 2bit operating systems, there are no 64bit drivers available. The CPLD board allows in-circuit programming of an ALTERA CPLD device. This board is used together with Altera s free and comprehensive downloadable CPLD program, Quartus II. The board can be programmed using various programming techniques such as Schematic Entry, Block Diagram and Hardware Description Languages (HDLs such as AHDL, VHDL and Verilog). It provides clean access to all available lines on the relevant CPLD device. The USB driver for the EB020 is available from the Matrix Learning Centre. Please see the instructions in the driver zip file for the process to install the USB driver. Features E-blocks compatible Used as a programmer and as a development board Full suite of programming software 25MHz Xtal operation 7 full ports Clock circuit x 1 USB programming circuitry C5 C6 USB programming circuitry J4 14V 0V +V OUT +V OUT +14V J2 J1 Power supply SW1 regulation ON OFF 5V D4 POWER INDICATOR 2 TDO TDI TMS TCK Socketed CPLD device CPLD1 CPLD2 CPLD [J5] [J6] [J7] CPLD4 CPLD5 CPLD6 CPLD7 [J] [J9] [J10] [J11] 4 Copyright
Circuit description The EB020 CPLD board circuit can be observed on page. The CPLD board solution is made up of two parts: a circuit board that allows slave CPLD devices to be programmed, and the program to be executed seamlessly, and the Windows based programming utility Quartus II web edition. 1. Power supply The board can be powered from a 14V supply. The regulation circuitry will withstand unregulated 20V as a maximum input voltage and 7V as a minimum. If you are using a DC power supply then you should use a 14V setting. Power can Location Pin_1 be connected using the 2.1mm power jack (positive outer), or the screw terminal connectors J1, J2. The two +V OUT screw terminals are supplied for powering other E-blocks, supplying approximately +5V. The regulator will supply up to 400mA via all outputs. LED D4 will indicate that power is connected to the board and that the voltage regulation circuitry is fully functional. Please note connector J4 is directly connected to the J1 screw terminal pin 1 labelled +14V therefore any voltage input to J4 will also be available direct from pin 1 of J1. Remember that other E-blocks will have to receive +5V by placing a connecting wire from the +V OUT screw terminal of the multiprogrammer to the +V screw terminal of each E-block that requires a voltage. 2. The CPLD The CPLD that comes with this board is an 4-pin PLCC Altera MAX 7000 series device. The device has 2500 usable gates with 12 macrocells available. The device has a maximum of 6 lines (note some of them are multiplexed for dual use). This CPLD board utilizes 56 pins, thus providing plenty of resources to set up both simple and complex projects.. Crystal operation The board is fitted with a 25MHz crystal. To make use of the 25MHz crystal, your design must include a not 5 Copyright Option Value clkin INPUT VCC gate function between the crystal input (Pin 1) and the crystal output (Pin 0). The system clock can be taken from the output of the not gate. The following diagram shows the block schematic, using Quartus, for the necessary circuit to enable the 25MHz crystal. The clk_in input is connected to Pin location 1; this is the physical pin for the crystal input. The clk_out input is connected to Pin location 0; this is the physical pin for the crystal output. The output of the not gate is used as a system clock to clock all other parts of the circuit. NOT inst2 Use as system clock OUTPUT Option Location clkout Value Pin_0 Drawing showing the clock schematic block to enable 25MHz The following is an example Verilog code to enable the crystal in the design. This design uses the same name as the clock schematic above. /********* Crystal oscillator *********/ always @ (clk_in) begin clk_out =!clk_in end /************************************/ An example of VHDL code to use the crystal in your design is shown below. Again this code uses the same names as the above clock schematic. ------------------------------ entity clock_gen is port ( clk_in: in std_logic; clk_out: out std_logic); end clock_gen; architecture behave of clock_gen is begin process (clk_in) begin clk_out <= not clk_in; end process; end behave; ------------------------------
4. DIL headers and ports The CPLD DIL headers (J12, J1, J14 and J14) are wired to the exact replica of the CPLD pins. The s surrounding these 4 DIL header pins shows pin of the CPLD device each header pin is connected to. Please note that the 4 header blocks have 22 pins each and therefore one is not connected, which is marked with an X on the board. There are 56 dedicated lines fed out to 7 D-type sockets grouped in ports, each port having lines. The pin-out of these ports can be found below.! Note all available are clean signals - this means there is no protection. The user must be aware of this when selecting the functionality of the pins. Avoid connecting +V directly to an pin or two outputs pins directly together - this can damage the CPLD device. 5. USB circuitry The EB020 CPLD FPGA board makes use of a USB socket to provide the programming functionality. Note that the Altera Quartus II software thinks that it is talking to a parallel port or LPT port when it is talking to the Byteblaster cable. This is normal as the USB driver chip is actually emulating a parallel port. CPLD2 1 15 2 16 17 4 1 5 20 6 21 7 22 24 9 CPLD4 1 5 2 6 7 4 9 5 40 6 41 7 44 45 9 EPM712 pin EPM712 pin CPLD 1 25 2 27 2 4 29 5 0 6 1 7 4 9 CPLD5 1 46 2 4 49 4 50 5 51 6 52 7 54 55 9 EPM712 pin EPM712 pin 6. Device pin out The following diagram shows the pin-out of the Altera MAX EPM12SLC4 device that comes with this board. 7. Port connections The following tables show the pin connections on the 9-way D-type ports. This should be used for correctly setting the Pin location in the Quartus software...v operation This board is not compatible with.v systems. CPLD1 1 4 2 5 6 4 5 9 6 10 EPM712 pin () (TDI) () (TMS) 12 1 14 15 16 17 1 19 20 21 22 2 24 25 26 27 2 29 0 1 2 (1) VCCINT INPUT/OE2(GCLK2) (2) INPUT/GLCRn INPUT/OE1 11 10 9 7 6 5 4 2 INPUT/GCLK1 (1) 1 4 2 1 0 79 7 77 76 75 EPM7064 EPM7064S EPM7096 EPM712E EPM712S EPM7160E EPM7160S 74 7 72 71 70 69 6 67 66 65 64 6 62 61 60 59 5 57 56 55 54 (TDO) () (TCK) () 7 11 12 4 5 6 7 9 40 41 42 4 44 45 46 47 4 49 50 51 52 5 9 (1) VCCINT (1) 6 Copyright 4-pin PLCDD
CPLD6 1 56 2 57 5 4 60 5 61 6 6 7 64 65 9 EPM712 pin CPLD7 1 67 2 6 69 4 70 5 7 6 74 7 75 76 9 EPM712 pin Protective cover Most of the boards in the E-blocks range can be fitted with a plastic cover as an optional extra. These covers are there to protect your E-blocks board therefore extending the life of the board. The covers also prevent the removal of external components while still allowing for the adjustment of applicable parts on the board. 12mm M spacers, anti-slip M nuts and 25mm M bolts can be used to attached the cover to the board. These are not included but can be bought separately from our website. The order code for the EB020 CPLD board is EB720. 7 Copyright
Circuit diagram Copyright
Matrix Technology Solutions Ltd. The Factory Gibbet Street Halifax, HX1 5BA, UK t: +44 (0)1422 2520 e: sales@matrixtsl.com www.matrixtsl.com EB020-0-4