CPLD Experiment 4 XOR and XNOR Gates with Applications Based on Xilinx ISE Design Suit 10.1 Department of Electrical & Computer Engineering Florida International University
Objectives Materials Examining the characteristics of XOR and XNOR gates. Demonstrate applications of XOR and XNOR gates Learn to use the VHDL approach to combinational logic design. Xilinx ISE software, student or professional edition v10.1 IBM or compatible computer with Pentium III or higher, 128MB RAM or more and 8GB or larger hard-drive. Xilinx Coolrunner 2 CPLD boards. Oscilloscope and function generator Discussion So far we have studied five basic types of gates: AND, OR, NAND, NOR and NOT. In some applications, it is convenient to use two other types of gates: XOR and XNOR. The XOR and XNOR gates have their own symbols and unique characteristics. Common applications for XOR and XNOR gates are: comparators, switchable inverter/buffers, parity generator/checkers and adder/subtractor. They can also be used to simplify Boolean equations. We will first discuss the properties of XOR and XNOR having two inputs. Gate Characteristics: 1. The XOR gate For a 2-input XOR gate, the output is High when the inputs are unequal. The output is Low when the inputs are equal. The Boolean equation for a 2-input XOR gate can be abbreviate as: However, the function definition remains the same. Symbol Boolean Equation Truth Table Inputs Output 2. The XNOR gate The output of an XNOR gate is the complement of that of an XOR. For a 2-input XNOR gate, the output is Low when the inputs are unequal but High when the inputs are equal. The Boolean equation for a 2-input XNOR gate can be written as: 2
The number of inputs for the XOR and XNOR gates can be two or more. The characteristics of XOR and XNOR gates can be extended to three or more inputs. We will examine the characteristics of 3-input XOR and XNOR gates. Symbol Boolean Equation Truth Table Inputs Output Section I: XOR and XNOR characteristics. Step 1: Creating a New Project 1. Select Start > Programs > Xilinx ISE Design Suit 10.1> Project Navigator. This will open up Xilinx ISE 10.1 s Project Navigator. A helpful tip of the day will come up. Click OK. 2. Select File > New Project. The New Project Wizard should appear. 3. Enter a location for the new project and a name. This will automatically create a subdirectory which stores all of the project s files. Call this project EXGATES. 4. Select schematic from the Top-Level Module Type List, which indicates that the top level file in your project will be of the type schematic. 5. Click on next to move to the project properties page. 6. Fill in the properties as follows: Family-> coolrunner2 cplds, Device ->XC2C256, Package ->TQ144, Speed Grade -> -7, Top Level Source Type -> schematic, Synthesis Tool -> XST, Simulator -> ISE Simulator and Preferred Language -> VHDL. When you are finished filling in the table, it should look like the following: 3
7. Click Next to proceed to the Create New Source Window in the New Project Wizard. Step 2: Create a Source In this section, you will be creating a simple modulo 16 counter. 1. Click New Source under Project to add one new source to you project. 2. Select schematic Module as the source type in the New Source dialog box. 3. Call the file exgates_sch. 4. Verify that the Add to project checkbox is selected. 5. Click Next followed by finish.. 6. Click yes to create the directory. 7. Click Next in the New Project Wizard. 8. Click Next again. 9. Click Finish in the New Project Wizard dialog box. ISE creates and displays the new project in the Sources in Project Window and adds the exgates_sch.sch to the project. 10. Double-click on the exgates_sch file in the Sources in Project window to open the file in the ISE schematic editor. 11. Draw the circuit likes the one seen below in the schematic editor by selecting symbols in the sources file and wire connections from the menu bar. 12. Once circuit is completed click on check schematic button. If there are no errors save the file. 4
13. Under sources select exgates_sch and then double click the button Implement design under processes. 14. Make sure there is no error and warnings. If the Process completes successfully, a green check mark will appear. If there were errors and the process failed, a red X will appear, a yellow exclamation point means that the process completed successfully, but some warnings occurred, and an orange question mark means that the process is out of date and needs to be run again. Look in the Console tab of the transcript window to see any errors or warnings that you may have produced. You can ignore the warnings, but not the errors. They must all be fixed before simulation or synthesis. Creating a Test Bench for Simulation This section describes how to create a test bench waveform containing the input stimulus you can use to stimulate the counter module. 1. Select the exgates_sch file in the Sources in Project Window. 2. Create a new source by selecting Project > New Source. 3. In the New Source Window, select Test Bench Waveform as the source type and call it exgates_tbw. 5
4. Click Next. 5. The Source File dialog Box shows that you are associating the test bench with the source, exgates_sch. Click Next. 6. Click Finish. 7. Initial timing and clock wizard appears. Select combinatorial under clock information and click next. 8. Click Finish to open the waveform editor. You may find it easier to work with this waveform if you un-dock it from ISE. To do this, click the Window button in the Menu Bar and select Float. To re-dock it, press the dock button in the Menu Bar of the Waveform Editor Window. The blue shaded areas are associated with each input signal. 9. Set the input pulse for A, B, C like shown in the figure below and save it. Step 6: Simulating the Behavioral Model 1. Select the test bench waveform in the sources in Project window under Sources for: Behavioral Simulation. 2. Click the + next to the Xilinx ISE Simulator and then Double-click the Simulate Behavioral Model process. This will then make ISE run the simulation to the end of the test bench. 3. To see the results, use the zoom buttons to see how the counter responds to the changes in direction. Print out your waveform and label it appropriately. 4. After checking the outputs X and Y, close the waveform. Step 11: Creating Configuration Data The final phase in the software flow is to generate a bitstream and configure the device (CPLD board). 1. Connect the CPLD board to the PC with an USB cable. 2. Select the exgates_sch source file in the Sources in Project window under sources for: Synthesis/Implementation. 3. Run the Generate Programming File process located near the bottom of the Processes for Source window. This will create a bitstream. This is the actual configuration data. 6
4. To download the design onto your device, double-click on the icon of adept. Then click Initialize Chain, select your design by click the icon. After that, click icon to download to your board. Figure shows the window when you download. 5. Use your target board to verify the results for both XOR3 and XNOR3 gates. Based on your results, fill in the following tables. A B C Output of XOR3 Output of XNOR3 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 X Y 6. Verify that the experimental results are consistent with the Discussion. However these results can be extended to more than 3-inputs. Checked by Date 7
Section II: XOR gates used in a comparator A simple 4-bit comparator will be built in this section of the experiment. This comparator does not distinguish which 4- bit binary word is larger or smaller. It only informs us whether the two words are the same or not. Specifically, the output of this comparator is high when the two 4-bit binary words are the same but Low when then two words are different. Although the comparator is implemented here with XOR gates and a 4-input NOR gate, you can implement the same function using XNOR gates coupled with a 4-input AND gate. 1. Start a new project called COMPARA and build a schematic design similar to the before in section I, as shown below. 2. Save the schematic design and return to the project navigator window test bench waveform by selecting a new source and implement this design. Input wave form: Output waveform: 8
3. When you have completed the implementation successfully, download the design onto your target board. 4. Fill in the truth tables and comment on the result. Word A Word B output A0 A1 A2 A3 B0 B1 B2 B3 X 0 1 1 0 1 0 0 1 1 0 1 0 1 0 1 0 0 0 1 1 1 1 0 0 0 1 0 0 0 1 0 1 1 1 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 1 0 1 1 0 0 1 1 5. Summarize the results on your own words. Checked by Date Section III: XNOR gates used in comparators designed with VHDL. The 4-bit comparator built in the last section can be designed using VHDL. You will find the same functionality of the circuit from different approaches. In this section, we will show the steps of VHDL design for the 4-bit comparator. We have demonstrated that an XNOR gate can be constructed by cascading an XOR gate and a NOT gate. We also studied that a NOR gate is functionally equivalent to an AND gate with inverted inputs according to DeMorgan s theorem. Hence we will use 4XNOR gates and 1AND gate to build the design. 1. In the Xilinx ISE project navigator, select file new project then follow the steps as shown in the figures. 9
2. Click new source on the next screen and and select the source type as follows and name as shown in the figure. 10
3. Then click finish in the next new source summary. 4. Click next next finish. The skeleton xcmp.vhd file will be displayed in the project navigator. 11
5. Next you need to enter the Boolean equation for your comparator as shown below. 6. Now by editing user constraint file we will have to make pin assignments. 7. Expand user constraints in the processes for current project and double click on floorplan pre-synthesis. 12
8. Assign pin locations and Save then click ok under bus delimiter. 9. Create a test bench waveform by clicking project New source. Associate it with the vhdl source. 10. Select next next finish and then for clock information select combinatorial. 13
11. Give the inputs as shown below, implement the design and simulate. Input Waveform: 12. After simulation the output wave form should be as shown in the figure below. 13. Draw the truth table accordingly similar to section II and compare. Are they same? Discuss. Word A Word B output A0 A1 A2 A3 B0 B1 B2 B3 X 0 1 1 0 1 0 0 1 1 0 1 0 1 0 1 0 0 0 1 1 1 1 0 0 0 1 0 0 0 1 0 1 1 1 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 1 0 1 1 0 0 1 1 14
Checked by Date Section IV: XNOR gates used as buffers and inverters. If you examine the truth table of an XNOR gate carefully, you will notice an interesting fact: when input A is held Low, the output is the complement of input B. When input A is kept High, the output follows input B. This effect means that the XNOR gate can be used to construct a buffer/inverter circuit. What we have to do is use one of the inputs as the control signal and the other input as the data signal. The XNOR will act like a buffer when the control signal is High, but as an inverter when the control signal is pulled Low. Here we will build a 4-bit buffer/inverter circuit and then run a simulation to verify the result. 1. In the project navigator create a new project BUF_INV. 2. Build schematic as shown in the figure below. 3. Following the similar steps as in section I perform implementing the design, simulation and download the design on to the target board and verify your results and draw the truth table for two different inputs for control 0 and 1 value. Inputs and outputs are shown in the figure below. Case 1. Control=0 Input waveform: Output waveform: 15
Case2. Control=1. Input waveform: Output waveform: 4. Fill the truth table according to the outputs you have got and compare the two waveforms. When will the circuit act as a buffer and when will it act as a inverter? Explain. CONTROL=0 CONTROL=1 D0 D1 D2 D3 X0 X1 X2 X3 D0 D1 D2 D3 X0 X1 X2 X3 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 0 1 1 0 0 1 1 0 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 1 1 1 0 1 1 1 1 0 0 0 1 0 0 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 1 1 0 1 1 1 1 0 1 1 1 0 1 1 1 1 1 1 1 1 16
5. Summarize the results in your own words. Questions: Checked by Date 1. A 3-input XOR gate is equivalent to the circuit shown below: The Boolean equation can be written as: Or simply denoted as: Using only AND, OR and inverter gates to implement the above Boolean equation, how many gates are needed? Draw the logic diagram. Compare the savings of a single XOR gate implementation with the circuit you just drew. 2. How can you use a 2-input XOR gate to function as a 1-bit buffer/inverter? Draw the logic diagram. Show the logic connections for the control and data input lines. 17
3. Draw the logic circuit for each of the following. For each gate, determine EVEN or ODD parity and find the output for the given input data: a. 4-input XOR, input data=1001 b. 5-input XNOR, input data-10010 c. 6-input XOR, input data=101001 d. 7-input XNOR, input data = 1011011 18