Architectural Support for 50 and 100 Breakout Ali Ghiasi Ghiasi Quantum LLC IEEE 802.3cd Task Force Mee@ng San Diego July 26, 2016
Overview q Baseline for 50 and NG 100 adopted in Whistler h=p://www.ieee802.org/3/cd/public/may16/nicholl_3cd_01a_0516.pdf Leveraging CL82 40 for 50 having 4 lanes Leveraging CL82 100 for NG 100 having 20 lanes Adopted s are compaqble with P802.3bs architecture and supports both 25G and 50G IO q In Whistler we didn t make a decision on # lanes or distribu@on to further study the burst error not using the P802.3bs interleaved TX differenqal pre-coding was invesqgated for 50 Gb/s link h=p://www.ieee802.org/3/cd/public/adhoc/archive/hegde_070616_3cd_01_adhoc.pdf RS(544,514) performance with pre-coding and bit/symbol were invesqgated h=p://www.ieee802.org/3/cd/public/adhoc/archive/anslow_070616_3cd_01_adhoc.pdf TX differenqal pre-coding helps burst error on links with large dominant 1 st tap allowing to build a supporqng bit-mux and compaqble with P802.3bs A supporqng bit mux is key to building common ports/modules and breakout applicaqons q In this contribu@on the need to support 25G lanes in support of breakout applica@ons will be discussed. A. Ghiasi 2 IEEE 802.3cd Task Force
SupporQng Breakout ApplicaQons q QSFP56 4x50G (200 ) 2x100 4x50 q QSFP-DD 8x25G (200 ) 2x100 4x50 8x25 (in the Qme frame not likely applicaqon) q CFP8 16x25G (400 ) 2x200 4x100 8x50 16x25 (in the Qme frame not likely applicaqon) q Next will examine architectural requirement to support breakout. A. Ghiasi 3 IEEE 802.3cd Task Force
SupporQng Breakout in CFP8 q baseline already supports 25G lane h=p://www.ieee802.org/3/cd/public/may16/nicholl_3cd_01a_0516.pdf q also needs to support 25G lane Currently 200 /400 support 25G lanes and allow implemenqng into 25G IO host ASIC Unless 50 and NG 100 supports 25G lane then is forced into the CFP8 module resulqng in more complex module architecture recommended to support 25G lanes in support of breakout applicaqon, flexibility, compaqbility with BS, and allow to reside on host ASIC or in the - chip. Super-set Host Super-set SOC + 400 2x200 4x100 8x50 CDAUI-16 2xCCAUI-8 4xCAUI-4 8x50GAUI-2 - Mux + (not desirable) CFP8 CDAUI-8 2xCCAUI-4 4xCAUI-2 8x50GAUI-1 400 2x200 4x100 8x50 A. Ghiasi IEEE 802.3cd Task Force 4
SupporQng Breakout in QSFP-DD q baseline already supports 25G lane h=p://www.ieee802.org/3/cd/public/may16/nicholl_3cd_01a_0516.pdf q also needs to support 25G lane Currently 200 /400 support 25G lanes allow implemenqng into 25G host ASIC Unless 50 and NG 100 supports 25G lanes then is forced into the QSFP-DD module resulqng in more complex module and possibly exceeding QSFP-DD power envelope architecture recommended to support 25G lanes in support of breakout applicaqon, flexibility, compaqbility with BS, and allow to reside on host ASIC or in the - chip. Super-set Host CCAUI-8 2xCAUI-4 4x50GAUI-2 QSFP-DD Super-set SOC + 200 2x100 4x50 - Mux + (not desirable) CCAUI-4 2xCAUI-2 4x50GAUI-1 200 2x100 4x50 A. Ghiasi IEEE 802.3cd Task Force 5
SupporQng Breakout in QSFP56 q baseline already supports 25G lane h=p://www.ieee802.org/3/cd/public/may16/nicholl_3cd_01a_0516.pdf q QSFP56 having na@ve 50G IO is designed to operate with na@ve 50G host IO but early ASIC implementa@on my require 2:1 - mux Currently 200 /400 support 25G lanes and allow implemenqng into 25G host ASIC Any 2:1 - mux/ on the line card it will not add complexity or power to the QSFP56 architecture supporqng 25G lanes provide benefit even in this scenario by allowing opqmizing the implementaqon based on availability host ASIC/FPGA and - Mux. Super-set Host Super-set SOC + 200 2x100 4x50 CCAUI-4 2xCAUI-2 4x50GAUI 2:1 PAM- Mux + (not desirable) IC QSFP56 200 2x100 4x50 A. Ghiasi IEEE 802.3cd Task Force 6
SupporQng Breakout q In addi@on to the suppor@ng 25G lanes for ease of implementa@on needs to support 25G lanes as well! Super-set Host with 25G IO Module Common Suppor@ng 50, NG 100, 200, and 400 25G Lanes Supported 8x50 4x100 2x200 400 8x50 4x100 2x200 400 25G Lanes Not Supported 8x50 4x100 2x200 400 8x50 4x100 2x200 400 A. Ghiasi IEEE 802.3cd Task Force 7
Summary q Commonality of and where possible with 802.3bs allow broadest set of breakout applica@ons 50 will be most common breakout from 200G ports 100 will be the most common breakout from 400G ports q Adhoc inves@ga@on of (544,514) with differen@al pre-coding indicate bit mux can be support on non-interleaved 50 /NG 100 allowing to build common /module suppor@ng P802.3bs applica@ons q The 50 and NG 100 supports 25 lane which allow early implementa@on as well as more efficient 2 nd genera@on implementa@ons based on 50G IO q Recommend to also support 25 lane for compa@bility with P802.3bs and allow breakout applica@on using a common IC without the need to force into the module. A. Ghiasi 8 IEEE 802.3cd Task Force