Silicon Interposers: Ghost of the Past or a New Opportunity? Linda C. Matthew TechSearch International, Inc. www.techsearchinc.com
Outline History of Silicon Carriers Thin film on silicon examples Multichip module examples New Developments Today s silicon interposers Integrated passive substrates Potential suppliers Conclusions
History of Silicon Substrates Early developments from AT&T Bell Labs, IBM, Toshiba, NEC, and others Large Panel MCM-D Consortium (Glass) Thin Film on Silicon Substrates Intel IBM Micro Module Systems (MMS) nchip Many Japanese companies such as Toshiba and NEC Source: MMS Source: nchip
Toshiba Toshiba MCM business with thin film on silicon substrate
MCM Company Cemetery Source: TechSearch International, Inc.
Today s Silicon Interposers Advantages High wiring density due to very flat substrate TCE matched to silicon die Excellent electrical and thermal performance Lower laminate substrate cost due to reduced wiring density Partitioning improve yield, reduce cost of large die Smaller I/O pitch on chip Lower power due to multiple die on one substrate Integrated passives Low cost due to depreciated equipment Can have TSVs Intermediate solution to full 3D-IC Minimal stress on low-k, ELK dielectrics Disadvantages Technical issues: TCE, lossy silicon, memory latency Cost (especially for high via counts, large substrates) Logistics Infrastructure (few suppliers, supply chain handoff needs to be defined)
Today s Barriers to 3D-ICs 3D-IC constrains die I/O locations, compromising design freedom and functionality TSV real-estate is costly on an active device serving as the stack base Additional device yield loss due to TSV Handling thin wafers full thickness die can be used on thin interposer Thermal management 3D-IC process not ready for everyone EDA tools not ready for 3D-IC
Potential Applications Server ASICs and FPGAs performance, yield benefit from partitioning very large die Planar module: stacked memory adjacent to the processor for high speed applications with large memory. Test prior to stacking Sandwich module with die above and below interposer Bottom package in PoP where laminate substrate has reached routing density limit smaller package, top PoP memory Wireless modules with integrated passives in substrate
Specifications of Si Interposers under Evaluation
Integrated Passives in Substrates Early developments from AT&T Bell Labs and Intarsia Thin film process on silicon or glass STMicroelectronics SyChip (purchased by Murata) NXP now IPDiA Active devices mounted on top of substrate Flip chip Wire bond Discrete passive devices may also be mounted System cost savings Smaller form factor Competes with LTCC Laminate substrates with integrated passives
Intarsia Founded in 1997 as a joint venture by Dow Chemical and Flextronics Closed in 2001 Did much to demonstrate capabilities and potential for thin-film integrated passive technology in its short time Early work on thin-film substrates with integrated passives Glass substrate Also developed IPDs in wafer level packages Demonstrated SiP modules Research Triangle Institute (RTI) has the right to transfer the technology including the process technology and design library
STMicroelectronics Flip Chip for IPAD SiPs Source: STMicroelectronics
NXP s Passive Integration Connecting Substrate Source: NXP Technology developed to support NXP s products such as Bluetooth transceiver, as well as GSM, GPRS, Edge transceivers, and WiFi transceivers Thin-film substrates with integrated passives Substrate incorporates passives such as capacitors, resistors, and inductors High density capacitors (up to 100nF/mm2) SiP modules in production (France for production and R&D, China for high volume production) NXP spin-off now called IPDiA
Today s Potential Silicon Interposer Suppliers ALLVIA Samples by Q3 2010 Amkor Will use interposers, development with customers, production in 2011 or 2012 ASE Internal capacity by end of 2011 or 2012 Dai Nippon Printing (DNP) Started offering prototypes of standard interposer in January 2010 Ibiden R&D IPDiA First samples available in October 2010 Samsung Electro-Mechanical R&D Shinko Electric R&D STATS ChipPAC Samples available in mid-2010, volume production in 2011 or 2012 TSMC R&D
ALLVIA
Amkor Developing assembly with silicon interposers in partnership with customers Microbumps using copper pillar with underfill No integrated passives offered
ASE Two options Supply internally developed silicon interposers (2011 or 2012) Source interposers externally and do thinning, redistribution, and assembly (2012) Substrate size Range from 32 mm x 32 mm to 55 mm x 55 mm Thickness 100 to 200 µm Microbumps using copper pillar or solder bumps, underfill will be used
Dai Nippon Printing (DNP) Standard silicon interposer Samples offered in January 2010 Substrate size Thickness 400µm 50µm TSVs on 200µm pitch Cu via RDL (1 or 2 layers) User can customize wiring design
IPDiA Spin-off from NXP located in Caen, France (Normandy) First samples of silicon interposers available October 2010 Interposers with integrated passives for decoupling capacitors and RF devices will ship samples in December 2010 Volume production is expected by the end of 2011 or 2012 RF interposer in volume production >100M modules shipped through NXP, IPDiA 5.5 mm x 5.5 mm, 200µm thick TSV diameter 75µm on 125µm pitch First generation capacitance density of 25nF/mm 2 Second generation capacitance density of 80nF/mm 2 Third generation capacitance density (in qualification) of 250nF/mm 2
STATS ChipPAC Plans to offer assembly samples with silicon interposers in mid-2010 Has capability for integrated passives Volume production expected in 2011 or 2012 Sample test vehicle Thickness of 100µm Demonstrated test vehicle with Cu or AgSn microbumps 40 to 50µm pitch, underfill used
Conclusions Different solution today than in old MCM days Potential for applications Wireless devices ASIC CPU for server GPU FPGA Suppliers starting to appear, not really ready for high volume production today Cost remains a concern