Te chnologic Sys tems a te e c., 00 TS- PC/ 0, PL,.0 RLM PC/0 Bus JTAG a ta Buffe r.v Re g. Outputs (Input) EPM0T00C A CHK# A A A A A A A A 0 RY A AEN A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A B B RESET B + V B IRQ B -V B RQ B -V B ENX# B + V B0 (KEY) B B B W# B R# B ACK# B RQ B ACK# B RQ B RFRSH# B0 BCLK B IRQ B IRQ B IRQ B IRQ B IRQ B ACK# B TC B BALE B + V B0 OSC B B CN0 PC0- A K LE Gre e n R % STOPCLK# TCK TI TMS 0 TO J JTAG_X TCK TI TO TMS CLK CLK CLK CLK 0 0 INT INT INT/ INT/ 0 0 / 0 / 0 00 0 0 0 U MAX_0 B0 B B B B B B B 0 A A A A A A A 0 U LVC A K LE Re d R % VIN.V.V U LMMP- C 0 uf V RA-C RA-A BAV R.K C 0 nf C 0 nf C 0 nf C 0 nf C 0 nf C 0 nf C. uf C0. uf C. uf RA-B RA- ISA_RESET W# R# S0 S S S S S S S.MHZ S[0:] A[00:].V.V JP JP.V JP JP A[00:] A R# W# V V.V PL_# _ B0 B B B B B B B S S S S S S S S0 S[0:] B[0:] B0 B B B B B B B.MHZ ISA_RESET _ PL_# OUT_[0:] OUT_0 OUT_0 OUT_0 OUT_0 OUT_0 OUT_0 OUT_0 OUT_0 OUT_0 OUT_0 OUT_ OUT_ OUT_ OUT_ OUT_ OUT_ OUT_ OUT_ OUT_ OUT_0 OUT_ OUT_ OUT_ OUT_ OUT_ OUT_ OUT_ OUT_ OUT_ OUT_0 OUT_ OUT_ REA_# REA_# REA_# REA_# A A GATE_A RAM_R#.V.V V.V A A RAM_# RAM_CS# S_RST# GRN_LE# GRN_LE#
V INPUT_[0:].V R0 RA-A RA-B RA-C RA- RA-A RA-B RA-C RA- INPUT_0 RAM_[0:] RAM_ RAM_ RAM_ RAM_ RAM_ RAM_ RAM_ REA_# U A B A B A B A B A B A B A B A B HC 0 0 R R R R R R R INPUT_0 INPUT_0 INPUT_0 INPUT_0 INPUT_0 INPUT_0 INPUT_0 INPUT_0 INPUT_0 INPUT_0 INPUT_0 INPUT_0 INPUT_ INPUT_ INPUT_ INPUT_ INPUT_[0:] CN 0 INPUT_0 INPUT_0 INPUT_0 INPUT_0 INPUT_0 INPUT_ INPUT_ INPUT_ INPUT_ INPUT_ 0 INPUT_0 INPUT_ INPUT_ INPUT_ INPUT_ INPUT_ INPUT_ INPUT_ INPUT_ INPUT_ 0 INPUT_0 V INPUT_ INPUT_ RAM_ RAM_ RAM_ RAM_ RAM_ RAM_ RAM_ REA_#.V U 0 A B A B A B A B A B A B A B A B 0 HC R R R0 R R R R RA-A RA-B RA-C RA- RA-A RA-B RA-C RA- INPUT_0 INPUT_0 INPUT_ INPUT_ INPUT_ INPUT_ INPUT_ V PF PTC_0 0 ma H- AMP 0- or AMP 0- Rt Angle = AMP 00- La tche s = AMP 00- R INPUT_ Te chnologic Sys tems TS- Input s a te e c., 00.0 RLM
Te chnologic Sys tems a te e c., 00 TS- Input s RLM R RA-A RA-B RA-C RA- RA-A RA-B RA-C RA- A A A A B B B B A A A A B B B B 0 0 U HC R R R R0 R R R R RA-A RA-B RA-C RA- RA-A RA-B RA-C RA- A A A A B B B B A A A A B B B B 0 0 U HC R R R R R R0 R.V.V RAM_[0:] RAM_ RAM_ RAM_ RAM_ RAM_ RAM_ RAM_ REA_# RAM_ RAM_ RAM_ RAM_ RAM_ RAM_ RAM_ REA_# INPUT_[0:] INPUT_ INPUT_ INPUT_ INPUT_0 INPUT_ INPUT_ INPUT_ INPUT_ INPUT_ INPUT_ INPUT_ INPUT_ INPUT_ INPUT_0 INPUT_ INPUT_ V V
Re na s a s low powe r SRAM Pa rt # RLP00CSP-SC V pa rt A[00:] C 0 nf C 0 nf C. uf U Te s t Point to me a s ure dra in K V RAM_CS# A Ke ys tone # 0 igike y # 0K-N ba ttery = CR0 00 ma-hour VIN BATT MOE CE# CE# A/CE# B/CE# U0 VOUT TOL RST# CS# CS# CS# CS# 0 S SS = SOIC TOL tie d to Vout = Re s e t trip is. to.0 V This is a ls o whe n the ba ttery is s witche d in or out S_RST# RAM_CS# RAM_CS# A[00:] GATE_A GATE_A RAM_CS# RAM_R# RAM_CS# RAM_R# A A A A A A A A A A A A A A 0 0 0 0 A A A A A A A 0 A A A A A A A A A A CS# WR# SRAM_MBIT U A A A A A A A 0 A A A A A A A A A A CS# WR# 0 0 RAM_ RAM_ RAM_ RAM_ RAM_ RAM_ RAM_ RAM_ RAM_ RAM_ RAM_ RAM_ RAM_ RAM_ RAM_[0:] RAM_ RAM_ RAM_ RAM_ RAM_ RAM_ RAM_.V 0 0 U B0 A B A B A B A B A B A B A B LVC _ RAM_# S0 S S S S S S S S[0:] Mode = a t powe r up --> -bit mode SRAM_MBIT mv = 0 ua dra in (ma ximum de s ire d) R 00 Mode = Vout a t powe r up --> -bit mode.v X X R-C R- R-A R-B MT MT S_RST# Te chnologic Sys tems a te e c., 00 TS- RAM, Ba ttery, S Re v:.0 e s igne r RLM She e t of
OUT_[0:] U OUTPUT_[0:] OUT_0 OUT_0 OUT_0 OUT_0 OUT_0 OUT_0 OUT_0 IN IN IN IN IN IN IN OUT OUT OUT OUT OUT OUT OUT 0 OUTPUT_0 OUTPUT_0 OUTPUT_0 OUTPUT_0 OUTPUT_0 OUTPUT_0 OUTPUT_0 ULN00A OUTPUT_[0:] U OUT_0 OUT_0 OUT_0 OUT_ OUT_ OUT_ OUT_ IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT ULN00A 0 OUTPUT_0 OUTPUT_0 OUTPUT_0 OUTPUT_ OUTPUT_ OUTPUT_ OUTPUT_ OUTPUT_0 OUTPUT_0 OUTPUT_0 OUTPUT_0 OUTPUT_0 OUTPUT_ CN 0 OUTPUT_0 OUTPUT_0 OUTPUT_0 OUTPUT_0 OUTPUT_0 OUTPUT_ OUTPUT_ OUTPUT_ OUTPUT_ OUTPUT_ OUT_ OUT_ OUT_ OUT_ OUT_ OUT_0 OUT_ IN IN IN IN IN IN IN U OUT OUT OUT OUT OUT OUT OUT 0 OUTPUT_ OUTPUT_ OUTPUT_ OUTPUT_ OUTPUT_ OUTPUT_0 OUTPUT_ OUTPUT_ OUTPUT_ OUTPUT_ OUTPUT_ OUTPUT_ OUTPUT_ OUTPUT_ OUTPUT_ 0 0 OUTPUT_ OUTPUT_0 OUTPUT_ OUTPUT_ OUTPUT_ OUTPUT_ OUTPUT_0 OUTPUT_ ULN00A H- OUT_ OUT_ OUT_ OUT_ IN IN IN IN IN IN IN U OUT OUT OUT OUT OUT OUT OUT 0 OUTPUT_ OUTPUT_ OUTPUT_ OUTPUT_ Outputs thru V R C. uf ULN00A ca n s ink 00 ma Conne ctor pin is cla mp voltage Outputs thru ca n s ink 00 ma This s hould be conne cted to the highe s t voltage powe r s ource U us e d on the e xterna l de vice s OUT_ OUT_ OUT_ OUT_ IN IN IN IN IN IN IN OUT OUT OUT OUT OUT OUT OUT 0 OUTPUT_ OUTPUT_ OUTPUT_ Outputs ca n be pa ra lle le d for much highe r curre nt drive 0V ma x output voltage The cla mp voltage protects a ga ins t inductive ringing which is common with re la ys ULN00A OUTPUT_ U OUT_0 OUT_ OUT_ IN IN IN IN IN IN IN OUT OUT OUT OUT OUT OUT OUT 0 OUTPUT_0 OUTPUT_ OUTPUT_ ULN00A Te chnologic Sys tems a te Fe b., 00 TS- Out put s Re v: e s igne r RLM She e t of