PPLICTION NOTE igital Video ecoder/encoder Module System: ENCMO03 + I²C Interfacing
bstract This application note is intended to provide application support for Philips igital Video ecoders and Encoders. It contains a description of various evaluation boards as well as I²C-bus programming of the ICs. The igital Video ecoder converts an analog video input signal into a digital output signal. This signal can be processed by a wide range of applications and fed to the igital Video Encoder, which delivers analog video signals to TV receivers or video cassette recorders. This note gives a detailed description of the schematics and some hints how to design the PCB (Printed Circuit Board) with mixed analogue and digital signal processing. Philips Electronics N.V. 1997 ll rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. 2
PPLICTION NOTE igital Video ecoder/encoder Module System: ENCMO03 + I²C Interfacing uthor: Thomas Grube Systems Laboratory Hamburg, Germany Keywords igital Video Encoder (ENC) S7120/21 igital Video ecoder S7111(), VIP, EVIP I²C Bus MultiMedia ate: 7th Febuary 1996 3
Summary This application note is intended to provide application support for Philips igital Video ecoders and Encoders in addition to the application note N96055. It contains a description of evaluation boards as well as I²C-bus programming of the ICs. The igital Video ecoder converts an analog video input signal into a digital output signal. This signal can be processed by a wide range of applications and fed to the igital Video Encoder, which delivers analog video signals to TV receivers or video cassette recorders. This note gives a detailed description of the schematics and some hints how to design the PCB (Printed Circuit Board) with mixed analogue and digital signal processing. 4
CONTENTS 1. Introduction.................................................. 7 2. igital Video Encoder Module ENCMO03................................. 7 3. I²C-bus EEPROM on ECMO01, ENCMO02 and ENCMO03.................... 10 4. Module System Connectors........................................ 11 5. I²C-Bus Interface H6CS38........................................ 12 6. I²C-Bus Level Shifter............................................ 13 7. Programming tables for S7120/21 and S7111........................... 14 8. Universal Register ebugger Software................................... 15 9. Tips for a PCB layout with analog and digital signal processing...................... 15 10. PCB Revisions............................................... 16 11. ppendix: Schematics and Layout..................................... 16 11.1 Schematics............................................. 16 11.1.1 Top sheet of ENCMO03................................ 17 11.1.2 igital Video Encoder of ENCMO03......................... 18 11.1.3 Inputs of ENCMO03.................................. 19 11.1.4 Outputs of ENCMO03................................. 20 11.1.5 Power Supply and EEPROM of ENCMO03...................... 21 11.1.6 I²C Interface H6CS38................................. 22 11.2 Layout............................................... 23 11.2.1 Top placement of ENCMO03............................. 23 11.2.2 Routing of top layer of ENCMO03........................... 24 11.2.3 Routing of bottom layer of ENCMO03......................... 25 11.2.4 Routing of ground plane layer of ENCMO03..................... 26 11.2.5 Routing of power supply layer of ENCMO03..................... 27 11.2.6 Routing and Placement of I²C Interface H6CS38................... 28 5
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1. Introduction The s provide the basis to evaluate various Philips digital video decoders and encoders and give the opportunity to simply insert the modules into customized applications and systems. This application note is an extension to application N96055 ( System) and contains additional information about the module ENCMO03 and I²C-bus interfacing (3V/5V level translation). On the following pages the schematics of the igital Video Encoder Module ENCMO03 are shown. The module can be operated in stand alone operation (colourbar generator) as well as extension to other systems like PCIbridges, MPEG decoders or Video input/output systems. The module has a socket for an I²C-bus EEPROM (e.g. PCF8582, PCF8594, PCF8598, X24164) in order to store data for initialization and for simple control functionality operated by a (future) microcontroller module. Software for IBM compatible personal computers enables access to all features and settings of the devices. It handles the I²C-bus via a printer port adaptor. This modular concept was designed to combine different video decoders with various video encoders. Each module can be configured for several devices and packages without the necessity of having a new PCB. This could be achieved by using multiple footprints for one IC and some configurational parts. For interfacing a 26-pin and a 16-pin flat ribbon cable connector is used. The 26-pin YUV-Feature Connector is used for the signal path while the other one is used for power supply and I²C-bus. 2. igital Video Encoder Module ENCMO03 The digital encoder module ENCMO03 contains the encoder S7120/21 in QFP44 package. The digital data are accepted in CCIR 656 format (1). The outputs of the / converters are fed through analog postfilters to the connectors. To allow future ICs to be assembled on this module, some provisions have been done. The filters are assigned to the connectors, so that for each signal type the serial resistor and the filter can be optimized. The signals out of the / converters are routed via jumpers to adapt the different output modes of future ICs (JP22, JP23). RGB signals can be fed to the future encoder via connector J3. The RGB inputs are connected to the IC via optional resistor dividers to adapt the input voltage range and to terminate the lines. The clock and synchronization signals can be fed to the encoder via jumper (JP10, JP11, JP15) when operating the slave mode (JP21 open). Using the encoder as clock master (JP21 closed) LLC is supplied by XCLK out of the S7120/21. The pins RCV1 and RCV2 can be configured to outputs via I²C-bus setting (see I²C-bus register 6Bh in datasheets) to provide horizontal and vertical synchronization signals. 7
T1 J1 T2 T3 JP1 GN U1 J5 JP5 JP15 JP10 JP21 U4 J6 QFP44 JP11 JP6 JP2 JP12 JP8 JP9 JP7 U2 U3 JP3 JP4 J3 GN ENC03.wmf Fig.1 Location of ICs, jumpers and connectors on the ENCMO03 PCB 8
TBLE 1 Configuration ENCMO03 Part Value escription JP12 closed open slaveaddress 88h slaveaddress 8Ch JP8, JP9 closed connection of (5V-) I²C-bus to system connector R55, R56 0R only stuffed, if no 3V to 5V adaption of I²C levels R53, R54 3k stuffed for 3V to 5V adaption of I²C levels Q2, Q3 BS170 stuffed for 3V to 5V adaption of I²C levels R35 0R connection GN to GN near encoder R34 open termination LLC JP15 closed jumper LLC (clock from/to feature connector) JP21 JP11 JP10 closed open connects the XCLK output with the LLC input HS/HREF to/from RCV2 VS to/from RCV1 J3 RGBin RGB input connector (for future ICs) R15,16,17,18,23,24,26,27 used to adapt input voltage range T5 RESN testpin (active low reset input) T7 TTXRQ testpin (output signal for teletext request) T8 TTX testpin (input signal for teletext data) R62, R63 0R connection of TTX and TTXRQ to system connector JP19 to be stuffed for future ICs JP20 to be stuffed for future ICs JP22 to be stuffed for future ICs JP23 to be stuffed for future ICs R57, R59 0R to be left open for future ICs R58, R60, R61 open to be stuffed 0R for future ICs R64, R65, R66 0R to be left open for future ICs JP2 additional pins for using a 60 pin header for JP1, JP2 and JP3 JP4 additional testpins connected to reserved pins on JP3 JP5 JP6 JP7 additional pins for using reverse connectors Remark: The parts mentioned in Table 1 are only for evaluation purpose and can be omitted in an application. 9
3. I²C-bus EEPROM on ECMO01, ENCMO02 and ENCMO03 The IC U1 on each module can be assembled with different IC types depending on the desired memory size. dditionally the I²C-bus device address can be adapted by soldering corresponding SM resistors which is described in the tables below. TBLE 2 Configuration of I²C-bus EEPROMs IC type Size Pin 1 Pin 2 Pin 3 Pin 7 ddress Range PCF8582x-2 256 bytes 0: PCF8594x-2 512 bytes WP 1: 1: PCF8598x-2 1024 bytes WP n.c. X24164 2048 bytes S0: S1: 2: 2: 2: S2: PTC PTC PTC TEST 0h or 2h or 4h or 6h or 8h or h or Ch or Eh 0h and 2h or 4h and 6h or 8h and h or Ch and he 0h, 2h, 4h and 6h or 8h, h, Ch and Eh 80h, 82h, 84h, 86h, 88h, 8h, 8Ch and 8Eh or 90h, 92h, 94h, 96h, 98h, 9h, 9Ch and 9Eh or 0h, 2h, 4h, 6h, 8h, h, Ch and Eh or B0h, B2h, B4h, B6h, B8h, Bh, BCh and BEh or C0h, C2h, C4h, C6h, C8h, Ch, CCh and CEh or 0h, 2h, 4h, 6h, 8h, h, Ch and Eh or E0h, E2h, E4h, E6h, E8h, Eh, ECh and EEh or F0h, F2h, F4h, F6h, F8h, Fh, FCh and FEh TBLE 3 Board Configuration for I²C-bus EEPROMs Pin Remark PTC or TEST 2 or S2 1 or S1 WP, 0 or S0 R4: OPEN R8: 0R R5: OPEN R9: 0R R6: OPEN R10: 0R R7: OPEN R11: 0R R4: 0R R8: OPEN R5: 0R R9: OPEN R6: 0R R10: OPEN R7: 0R R11: OPEN Leave pin PTC open; apply to pin TEST pin S1 (X24164) is inverted internally WP: --> write protect of upper 256[512] bytes --> write enabled (only PCF8594[PCF8598]) Note: The modules will be stuffed by default using the following slaveaddresses (8-bit notation): EEPROM - type:ecoder Modules: Encoder Modules: PCF8582x-2 6h 8h PCF8594x-2: 4h, 6h, WP=1 8h, h, WP=0 PCF8598x-2: 0h, 2h, 4h, 6h, WP=1 8h, h, Ch, Eh, WP=0 X24164: 90h, 92h, 94h, 96h, 98h, 9h, 9Ch and 9Eh E0h, E2h, E4h, E6h, E8h, Eh, ECh and EEh 10
4. Module System Connectors The YUV connector (feature connector) provides access to the digital YUV data input coming from a digital video decoder or from an MPEG video source supplied to a video encoder. Two YUV data formats are supported, 16- bit decoder format or 8-bit CCIR656 compatible (1). The control lines are set either as inputs or outputs. The connector has the following pin assignment: Pin 1, 3, 5, 7, 9, 11, 13, 15 UV0: UV7 digital UV data (not used on ENCMO03) Pin 2, 4, 6, 8, 10, 12, 14, 16 Y0: Y7 digital CCIR656 data Pin 17 LLC digital clock Pin 18 LLC2 (not used on ENCMO03) Pin 19 CREF, clock reference (not used on ENCMO03) Pin 20 HREF, optional horizontal reference (blanking) Pin 21 RTC, real time control Pin 22 HS, horizontal synchronisation pulse Pin 23 digital ground Pin 24 VS, vertical synchronisation pulse Pin 25 IR Pin 26 digital ground The 16-pin header for power supply and I²C-bus has the following pin assignment: Pin 1 SCL Pin 2 S Pin 3, 9, 15, 16 reserved for future use Pin 4 TTXRQ (teletext data request output from encoder) Pin 5, 6 digital power supply (5V) Pin 7, 8 digital groundl Pin 10 TTX (teletext data input to encoder) Pin 11, 12 analog power supply (12V) Pin 13, 14 analog ground On each module in addition (or as alternative) a 4 pin connector can be used for I²C-bus control: 1 SCL 2 GN 3 +5V 4 S 1 2 3 4 SCL 1 GN 2 S 3 +5V 4 S SCL GN +5V I2C-NEW I2C-OL (Europe) I2C (US) T1 1 SCL 2 GN 3 +5V 4 S T2 T3 I2C-NEW +5V S GN SCL S SCL GN +5V using 3 additional pins, one out of the three common used pin configurations can be stuffed I2C_CON6.wmf Fig.2 I²C-bus connector pinnings Note: lways supply the I²C-bus with pull-up resistors, but avoid too high currents (see I²C-bus specification). On each module pull-up resistors can be added (R1 and R2), but preferably only one pull-up should be done on the I²C-bus master IC. 11
5. I²C-Bus Interface H6CS38 For systems running in a 3.3V environment it is required to use an I²C-bus interface with 3.3V capability. The new Single Master Interface H6CS38 with the IC 74HC9114 replaces former Single Master Interfaces with the IC 74LS05 (e.g. H3VS15), which is only suited for 5V. The new interface operates on the I²C-bus from 1.8V to 5V. The 74HC9114 is a nine wide Schmitt-Trigger buffer with open drain inverting outputs, which are not clamped by diodes connected to V CC. This allows the device the operation as level shifter with the output to be pulled between GN and V Omax. There are three options to represent (or to support the internal) pull-up resistors at the input lines of the PC s parallel port (see also schematics of H6CS38 in appendix): 1.) the databits at portpins 2 ~ 4 of the LPT connector (-SUB25) are connected via 10k resistors R1 ~ R3 to pins 11, 12 and 15 (input lines) 2.) if V on the I²C-bus connector is high enough, the resistors R7 ~ R9 get the supply via diodes 4 ~ 6 3.) an external supply can be fed to R7 ~ R9 via diodes 1 ~ 3 The pull-up resistors on the interface to the PC side are supplied by unused databits which should be programmed to by the I²C-bus driver software. Together with the LPT-internal pull-ups this should operate. ue to the various different implementations of parallel port interfaces (LPT) in Personal Computers in a few cases it could be required to add an additional supply voltage of 5V to the interface to meet the correct input levels. Therefor two pads are foreseen on the interface PCB (named +5V and GN ). If the databits are set to, R1 ~ R3 act as load and decrease the signals. If no external 5V supply is available, it is then possible to remove R1 ~ R3. In that case, the LPT portpins must have their own pull-ups. The I²C-bus driver Í2CRV.LL (96-03-22 10:46, 52192 byte; supplied with the Universal Register ebugger software) switches the databits to during a start condition, but this does not influence the I²C transmission. The driver I2CPI.LL version 1.0.0.3 (supplied with several tools from the Systems Laboratory Hamburg) tests in addition the performance of the LPT-port signals. If the low to high transition is too slow (more than 1µs), the interface detection will fail. This can be caused by too high ohmic pull-up resistors or too much capacitive load due to long interface cables (e.g. 25 pin flat ribbon cable). In some configurations (e.g. PC-Laptop with capacitors at LPT-portpins; Error message: No I2C device on parallel port ) two additional pull-up resistors (1...4k7) should be added to the input pins 1 and 3 of the 74HC9114. They can be either connected to VCC or to another unused portpins (like R1~R3 and R7~R9; e.g. use with pins 5~8 of SUB- 25pin connector). The TV (MPC-E) debugger software (versions 1.0x) does not affect the databits, so that they remain in their prior state. This can cause problems when the I²C-bus supply is less than 5V and the bits are (workaround: see above). The software IICTV (and related OS based software packages from Philips Semiconductors) set the databits to so that no problems are expected with R1~R3. The lower the supply voltage of the I²C-bus the lower the pull-up resistors have to be, to ensure a specific current. dditionally noise margins get smaller and voltage drops over serial resistor become more important. These things have to be considered for designs with low voltage I²C-bus. 12
6. I²C-Bus Level Shifter On the Encoder Module ENCMO03 a circuit was implemented to allow the connection of the internal 3.3V I²Cbus to an external 5V I²C-bus connected via the 16pin system connector (the external I²C-bus has to provide its own pull-up resistors). The circuit also operates with 3.3V levels on the system connector, but if no level conversion is necessary, the circuit can be removed (R53, R54, Q2, Q3) and bypassed with resistors R55 and R56. The N-channel enhancement mode vertical -MOS transistors Q2 and Q3 allow the bi-directional I²C-bus operation while shifting the levels. If the bus lines are pulled high (e.g. I²C-bus is inactive) the transistor is in high ohmic state (V GS ~ 0V). If the Source is pulled to GN (3.3V side), V GS exceeds V GS(th) and the transistor conducts so that the rain is also forced to the level of the Source (low). If the rain is pulled to GN, the parasitic diode conducts and the Source is also pulled down. The lower the voltage on the I²C-bus, the more important is the threshold voltage VGS(th) of the transistor. For 3.3V environment, several types can be used (e.g. BSS123 in SOT123 envelope on ENCMO03). For lower voltages it is recommended to use e.g. BSS138 (SOT123) or BS108 (TO92). 13
7. Programming tables for S7120/21 and S7111 The data tables below show the programming for the S7120/21 for operation with S7111 (e.g. ECMO01 connected to ENCMO03) S7120/21: - init data PL Slave: 88h Sub ata REG 3a = 13 (93) REG 5a = 77 REG 5b = 7d REG 5c = af REG 5d = 23 (a3) REG 5e = 35 REG 5f = 35 REG 60 = 00 REG 61 = 06 REG 62 = 2f (af) REG 63 = cb REG 64 = 8a REG 65 = 09 REG 66 = 2a REG 67 = 00 REG 68 = 00 REG 69 = 00 REG 6a = 00 REG 6b = 20 REG 6c = 01 REG 6d = 30 REG 6e = a0 REG 6f = 00 REG 70 = 00 REG 71 = 00 REG 72 = 00 REG 73 = 00 REG 74 = 00 REG 75 = 00 REG 76 = 00 REG 77 = 00 REG 78 = 00 REG 79 = 00 REG 7a = 00 REG 7b = 00 REG 7c = 00 REG 7d = 00 REG 7e = 00 REG 7f = 00 I2C1120d.mem S7120/21: - init data NTSC Slave: 88h Sub ata REG 3a = 13 (93) REG 5a = 77 REG 5b = 76 REG 5c = a5 REG 5d = 2a (aa) REG 5e = 2e REG 5f = 2e REG 60 = 00 REG 61 = 15 REG 62 = 3f (bf) REG 63 = 1f REG 64 = 7c REG 65 = f0 REG 66 = 21 REG 67 = 00 REG 68 = 00 REG 69 = 00 REG 6a = 00 REG 6b = 20 REG 6c = 11 REG 6d = 31 REG 6e = 80 REG 6f = 00 REG 70 = 00 REG 71 = 00 REG 72 = 00 REG 73 = 00 REG 74 = 00 REG 75 = 00 REG 76 = 00 REG 77 = 00 REG 78 = 00 REG 79 = 00 REG 7a = 00 REG 7b = 00 REG 7c = 00 REG 7d = 00 REG 7e = 00 REG 7f = 00 I2C1120d.mem S7111: - init data Slave: Sub 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0h 0Bh 0Ch 0h 0Eh 0Fh 10h 11h 12h 1Fh I2C1120d.mem 48h ata 00h 00h 0h (5h) 00h 00h 00h F9h E9h 8h (2Eh,6Eh) 00h (80h) 80h 47h 40h 00h 00h 00h 0h 0Ch 01h 87h Values in brackets: register 02h: select S-Video input register 08h: H-PLL opened (50Hz/60Hz forced) register 09h: Luma bypass for enhanced S-Video performance Values in brackets: register 3h: Colourbar on register 5h: only use with revision S7120/21 V0 register 62h: Real Time Control (RTCE) enabled INITeI2C.wmf 7120 07.02.96 14
8. Universal Register ebugger Software You can install the Universal Register ebugger Software by simply running the SETUP.EXE on the floppy disk. fterwards you should copy the subdirectory \URT from floppy disk to harddisk. The file \UR- T\1120TG1.UR contains startup information (and a few macros) for the S7111 (EVIP) and S7120 (CONENC). The I²C-bus Single Master Interface has to be connected to a printer port and to the ecoder/ Encoder Modules. fter powering up the hardware and calling the software, the CVBS2 input (J3, ECMO01) accepts PL-B/G input signals to be encoded on the ENCMO03. The following macros can be used (Macro / o Macro): VIP S-Video in: selects input S-Video (J5) of ECMO01 (I12, I22 of S7111) VIP CVBS2 in: selects input CVBS2 (J3) of ECMO01 (I11 of S7111) 7120 NTSC: S7120 setup for NTSC-M 7120 PL: S7120 setup for PL-B/G CB PL: CB NTSC: enables Colourbar Generator Mode of S7120; opens H-PLL of S7111 and forces 50Hz Note: only use this macro in conjunction with 7120 PL macro enables Colourbar Generator Mode of S7120; opens H-PLL of S7111 and forces 60Hz Note: only use this macro in conjunction with 7120 NTSC macro CB off: switches colourbar off; closes H-PLL again On a slow PC it might take a few seconds to run the macros (~10s for 7120 PL/NTSC on a 386X33). The Universal Register ebugger (UR.EXE dated 96-11-06) is a β-release. fter starting the software it might be required to enlarge the window in horizontal direction to view and edit the values of the registers. The UR-files on the disk do not claim to be perfect. Please check with latest datasheet. The file 1120TG1.UR contains modified settings for S7120V0. 9. Tips for a PCB layout with analog and digital signal processing - use separate ground planes for analog and digital supply in one layer (no overlapping!) - use separate supply planes for analog and digital with the same shape (or smaller) as ground (no overlap of analog supply with digital ground and vice versa!) - if there are different (asynchronous) clock domains, use separate ground and supply planes (place the analog areas not in a direct neighbourhood; separate the clock domains) - always use the inner layers for ground and supply planes (no signal layer in between!) - try to keep digital signals away from analog areas - place analog areas close to the border of a PCB - avoid long tracks for analog signals - place decoupling capacitors (22nF to 100nF) close to the power pins of the ICs - prepare several provisions for connecting places for analog and digital ground on the PCB for further optimization on the final board 15
10. PCB Revisions ECMO01: Version Package evice(s) Remarks 1: PLCC68 S7110() PLCC socket stuffed; 26.800 MHz crystal 2: PLCC68 S7111 PLCC socket stuffed; 24.576 MHz crystal 3: LQFP64 S7111 24.576 MHz crystal ENCMO02: ENCMO03: Note: 1: PLCC84 S7124/25/82/83 PLCC socket stuffed 2: QFP80 S7124 3: QFP80 S7125 4: LQFP64 S7124 5: LQFP64 S7125 6: PLCC84 S7182/83 PLCC socket stuffed 7: QFP80 S7182 8: QFP80 S7183 1: QFP44 S7120 I²C-bus level shifter 3V/5V stuffed 2: QFP44 S7120 I²C-bus 3.3V levels - ENCMO02 Vers. 1~8 should be combined with ECMO01 Vers. 2 (5V I/O) - ENCMO03 should be combined with ECMO01 Vers. 3 (3.3V I/O) - ENCMO03 and ECMO01 Vers. 3 (3.3V I/O) should be used with I2C Single Master Interface H6CS38 - all Encoder Modules require a 27.000 MHz 3rd overtone crystal (only for master mode) 11. ppendix: Schematics and Layout The schematics are made in OrC and the files can be delivered on request. For the board layout GERBER files are available. 11.1 Schematics 16
11.1.1 Top sheet of ENCMO03 B C E OUTPUTS CONENC INPUTS VS VS CVBS/Y CVBS/Y 4 4 HS HS CVBS/C CVBS/C HREF HREF CVBS/R CVBS/R TTXRQ TTXRQ Y/G Y/G C/B C/B TTX TTX INPUTS CONENC OUTPUTS CSYNC CSYNC RTC RTC S S SCL SCL RCV1 RCV1 LLC LLC 3 Y[0..7] HS 3 Y[0..7] Y[0..7] Va V5Vd V12Va Vdig Va SCL3 S3 2 2 POWER SUPPLY & EEPROM S3 SCL3 POWER SUPPLY N EEPROM Vdig Va Philips Semiconductors Systems Laboratory Hamburg Software and Multimedia V5Vd ecoder/encoder Module System 1 V12Va T.Gru 1 Title igital Colour Encoder Modul ENCMO03 Size ocument Number Rev ENC03a.dsn 1.0 ate: Tuesday, October 08, 1996 Sheet 1 of 5 B C E 17
+ B B C C + E E Philips Semiconductors 11.1.2 igital Video Encoder of ENCMO03 Vdig R53 R54 Q2 TSTP 3k 3k S T1 L4 2uH2 Va V1 J1 1 1 SCL3 L3 2uH2 C16 C17 C19 2 2 S S 3 3 4 100n C20 100n C52 4 4 BS107 Vdig V1 BSP126 4 P1 P2 BST76 4PCONN R55 BS170 C22 C24 C25 C26 100n 100n 4u7 TSTP OPEN 4u7 GN/GN GN T2 BS107 100n 100n 100n TSTP R35 SCL T3 S3 GN GN S3 0R SCL3 SCL3 S7120/21 QFP44 Module G Q3 GN GN R56 U4 OPEN Y[0..7] Y[0..7] Y7 9 10 MP7 CVBS 30 CVBS/R S SCL Y6 MP6 Y5 11 MP5 BS107 Y4 12 13 MP4 MP3 Y 27 BSP126 Y3 BST76 14 Y/G Y2 MP2 BS170 Y1 15 MP1 Y0 16 MP0 C 24 BS107 C/B 3 TTX 3 G 41 42 SCL S 36 31 V3.4 28 V3.3 25 V3.2 V3.1 39 17 V3.2 6 V3.1 V3.0 ConENC TTXRQ S7120_44p RTCI 19 8 RTC XCLK CVBS/Y XCLK 37 RCV1 7 RCV2 RCV2 RCV1 HS R61 OPEN XTL TTX TTXRQ 44 43 _TTX _TTXRQ TSTP TSTP XTL 34 T8 T7 TTX TTXRQ JP11 JUMP3 35 HSYNC XTLI XTLI C15 10p V1 R57 0R R58 OPEN HREF X1 VS JP10 27MHz 2 JUMP2 VS 2 RESN 40 LLC 4 RES.6 29 RES.5 26 RES.4 23 RES.3 22 RES.2 20 RES.1 1 VSS.2 VSS.1 VSS.2 VSS.1 VSS.0 2 P SP 3 S 33 32 38 18 5 21 C18 10p JP21 CVBS/C RCV1 R59 0R R60 OPEN JUMP2 L1 10uH C21 1n R18 75R R17 75R LLC JP15 LLC_ R15 1k R16 75R LLC JUMP2 R23 0R R34 OPEN SEL_in R24 0R B_in G_in R_in R27 0R R26 0R J3 5 5 4 4 3 3 2 2 1 1 5PCONN RGB-CON CSYNC R31 R52 S RESN Philips Semiconductors Systems Laboratory Hamburg 1 1 47k V1 10k Software and Multimedia ecoder/encoder Module System JP12 T.Gru JUMP2 T5 I2C_R Title TSTP RESN CONENC Size ocument Number Rev B ENC03a.dsn 1.0 Tuesday, October 08, 1996 ate: Sheet of 2 5 18
11.1.3 Inputs of ENCMO03 1 2 3 4 5 6 7 8 S7120/21 QFP44 Module UV[0..7] JP5 Y[0..7] UV[0..7] Y[0..7] JP1 Y0 UV0 Y0 1 Y1 UV1 Y1 2 Y2 UV2 Y2 3 Y3 UV3 Y3 4 Y4 UV4 Y4 5 Y5 UV5 Y5 6 Y6 UV6 Y6 7 Y7 UV7 Y7 8 LLC2 LLC LLC2 9 10 11 12 13 HEER 13 HREF HS VS CREF IR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 RTC HS R3 0R TSTP T13 HEER 13X2 VS HREF JP6 NC[0..8] JP2 NC[0..8] B NC0 NC0 B 1 1 2 NC1 NC1 2 3 4 NC2 NC2 3 5 6 NC3 NC3 4 7 8 NC4 NC4 5 9 10 NC5 NC5 6 11 12 NC6 NC6 7 13 14 NC7 NC7 8 15 16 NC8 NC8 9 17 18 HEER 9 HEER 9X2 JP7 S JP3 JP4 S_ext SCL JP9 JP8 S 1 SCL SCL SCL_ext S_ext S 1 2 res1 res2 JUMP2 res1 res2 1 2 3 4 JUMP2 res2 V5Vd 2 3 V5Vd V5Vd V5Vd 5 6 res3 C 3 4 7 8 C res4 res4 res3 res4 4 5 9 10 res5 V12Va 5 6 V12Va V12Va V12Va 11 12 res6 6 7 13 14 res6 res5 res6 8 15 16 HEER 6 HEER 8 HEER 8X2 female connectors (optionally) male connectors R62 0R Philips Semiconductors Systems Laboratory Hamburg TTX TTX res4 Software and Multimedia ecoder/encoder Module System R63 0R T.Gru TTXRQ TTXRQ res2 Title INPUTS Size ocument Number Rev ENC03a.dsn 1.0 ate: Tuesday, October 08, 1996 Sheet 3 of 5 1 2 3 4 5 6 7 8 19
B B C C E E Philips Semiconductors 11.1.4 Outputs of ENCMO03 S7120/21 QFP44 Module C32 120p JP22 B_F G_F R37 27R C34 390p L7 2uH7 C35 560p L8 2uH7 Blue 4 Y/G R64 0R 4 Y_F C41 120p CVBS/Y CVBS/R JUMP7 JP23 R66 0R R40 13R L13 2uH7 C42 390p C45 120p C43 560p L14 2uH7 R39 27R C38 120p L11 2uH7 C39 390p C40 560p L12 2uH7 Green C/B CVBS/C R65 0R C_F R42 13R L17 2uH7 C48 390p C49 560p L18 2uH7 3 4 2 1 J6 Y C GN GN C44 120p 3 SVHSCON 3 JUMP5 YC C33 120p R41 L15 L16 Red CVBS1_F R38 8R C36 390p L9 2uH7 C37 560p L10 2uH7 J5 CYNCH CVBS1 27R 2uH7 C46 390p C47 560p 2uH7 R_F C29 120p J4 R36 L5 L6 CYNCH 2 CVBS2_F 2 8R 2uH7 2uH7 CVBS2 J7 C30 C31 6 390p 560p 11 1 7 12 2 8 Va Sync/HS 13 3 R43 9 R44 VS 14 4 0R C50 10 100n OPEN 15 5 CSYNC R45 Q1 BC850B B15 VG 1k R46 75R R47 R48 R49 JP19 OPEN 1k JUMP3 OPEN Philips Semiconductors Systems Laboratory Hamburg 1 1 C-HS Software and Multimedia ecoder/encoder Module System R50 0R T.Gru HS Title RCV1 R51 0R JP20 JUMP2 VSYNC OUTPUTS Size ocument Number Rev B ENC03a.dsn 1.0 Tuesday, October 08, 1996 ate: Sheet of 4 5 20
11.1.5 Power Supply and EEPROM of ENCMO03 B C E S7120/21 QFP44 Module Vdig 4 4 R7 OPEN R6 OPEN R5 OPEN R4 OPEN S3 SCL3 U1 S0 S 5 3 S1 SCL 6 S2 S0 S1 S2 1 2 Vdig 8 GN 4 7 Test C51 100n TEST X24164 R11 OPEN R10 OPEN R9 OPEN R8 OPEN 3 3 U2 7803 Vdig 1 VO 3 VI V5Vd V5Vd C6 100n + C5 10u GN 2 C4 100n + C3 4u7 2 2 U3 7803 R13 1 VO 3 Va VI V12Va V12Va 18R C10 100n + C9 10u GN 2 C8 100n + C7 4u7 Philips Semiconductors Systems Laboratory Hamburg Software and Multimedia ecoder/encoder Module System 1 T.Gru 1 Title Power Supply and EEPROM Size ocument Number Rev ENC03a.dsn 1.0 ate: Tuesday, October 08, 1996 Sheet 5 of 5 B C E 21
11.1.6 I²C Interface H6CS38 22
11.2 Layout 11.2.1 Top placement of ENCMO03 23
11.2.2 Routing of top layer of ENCMO03 24
11.2.3 Routing of bottom layer of ENCMO03 25
11.2.4 Routing of ground plane layer of ENCMO03 26
11.2.5 Routing of power supply layer of ENCMO03 27
11.2.6 Routing and Placement of I²C Interface H6CS38 Top routing Bottom routing Top placement Bottom placement 28