CSE4L: Components and Design Techniques for Digital Systems La FSMs Instructor: Mohsen Imani Slides from Tajana Simunic Rosing Source: Vahid, Katz
Flip-flops Hardware Description Languages and Sequential Logic representation of clocks - timing of state changes asynchronous vs. synchronous FSMs structural view (FFs separate from cominational logic) ehavioral view (synthesis of sequencers not in this course)
Controller Design 3.4 Five step controller (FSM) design process 3
FSM inputs FSM outputs Controller Design: Laser Timer Example Prolem: Pressing utton () once turns on laser for 3 clock cycles clk Controller x laser Step : Capture the FSM patient Step 2: Create architecture Step 3: Encode the states Step 4: Minimize logic Step 5: Implement & test clk Cominational logic s s State register n n x a 4
3.3 Laser Timer Pressing utton () once turns on laser for 3 clock cycles Controller x laser Step : Capture the FSM clk patient Clock here is compressed to save space 5
FSM inputs FSM outputs Controller Design: Laser Timer Example Step : Capture the FSM Already done Step 2: Create architecture 2-it state register (for 4 states) Input, output x Next state signals n, n Step 3: Encode the states Any encoding with each state unique will work Inputs: ; Outputs: x x= Off x= x= x= On On2 Cominational logic s s n n x On3 a clk State register 6
FSM inputs Controller Design: Laser Timer Example (cont) Step 4: Create state/excitation tale Inputs: ; Outputs: x x= Off x= x= x= On On2 On3 Cominational logic s s n n x FSM outputs clk State register 7
Controller Design: Laser Timer Example (cont) Step 5: Implement cominational logic FSM inputs Cominational logic s s n n x FSM outputs clk State register x = s + s n = s s + s s + ss + ss n = s s + ss n = s s + ss + ss n = s s + ss 8
Controller Design: Laser Timer Example (cont) Step 5: Implement cominational logic (cont) FSM inputs Cominational logic FSM inputs Cominational Logic s s n n x FSM outputs x n clk State register n s s clk State register x = s + s n = s s + ss n = s s + ss 9
Understanding the Controller s Behavior x= Off x= x= x= On On2 On3 x= Off x= x= x= On On2 On3 x= Off x= x= x= On On2 On3 clk s s x n n clk s s x n n clk s s x n n clk state= state= state= Inputs: Outputs: x
module LaserTimer(, x, clk, rst); input, clk, rst; output x; reg x; parameter S_Off = 2', S_On = 2', S_On2 = 2', S_On3 = 2'; reg [:] currentstate; reg [:] nextstate; // state register procedure always @(posedge rst or posedge clk) egin if (rst==) // initial state currentstate <= S_Off; else currentstate <= nextstate; Laser timer in Verilog // cominational logic procedure always @(currentstate or ) egin case (currentstate) S_Off: egin x <= ; // laser off if (==) nextstate <= S_Off; else nextstate <= S_On; S_On: egin x <= ; // laser on nextstate <= S_On2; S_On2: egin x <= ; // laser still on nextstate <= S_On3; S_On3: egin x <= ; // laser still on nextstate <= S_Off; case module // LaserTimer
FSM design example Moore vs. Mealy Remove one from every string of s on the input Moore Mealy zero [] zero [] / one [] twos [] / one [] / /
Verilog FSM - Reduce s example Moore machine module reduce (clk, reset, in, out); input clk, reset, in; output out; state assignment (easy to change, if in one place) parameter zero = 2 ; parameter one = 2 ; parameter twos = 2 ; reg out; reg [2:] state; reg [2:] next_state; // state variales always @(posedge clk) if (reset) state = zero; else state = next_state; zero [] one [] twos []
Moore Verilog FSM (cont d) always @(in or state) case (state) zero: // last input was a zero egin if (in) next_state = one; else next_state = zero; one: // we've seen one egin if (in) next_state = twos; else next_state = zero; twos: // we've seen at least 2 ones egin if (in) next_state = twos; else case next_state = zero; crucial to include all signals that are input to state determination note that output deps only on state always @(state) case (state) zero: out = ; one: out = ; twos: out = ; case module
Mealy Verilog FSM module reduce (clk, reset, in, out); input clk, reset, in; output out; reg out; reg state; // state variales reg next_state; always @(posedge clk) if (reset) state = zero; else state = next_state; always @(in or state) case (state) zero: egin out = ; // last input was a zero if (in) next_state = one; else next_state = zero; one: // we've seen one if (in) egin next_state = one; out = ; else egin next_state = zero; out = ; case module / zero [] one [] / / /
Synchronous Mealy Machine module reduce (clk, reset, in, out); input clk, reset, in; output out; reg out; reg state; // state variales always @(posedge clk) if (reset) state = zero; else case (state) zero: egin out = ; // last input was a zero if (in) state = one; else state = zero; one: // we've seen one if (in) egin state = one; out = ; else egin state = zero; out = ; case module
Example: Traffic light controller Highway/farm road intersection farm road car sensors highway
Traffic light controller (cont.) Detectors C sense the presence of cars waiting on the farm road with no car on farm road, light remain green in highway direction if vehicle on farm road, highway lights go from Green to Yellow to Red, allowing the farm road lights to ecome green these stay green only as long as a farm road car is detected ut never longer than a set interval; after the interval expires, farm lights transition from Green to Yellow to Red, allowing highway to return to green even if farm road vehicles are waiting, highway gets at least a set interval of green Assume you have an interval timer that generates: a short time pulse (TS) and a long time pulse (TL), in response to a set (ST) signal. TS is to e used for timing yellow lights and TL for green lights
Traffic light controller (cont.) inputs description outputs description reset place FSM in initial state HG, HY, HR assert green/yellow/red highway lights C detect vehicle on the farm road FG, FY, FR assert green/yellow/red highway lights TS short time interval expired ST start timing a short or long interval TL long time interval expired state description HG highway green (farm road red) HY highway yellow (farm road red) FG farm road green (highway red) FY farm road yellow (highway red) (TL C)' TL C / ST HG Reset TS / ST TS' HY FY TS' TS / ST FG TL+C' / ST (TL+C')'
Traffic light controller (cont.) Generate state tale with symolic states Consider state assignments output encoding similar prolem to state assignment (Green =, Yellow =, Red = ) Inputs Present State Next State Outputs C TL TS ST H F HG HG Green Red HG HG Green Red HG HY Green Red HY HY Yellow Red HY FG Yellow Red FG FG Red Green FG FY Red Green FG FY Red Green FY FY Red Yellow FY HG Red Yellow SA: HG = HY = FG = FY = SA2: HG = HY = FG = FY = SA3: HG = HY = FG = FY = (one-hot)
Traffic light controller FSM Specification of inputs, outputs, and state elements module FSM(HR, HY, HG, FR, FY, FG, ST, TS, TL, C, reset, Clk); output HR; output HY; output HG; parameter highwaygreen = 6'; output FR; parameter highwayyellow = 6'; output FY; parameter farmroadgreen = 6'; output FG; parameter farmroadyellow = 6'; output ST; input TS; input TL; assign HR = state[6]; input C; assign HY = state[5]; input reset; assign HG = state[4]; input Clk; assign FR = state[3]; assign FY = state[2]; reg [6:] state; assign FG = state[]; reg ST; specify state its and codes for each state as well as connections to outputs
Traffic light controller FSM initial egin state = highwaygreen; ST = ; always @(posedge Clk) egin if (reset) egin state = highwaygreen; ST = ; else egin ST = ; case (state) highwaygreen: module case statement triggerred y clock edge if (TL & C) egin state = highwayyellow; ST = ; highwayyellow: if (TS) egin state = farmroadgreen; ST = ; farmroadgreen: if (TL!C) egin state = farmroadyellow; ST = ; farmroadyellow: if (TS) egin state = highwaygreen; ST = ; case
Timer FSM for traffic light controller module Timer(TS, TL, ST, Clk); output TS; output TL; input ST; input Clk; integer value; assign TS = (value >= 4); // 5 cycles after reset assign TL = (value >= 4); // 5 cycles after reset always @(posedge ST) value = ; // async reset always @(posedge Clk) value = value + ; module
Complete traffic light controller Tying it all together (FSM + timer) with structural Verilog (same as a schematic drawing) module main(hr, HY, HG, FR, FY, FG, reset, C, Clk); output HR, HY, HG, FR, FY, FG; input reset, C, Clk; Timer part(ts, TL, ST, Clk); FSM part2(hr, HY, HG, FR, FY, FG, ST, TS, TL, C, reset, Clk); module traffic light controller ST timer TS TL
Finite state machines summary Models for representing sequential circuits astraction of sequential elements finite state machines and their state diagrams inputs/outputs Mealy, Moore, and synchronous Mealy machines Finite state machine design procedure deriving state diagram deriving state transition tale determining next state and output functions implementing cominational logic Hardware description languages Use good coding style Communicating FSMs