Control in Digital Systems

CONTROL CIRCUITS

Control in Digital Systems Three primary components of digital systems Datapath (does the work) Control (manager, controller) Memory (storage) B. Baas 256

Control in Digital Systems Control blocks in chips Typically small amount of HW Typically substantial verilog code Therefore: We typically do not care about small circuit area We typically do not care about fast circuits A possible exception is in cases of data-depent control. For example, if arithmetic is required to make control decisions e.g., "change states if sum < phase" Verilog code can be complex Many opportunities for bugs May be impossible to test all states and transitions Often the focus of testing by Verification Engineers B. Baas 257

Sequential Logic Combinational circuits outputs are a function of the circuit s inputs and a time delay Sequential circuits outputs are a function of the circuit s inputs, previous circuit state, and a time delay input logic output c_state state B. Baas 258

Control with Finite State Machines Of course we can design all standard finite state machines we learned in basic logic design classes Moore type FSM outputs dep only on the present state (state below) Mealy type FSM outputs dep on the present state and the inputs input logic output c_state state B. Baas 259

Design process Writing Verilog for State Machines Think Draw state diagrams if helpful Draw block diagrams if helpful Draw timing diagrams Pick descriptive signal names Think Then Write verilog Test it B. Baas 260

#1 Design Goal for Controllers: Clarity Clear code bugs will be less likely It is even more important to use good signal naming conventions in control logic than with other digital circuits Ex: state_c state Reduce the amount of state if possible (clarity) Ex: It may be better to have one global state machine instead of two separate ones Increase the amount of state if helpful (clarity) Ex: It may be better to have two separate global state machines instead of a single global one Ex: Instantiate separate counters to count indepent events B. Baas 261

I. Counters Typically the output is equal to the state of the counter Frequently the next state is the present state plus a fixed number Ring Counter Count Up Counter Count Down Counter B. Baas 262

II. General FSMs Typically the output is derived from the state but it is not a copy of it The state can be encoded with a compact binary representation Ex: 5 states 3 bits has 8 possible states The state can be encoded one hot with the number of flip-flops equal to the number of states Ex: 5 states 5 state bits B. Baas 263

Good Sequential Circuit Coding Style Example combinational circuit with output freq_c Always declare default values at beginning of always blocks Use all of the best combinational logic design practices gets the final word higher priority or precedence //--- this "always" block instantiates the combinational logic always @(freq or xyz or abc or reset) begin // defaults freq_c = freq; // hold previous value in this case // logic case (freq) begin 3 b000: freq_c = abc; 3 b001: freq_c = abc+3 b001; default: freq_c = 3 bxxx; // error case case // logic if (xyz==4 b0010) begin freq_c = abc; reset abc xyz // reset logic is usually last in always block for highest priority if (reset == 1 b1) begin freq_c = 3 b000; logic freq_c clock freq //--- this "always" block instantiates the register always @(posedge clock) begin freq <= #1 freq_c; B. Baas 264

Characteristics of Virtually Every Well-Designed Verilog State Machine 1) Default: state_c = state; 2) case (state) 3) STATE: begin... for each state. Partition design by state. In traditional 180A-style design, we partition the overall design by bits of the state. 4) if (reset == 1 b1) at the of the combinational always block 5) Instantiate FF register(s) in a separate always block // this "always" block instantiates the combinational logic always @(state or reset or...) begin // defaults state_c = state; // hold previous value in this case case (state) begin INIT: begin... // Add a block for each state default: c_freq = 3 bxxx; // error case case reset logic state_c clock state // reset logic often last in always block for highest priority if (reset == 1 b1) begin state_c = 3 b000; // this "always" block instantiates the register always @(posedge clock) begin state <= #1 state_c; B. Baas 265

Characteristics of a Well-Designed Verilog State Machine with Integrated Counters 1) In the default section, it is probably a good idea to have an autoincrement or auto-decrement statement count_c = count + 8 h01; // Example increment count_c = count - 8 h01; // Example decrement 2) In the idle or wait state, it is probably a good idea to hold the counter value to eliminate unnecessary toggling to reduce power dissipation count_c = count; // Example hold counter value count_c = 8 h00; // Example hold counter at zero B. Baas 266

Example Controller Specification Four states IDLE Go to PREP when go is asserted PREP Do something for 10 cycles Go to JOB1 if x <= 5 Go to JOB2 if x > 5 JOB1 Do something for 5 cycles, then go to IDLE JOB2 Do something for 20 cycles, then go to IDLE reset at any time returns control to IDLE B. Baas 267

Control Block Example Solution (There are many solutions!) State registers Choose two bits (obviously the minimum) since there are four states Counter(s) Choose one five bit counter since states are indepent and counter can be shared between different states Counting down may be slightly better (simpler comparator for all uses compares with zero) Safest to keep registers (flip-flops) separate from state machine logic Always do this for this class It is normally clearer to define states with names (such as IDLE) rather than constants (such as 2'b01) B. Baas 268

Example State Machine State diagram reset IDLE go PREP 10 cycles x <= 5 x > 5 JOB1 5 cycles JOB2 20 cycles B. Baas 269

Example State Machine (untested, could have bugs especially syntax or off-by-one-cycle bugs) parameter IDLE = 2 h0; // constants in hex notation parameter PREP = 2 h1; parameter JOB1 = 2 h2; parameter JOB2 = 2 h3; reg [1:0] state, c_state; // declare both FF regs reg [4:0] count, c_count; // and comb. logic regs // Combinational logic for state machine always @(state or count or go or x or reset) begin // defaults (place first) c_state = state; // default same state c_count = count 5 b00001; // default count down // main state machine logic case (state) IDLE: begin if (go) begin c_state = PREP; c_count = 5 d10; // constant in decimal else begin c_count = 0; // only for lower power PREP: begin if (count == 5 b00000) begin if (x <= 5) begin // goto JOB1 c_state = JOB1; c_count = 5 d05; else begin // goto JOB2 c_state = JOB2; c_count = 5 d20; // PREP JOB1: begin if (count == 5 b00000) begin c_state = IDLE; // count will underflow to 1 but it is ok JOB2: begin if (count == 5 b00000) begin c_state = IDLE; // count will underflow to 1 but it is ok default: begin // good practice, but not used here c_state = 2 bxx; // better for testing c_state = IDLE; // another option case // reset logic (place last to override other logic) if (reset == 1 b1) begin c_state = IDLE; c_count = 5 b00000; // of always block // Instantiates registers (flip-flops) always @(posedge clk) begin state <= #1 c_state; count <= #1 c_count; I think it is better to put reset logic inside the control logic rather than with the FF declaration B. Baas 270