The 8237 DMA Controller: - The 8237 is the LSI controller IC that is widely used to implement the direct memory access (DMA) function in 8088 and 8086 based microcomputer systems. It is available in 40-pin DIP. DMA capability permits devices, such as peripherals, to perform high-speed data transfers between either two sections of memory or between memory and I/O device. DMA controller instead of MPU performs bus cycles related to DMA transfer. A single 8237 can support up to four peripheral devices for DMA operation. The 8237 is capable of DMA transfers at rates of up to.6 M bytes per second. Each channel is capable of addressing a full 64 Kbytes section of memory and can transfer up to 64 Kbytes with a single programming. Pin Functions: - CLK Clock CS Chip Select RESET Reset READY Wait states are caused when 0 HLDA Hold Acknowledge DREQ 3 -DREQ 0 DMA request inputs DB 7 -DB 0 Data bus IOR I/O read IOW I/O write EOP End-of-process A 3 -A 0 These address pins selects an internal register A 7 -A 4 These address pins are outputs HRQ Hold request (output), connects to the HOLD input of microprocessor DACK 3 -DACK 0 DMA Channel Acknowledge (outputs), acknowledge a channel DMA request AEN Address enable signal enables the address latch connected to DB 7 -DB 0 pins ADSTB Address strobe functions as ALE MEMR Memory read is an output control signal MEMW Memory write is an output control signal
Internal Registers: - Name Size Number Base Address Registers (BAR) 6 bits 4 Base Word Count Registers (BWCR) 6 bits 4 Current Address Registers (CAR) 6 bits 4 Current Word Count Registers (CWCR) 6 bits 4 Temporary Address Register 6 bits Temporary Word Count Register 6 bits Status Register 8 bits Command Register 8 bits Temporary Register 8 bits Mode Registers 6 bits 4 Mask Register 4 bits Request Register 4 bits Accessing the Registers of the 8237A: - Channel(s) Register Operation I/O address Internal relative to FF the base 0 Base and current address Write 0 0 Current address Read 0 0 Base and current count Write 0 Current count Read 0 Base and current address Write 2 0 Current address Read 2 0 Data bus
Base and current count Write 3 0 Current count Read 3 0 2 Base and current address Write 4 0 Current address Read 4 0 Base and current count Write 5 0 Current count Read 5 0 3 Base and current address Write 6 0 Current address Read 6 0 Base and current count Write 7 0 Current count Read 7 0 All Command register Write 8 X All Status register Read 8 X All Request register Write 9 X All Mask register Write A X All Mode register Write B X All Temporary register Read B X All Clear internal FF Write C X All Master clear Write D X All Clear mask register Write E X All Mask register Write F X
Each DMA channel has two address registers: BAR: it holds the starting address for the DMA operation. CAR: it contains the address of the next storage location to be accessed. Writing a value to the BAR automatically loads the same value into the CAR. Therefore, initially the CAR points to the starting I/O or memory address. Each DMA channel has two word count registers: BWCR: The number of bytes of data that are to be transferred during a DMA operation is specified by the value of this register. CWCR: At any time during the DMA cycle, the value in this register tells how many bytes remain to be transferred. The number of bytes transferred is always one more than the value programmed into the BWCR. This is because the end of a DMA cycle is detected by the rollover of the current word count from 0000h to FFFFh. Command Register: It is an 8-bit register. The bits in this register used to control the operating modes that apply to all channels of the DMA controller. Mode Registers: There is a separate mode register for each of the four DMA channels and that they are each 6 bits in length. There bits are used to select various operational features for the individual DMA channels. Request Register: It is used to request a DMA transfer in block mode via software. This is very useful in memory-to-memory transfer where an external signal is not available to begin the DMA transfer. Mask Register: It is a 4-bit register. One bit is provided in this register for each of the DMA channels. When a mask bit is set, the DREQ input for the corresponding channel is disabled. Therefore, hardware requests to the channel are ignored. On the other hand, if the mask bit is cleared, the DREQ input is enabled and its channel can be activated by an external device. Status Register: It is an 8-bit register. It shows the status of each DMA channel. TC means Terminal Count. Whenever the terminal count is reached, the DMA transfer is terminated for most modes of operation. The request bits indicate if the DREQ input for a given channel is active.
Temporary Register: It is used to store data temporarily when memory-to-memory DMA transfer occurs. Software Commands: - Three software commands are used to control the operation of the 8237. These commands do not have a binary pattern, as do the various control registers within the 8237. A simple output to the correct port number enables the software command. The function of the software commands are explained in the following list:. Clear the first/last flip-flop: Clears the first/last (F/L) flip-flop within the 8237. The F/L flip-flop selects which byte (low or high order) is read/written in the current address and current count registers. If F/L = 0, the low order byte is selected, If F/L =, the high order byte is selected. Any read or write to the address or count register automatically toggles the F/L flip-flop. 2. Master clear: Acts exactly the same as the RESET signal to the 8237. As with the reset signal, this command disables all channels. 3. Clear mask register: Enables all four DMA channels. Programming the Address and Count Registers: - There are four steps required to perform the 8237:. the F/L flip-flop is cleared using a clear F/L command. 2. the channel is disabled. 3. the LSB and then MSB of the address are programmed, and 4. the LSB and MSB of the count are programmed. Once these four operations are performed, the channel is programmed and ready to use. Additional programming is required to select the mode of operation before the channel is enabled and started.
DMA Interface for 8088 using 8237A: - I/O devices request DMA service by activating one of the 8237A s DMA request inputs, DREQ0 through DREQ3. When the 8237A receives a valid DMA request on one these lines, it sends a hold request to the HOLD input of the 8088 by setting the HRQ output to logic. After the 8088 gives up control of the system buses, it acknowledges by switching its HLDA output to the logic level. DMA controller receives this signal on its HLDA input, which means system buses are available for DMA transfer. DMA control signals to the device that is requesting service by activating its DMA acknowledge (DACK) line. AEN signal is used to put the data bus lines of microprocessor in high impedance state by applying logic at HOLD. If multiple requests for DMA service are received by the 8237A, they are accepted on a priority basis. One of two priority schemes can be selected for the 8237A under software control. They are called: Fixed priority. Rotating priority. The fixed priority mode assigns priority to the channels in descending numeric order. That is, channel 0 has the highest priority and channel 3 has the lowest priority.