Alternatives on the Road to 3D TSV E. Jan Vardaman President TechSearch International, Inc. www.techsearchinc.com
Everyone Wants to Have 3D ICs 3D IC solves interconnect delay problem bandwidth bottleneck Device latency Power management issues But there are issues before HVM EDA tool availability Manufacturing process yield (especially for temporary bond/ debond in wafer thinning) Thermal, where logic is part of stack Test and reliability Business infrastructure Cost compared to alternatives Source: Intel
Form factor, performance driven Roadmaps shifted out 3D ICs Source: Samsung Source: Renesas
Why 3D Logic + Memory? Wide I/O enables thinner and smaller form factors Relentless need for increased memory bandwidth and improved memory power efficiency Memory interface is the highest bandwidth interface in the system System performance tied to memory bandwidth (especially for graphics oriented devices) Memory power a growing portion of overall system power Source: Intel
Prototype Stacked DRAM with TSV (3D IC) DRAM prototypes and programs Elpida Hynix Micron Nanya Samsung Tezzaron highspeed SRAM memory Samsung announcements IBM and Intel have agreements with Micron for cube Elpida expected to be acquired by Micron Source: Tezzaron Source: Elpida
Alternatives to 3D IC with TSVs Novel ways to extend current technology 2.5D interposers with TSVs (Remember the MCM!!) Allows partitioned design (large chips can be partitioned into smaller ones) Manage chip/package interaction stress for large die with ultra low-k dielectrics Can incorporate integrated passives An interim solution before 3D IC with TSV is possible Planar module with stacked memory adjacent to the processor for high speed memory requirements, can be tested prior to stacking Stacked die with wire bond and/or flip chip Chip-on-chip Stacked Packages (packages can be tested, infrastructure exists) PoP Embedded die in bottom PoP Fan-out for bottom PoP
Fujitsu s Packaging Roadmap Alternatives to 3D IC with memory and logic stack Source: Fujitsu
2.5D (Silicon Interposer) Era Has Arrived FPGA shipments started Xilinx Altera ASIC designs Many companies CPU/GPU plans Potential processor + memory SiP for mobile products Source: Xilinx!
IBM s Silicon Interposer IBM working with Semtech to develop a silicon interposer to connect analog converter functions in a logic device with an interleaver IC in IBM s BiCMOS SiGe technology Applications are fiber optic telecom, high-performance RF, test equipment, processing for radar systems Source: IBM
Xilinx Heterogeneous Integration on Interposer Highest bandwidth FPGA with 2.78 Tb/s serial connectivity Form-fit-function die for varying design requirements Electrically isolated 28G transceivers for optimal signal integrity Process: 40nm High Performance Process: 28nm High Performance Low Power Process: 65nm 13G Transceivers Noise Isolation: Digital and analog separated for lowest noise and jitter Source: Xilinx Page 10 Copyright 2012 Xilinx
Altera Adopts TSMC s CoWoS Test vehicle announced CoWoS allows for mixing and matching multiple technologies in a single device Consolidates manufacturing and assembly Lowest risk Optimal yields Cu connection Source: Altera!
Types of Silicon Interposers Foundry Interposers with TSVs ALLVIA TSMC UMC IBM GLOBALFOUNDRIES Novati Technologies OSAT Interposers with TSVs ASE SPIL Interposers for MEMS with TSVs DNP IMT Silex Microsystems Interposers with Integrated Passives (with or without TSVs) IPDiA STATS ChipPAC Source: DNP Source: IPDiA
Effect of Interposers on 3D IC Forecast 3D-ICs, old forecast 3D-ICs, new forecast TSV Interposers 2010 2012 2014 2016 2018 Source: TechSearch International, Inc.
History of Silicon Substrates Early developments from AT&T Bell Labs, IBM, Toshiba, NEC, and others Large Panel MCM-D Consortium (Glass) Thin Film on Silicon Substrates Intel IBM Micro Module Systems (MMS) nchip Many Japanese companies such as Toshiba and NEC Source: MMS Source: nchip
MCM Company Cemetery Source: TechSearch International, Inc.
Chip-on-Chip in Sony s PSP and PS Vita Memory can be fabricated separately and assembled to the processor Provides a wide bus, high-speed memory interface needed for graphics image processor Source: ChipWorks
3D and High Density Packaging in Smartphones Source: Amkor
Package-on-Package (PoP) Individual packages are stacked on top of each other Separate package for logic Separate package for memory Packages individually tested before stacking Smartphones and tablets use PoP, some digital cameras New developments enabling thinner packages Embedded PoP with die embedded in the substrate of the bottom package ewlb versions using a fan-out technology Source: Amkor
Drivers for Decreasing PoP Package Thickness
STATS ChipPAC 5-Die ewlb PoP Total package height for total of 5 die (top and bottom packages), including solder balls, <1.0 mm Package is 12 mm x 12 mm Source: STATS ChipPAC
Moore s Law ASE Package Roadmap 90 nm 65 nm 45 / 40 nm 32 / 28 nm Advanced Wafer Nodes FCBGA LF LK LF ELK LF w/ TSV Interposer QFP PBGA Cost Performance FCCSP aqfn a-fccsp as 3 BGA DIP PLCC SOJ Ref.: Jisso SOP MCP System Integration Stacked Die Miniaturization Density QFN COL QFN FBGA Time PoP FC MCM WLCSP FC+WB MAPPoP Single Die Module amappop Single die+ Passives Side by Side 2010 2011 Fan-In PoP - EP PoP 3 Die+Discrete 2012 Source: ASE Stacked PoP
Conclusions Real engineering work underway for 3D ICs Structures have be fabricated Process improvements are still needed Applications for TSVs Image sensors and MEMs are in production today (backside via) Research on wireless applications High-speed logic (processors, FPGAs) Future memory applications, depends on cost trade-off and reliability data Cost/Performance trade-off determines adoption for each application Silicon interposer adoption underway (2.5D solution) but remaining issues Suppliers for foundry-type Assembly infrastructure, including handling, test? Alternatives include 3D packages such as PoP, wire bond stacks, WB/FC stacks, CoC