Digital Integrated Circuits Lecture 3 Jaeyong Chung System-on-Chips (SoC) Laboratory Incheon National University
GENERAL MODEL OF MEALY MACHINE Chung EPC6055 2
GENERAL MODEL OF MOORE MACHINE Chung EPC6055 3
MOORE SEQUENTIAL CIRCUIT Mealy Outputs Depend on Both Present State and Inputs Moore Outputs Depend Only on Present State Easier to Design and Debug Than Mealy Often Contain More States Than Mealy Chung EPC6055 4
SEQUENCE DETECTOR Circuit examines string of 0 s and 1 s applied to X input Generates output Z=1 only when input sequence is 101 Input X can change only between clock pulses Output Z=1 coincident with last 1 in 101 Circuit does not reset when 1 output occurs X= 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 Z= 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 Chung EPC6055 5
SEQUENCE DETECTOR Chung EPC6055 6
K-MAPS FOR NEXT STATE/OUTPUT Chung EPC6055 7
CIRCUIT FOR SEQUENCE DETECTOR Chung EPC6055 8
STATE GRAPH OF MOORE SEQUENCE DETECTOR Sequence to be detected - 101 Circuit does not reset when 1 output occurs The last 1 in 101 can be first 1 for next 101 Chung EPC6055 9
FOUR KINDS OF TRI-STATE DRIVERS Chung EPC6055 10
DATA TRANSFER USING TRI-STATE BUSSES Chung EPC6055 11
TYPES OF DESCRIPTIONS Chung EPC6055 12
NUMBER EXPRESSION IN VERILOG Chung EPC6055 13
NUMBER EXPRESSION IN VERILOG You can insert _ for readability 12 b 000_111_010_100 12 b 000111010100 12 o 07_24 Bit extension MS bit=0, x or z extend this 4 b x1 = 4 b xx_x1 MS bit=1 zero extension 4 b 1x = 4 b 00_1x Truncation Represent the same number Chung EPC6055 14
VERILOG SYNTAX Sequential Logic always statement (Procedural Construct) Format : always @ (sensitivity lists) begin end Executes Whenever Sensitivity Lists Change Can Also Be Used for Combinational Logic Design Chung EPC6055 15
VERILOG SYNTAX Sequential Logic D Flip-Flop Chung EPC6055 16
VERILOG SYNTAX Sequential Logic Asynchronous Reset D Flip-Flop Rest Asynchronous to CLK RST Chung EPC6055 17
VERILOG SYNTAX Sequential Logic Synchronous Reset D Flip-Flop Rest Synchronous to CLK RST Chung EPC6055 18
VERILOG SYNTAX always in Combinational Logic 2:1 Mux Example Chung EPC6055 19
VERILOG SYNTAX Control Statement if-else if (condition1) begin //function1 end else begin //else end Chung EPC6055 20
VERILOG SYNTAX Control Statement case case (check) check_case1 : ~~ ; //function check_case2 : ~~ ; //function : default : ~~; //Nothing Meets Above Conditions endcase Chung EPC6055 21
VERILOG SYNTAX Control Statement case case (check) check_case1 : ~~ ; //function check_case2 : ~~ ; //function : default : ~~; //Nothing Meets Above Conditions endcase Chung EPC6055 22
VERILOG SYNTAX Control Statement while : Loop Continues when Condition True while (condition) begin ~~ end for : Like in C/C++, But ++, -- Not Allowed for (condition) begin ~~ end repeat : Explicitly Give Number of Iterations loop (num_of_iteration) begin ~~ end Chung EPC6055 23
VERILOG SYNTAX Blocking vs. Non-blocking Statement Blocking Statement (= operator) Each statement Executed in Sequential Order within their blocks. Chung EPC6055 24
VERILOG SYNTAX Blocking vs. Non-blocking Statement Non-blocking Statement (<= operator) Schedule Assignments without Blocking the procedural flow. Chung EPC6055 25
PROCEDURAL TIMING CONTROL Delay controls #<time> <statement>; Delays the execution of a procedural statement by specific simulation time The right side expression is evaluated after the delay or event control Intra-assignment timing controls Ex> a = #20 b&c; Intra-assignment controls always evaluate the right side expression immediately and assign the result after the delay or event control Chung EPC6055 26
VERILOG SYNTAX Blocking vs. Non-blocking Statement Example begin a = #10 1 b1; b = #20 1 b0; c = #40 1 b1; end begin a <= #10 1 b1; b <= #20 1 b0; c <= #40 1 b1; end a b c a b c 10 20 30 40 50 60 70 80 10 20 30 40 50 60 70 80 Chung EPC6055 27
TIMESCALE `timescale <Time Unit>/<Time Precision> A compiler directive that sets the simulation s time unit size and precision. <Time Unit>: constant multiplier of time values <Time Precision>: minimum step size during simulation, which determines rounding of numerical values. Examples `timescale 1ns/1ps Chung EPC6055 28
VERILOG SYNTAX Blocking vs. Non-blocking Statement H/W Implementation module blocking (clk,a,c); input clk; input a; output c; wire clk; wire a; reg c; reg b; a D Q b always @ (posedge clk ) begin b = a; c = b; end clk c endmodule Chung EPC6055 29
VERILOG SYNTAX Blocking vs. Non-blocking Statement H/W Implementation module blocking (clk,a,c); input clk; input a; output c; wire clk; wire a; reg c; reg b; a D Q D Q b c always @(posedge clk) begin b <= a; c <= b; end endmodule Chung EPC6055 30
SEQUENCE DETECTOR IN VERILOG module seqdec(clk, x, z); input clk; input x; output z; wire xb,a,b; not i0(xb, x); and a0(z, a, x); and a1(a_in, xb, b); d_ff a_reg(a_in, clk, a); d_ff b_reg(x, clk, b); endmodule Chung EPC6055 31
SEQUENCE DETECTOR IN VERILOG Chung EPC6055 32
SEQUENCE DETECTOR IN VERILOG `timescale 1ns/1ns module seqdec_tb; reg clk, x; wire z; seqdec sd0 (clk, x, z); initial begin clk = 1; end always begin #50 clk <= ~clk; end initial begin #1 x = 0; #100 x = 0; #100 x = 0; #100 x = 0; #100 x = 1; #100 x = 1; #100 x = 0; #100 x = 1; #100 x = 1;.. end endmodule Chung EPC6055 33
SEQUENCE DETECTOR IN VERILOG Chung EPC6055 34