EE 3170 Microcontroller Applications

Block Diagram of 68HC11A8 EE 3170 Microcontroller Applications Lecture 14: Advanced 68HC11 Hardware- PartI A: Measuring Real-Time in the 68HC11 - Miller 7.7-7.8 Based on slides for ECE3170 by Profs. Davis, Kieckhafer, Tan, and Cischke Interrupt control Clock Mode control A/D ref. voltage Chip power COP Real-Time Interrupt ROM RAM EEPROM Microprocessor Timer & Pulse Accumulator SCI SPI A/D converter Port A Port B Port C Strobe Port D Port E EE3170/CC/Lecture#14-PartIA 1 EE3170/CC/Lecture#14-PartIA 2 Block Diagram of 68HC11A8 68HC11A8 Components COP PULSE ACCUMULATOR MODA/ LIR MODE CONTROL TIMER SYSTEM PORT A MODB/ V STBY PERIODIC INTERRUPT PA7/PAI/OC1 PA6/OC2/OC1 PA5/OC3/OC1 PA4/OC4/OC1 PA3/OC5/OC1 PA2/IC1 PA1/IC2 PA0/IC3 XTAL EXTAL OSCILLATOR CLOCK LOGIC PORT B E BUS EXPANSION ADDRESS PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 CPU IRQ/ XIRQ STROBE AND HANDSHAKE PARALLEL I/O SINGLE CHIP MODE INTERRUPT LOGIC ADDRESS/DATA CONTROL PORT C RESET R/W AS PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 STRB STRA A15 A14 A13 A12 A11 A10 A9 A8 A7/D7 A6/D6 A5/D5 A4/D4 A3/D3 A2/D2 A1/D1 A0/D0 R/W AS EXPANDED MODE CIRCUITRY ENCLOSED BY DOTTED LINE IS EQUIVALENT TO MC68HC24. SS SCK SPI MOSI MISO PD5/SS PD4/SCK PD3/MOSI PD2/MISO 8 KBYTES ROM 512 BYTES EEPROM 256 BYTES RAM CONTROL PORT D SCI TxD RxD PD1/TxD PD0/RxD A/D CONVERTER PORT E PE7/AN7 PE6/AN6 PE5/AN5 PE4/AN4 PE3/AN3 PE2/AN2 PE1/AN1 PE0/AN0 V DD V SS V RH V RL 1 Memory RAM ROM EEPROM Parallel Input/Output Port B Port C Strobe STRA STRB Programmable Timer & Pulse Accumulator Port A SCI (SPI) Serial Communications (Peripheral) Interface Port D Analog-to-Digital Converter Port E EE3170/CC/Lecture#14-PartIA Figure 1-1 Block Diagram 3 EE3170/CC/Lecture#14-PartIA 4

Lecture Overview The 4 Main 68HC11 Timer Functions Real-Time Interrupt Free-Running Counter Input Capture (time stamping) Output Compare (scheduling) Examples RTI Interrupt : Derived Real-Time Clock IC interrupt : Measuring the interval between two events OC interrupt : Generating a slow external clock Real-Time Real-Time (RT) = the perfect, ideal time base of the cosmos (e.g. the master clock of the gods) Ignoring relativistic and quantum effects: RT proceeds at a constant rate of progress RT is a continuous (non-discrete) function RT can not be measured or read precisely RT can only be approximated by a clock clocks have finite precision (tick length) clock accuracy (tick rate) varies a bit over time clock accuracies differ a bit from each other Real Real-Time A system that can guarantee an upper bound (worst case) on latency (response time) for time-critical operations. EE3170/CC/Lecture#14-PartIA 5 EE3170/CC/Lecture#14-PartIA 6 Underlying Time-Base Clock Functions Basic Clock Counter consists of a counter register increments once per crystal oscillator cycle when it overflows it rolls over from FF FF to 00...00 it asserts an overflow signal Counter acts as the basic time-base for the processor Defines the smallest available precision Various clocks can be derived from the counter Fixed-Period Timer Interrupt: allows processor to update a derived RT clock each interrupt = 1 tick of the RT clock Free Running Counter Software can load the counter value at any time Input Capture (IC) records counter value at instant an input signal arrives used to timestamp arrival of the input signal Output Compare (OC) asserts output signal at a specified counter value used to schedule an output pulse (or command) EE3170/CC/Lecture#14-PartIA 7 EE3170/CC/Lecture#14-PartIA 8

Motivations: Real-time Interrupt Clock Perform I/O operations at specific times Time Tracking Use I/O device that causes interrupts periodically An oscillator sets a flag at the end of each period Interrupt service routine can count interrupts to track time Refer to figure 7-7 Function 1: Real-Time Interrupt (RTI) Real-Time Interrupt (RTI) Hardware: an internal I/O device (oscillator) w/ a flag that cause periodic interrupts. Oscillator Rate Control (RTR1 & RTR0) Programmable Counter 4.10ms, 8.19ms, 16.38ms, 32.77ms Real-Time Interrupt Flag (RTIF) Real-Time Interrupt Enable (RTII) Interrupt Vector $FFF0 - $FFF1 Note -TMSK2: Timer Interrupt Mask Reg.; TFLG2: Time Flag Reg.; PACTL: Pulse Accumulator Control Reg. $1024 TOI RTII PR1 PR0 TMSK2 $1025 TOF RTIF TFLG2 $1026 RTR1 RTR0 PACTL EE3170/CC/Lecture#14-PartIA 9 EE3170/CC/Lecture#14-PartIA 10 Function 1 - Real-Time Interrupt (RTI) Warning: there is also RTI (Return from InTerrupt) instruction RTIF Flag is set by Counter Overflow signal RTIF = bit-6 of TFLG2 reg @ $1025 RTIF causes interrupt to vector @ $FFF0:$FFF1 RTIF is a Direct-Clearing flag (store 1 to clear) RTII bit enables/disables RTIF interrupt RTII- bit 6 of TMSK2 register @ $1024 RTII - 1 RTI is enabled I bit of CC register also enables/disables RTI RTI Frequency Control Relative Frequencies All are derived from processor crystal frequency (usually 8 MHz) E-Clock freq. = crystal freq. / 4 RTI freq. = E-Clock freq. / D = crystal freq. / (4D) where D is a programmable frequency divider RTR0 and RTR1 bits determine value of D RTR0 and RTR1 are bits 0 and 1 of PACTL register @ $1026 EE3170/CC/Lecture#14-PartIA 11 EE3170/CC/Lecture#14-PartIA 12

RTI Frequency Control Want RTI period to be long (several ms) otherwise processor spends too much time in ISR don t necessarily need extreme accuracy Frequency Divider Values (with 8 MHz crystal) RTR1 RTR0 D RTI period 0 0 2 13 4.1 ms. 0 1 2 14 8.2 ms. 1 0 2 15 16.4 ms. 1 1 2 16 32.8 ms. The Programmable Timer HC11 contains a hardware timer: can measure time for both inputs and outputs (time measurement) Its characteristics are programmable w/ software It uses interrupt system and has several interrupt vectors Free-Running Counter 16-bit Up-Counter clocked by an oscillator $0000 - $FFFF Roll-Over (Overflow) TOF Time base for all timer functions Timer Input Capture (IC) 16-bit Capture Registers TIC1 - TIC3 Measure elapsed times between events Timer Output Compare (OC) 16-bit Compare Registers TOC1 - TOC5 Control timing of events EE3170/CC/Lecture#14-PartIA 13 EE3170/CC/Lecture#14-PartIA 14 Function 2: Free-Running Counter Function 2: Free-Running Counter (TCTN) Free Running Counter A rollover 16-bit up-counter Value stored in 16-bit TCNT reg @ $100E:$100F TOF Interrupt PR1 PR0 Counter can be accessed for several purposes read by a program time-stamp an input accurately schedule an output Note: Free running counter is a completely separate hardware device from the RTI counter. TOI (Interrupt TOF enable) (Timer overflow flag) Free-running counter Prescaler E Clock EE3170/CC/Lecture#14-PartIA 15 EE3170/CC/Lecture#14-PartIA 16

TCNT 16-bit Counter Located at $100E-100F Rate determined by PR1 and PR0 (bits 0 and 1) in TMSK2 register ($1024) Overflow from FFFF to 0 sets the TOF flag (bit 7) of the TFLG2 register ($1025) causing an interrupt of the TOI mask (bit 7) of the TMSK2 register is 1 Free-Running Counter Control TOF - Timer Overflow Bit bit 7 of TFLG2 reg @ $1025 set when TCNT rolls over from FFFF to 0000 TOI - Timer Overflow Interrupt Enable Bit bit 7 of TMSK2 register @ $1024 =1 Interrupt Enabled PR0 and PR1 set frequency of TCNT increment PR0 and PR1 = bits 0 and 1 of TMSK2 reg @ $1024 PR0 and PR1 set number of E-clock cycles per TCNT increment EE3170/CC/Lecture#14-PartIA 17 EE3170/CC/Lecture#14-PartIA 18 Frequency Control For TCNT to have very high accuracy Want fine granularity TCNT frequency = E-clock freq./d = crytal freq. / 4D Free-Running Counter Register Summary TCNT - Counter value register 16 bits @ $100E:$100F TOF = Counter Overflow Flag Bit TCNT precision (with 8 MHz crystal) PR1 PR0 D TCNT Prec TOF period 0 0 1 0.5 μs 32.8 ms 0 1 4 2.0 μs 131.1 ms 1 0 8 4.0 μs 262.1 ms 1 1 16 8.0 μs 524.3 ms TOI - Counter Overflow Interrupt Bit PR0 and PR1 - Counter Frequency Control Bits EE3170/CC/Lecture#14-PartIA 19 EE3170/CC/Lecture#14-PartIA 20

How Can We Use TCNT? With software can read TCNT e.g. ldd $100E can create fixed time delay shown in text (p346-347: figure 7-15) Directly control or monitor I/O IC = Input Capture = Time-stamping of inputs (figure 7-12) OC = Output compare = Scheduling of output signals (figure 7-13) Can stamp and schedule signals with hardware accuracy within μs Function 3 - Input Capture (IC) When an ICx input arrives TICx ( 3 of them) register gets a copy of the counter value in TCNT IC1 pin loads the TIC1 register @ $1010:$1011 IC2 pin loads the TIC2 register @ $1012:$1013 IC3 pin loads the TIC3 register @ $1014:$1015 Thus TICx register captures the time that ICx arrived. Software can not write to the TICx registers. it can only read them IC arrivals can also cause interrupts. EE3170/CC/Lecture#14-PartIA 21 EE3170/CC/Lecture#14-PartIA 22 Input Capture Input Capture Input Capture Hardware ICx interrupt Free-running counter EDGxB EDGxA ICx Input-Capture Flags: IC1F, IC2F, IC3F - IC Flag Bits IC1F, IC2F, IC3F - bits 2,1,0 of TFLG1 register @ $1023 Bit ICxF is set when signal ICx arrives $1023 OC1F OC2F OC3F OC4F OC5F IC1F IC2F IC3F TFLG1 ICxI (Interrupt ICxF enable) (ICx flag) TICx Edge control Interrupt-Enable: IC1I, IC2I, IC3I - IC Interrupt Enable Bits IC1I, IC2I, IC3I - bits 2,1,0 of TMSK1 register @ $1022 If bit ICxI = 1, then ICxF interrupt is enabled $1022 OC1I OC2I OC3I OC4I OC5I IC1I IC2I IC3I TMSK1 EE3170/CC/Lecture#14-PartIA 23 EE3170/CC/Lecture#14-PartIA 24

Input Capture Interrupt (table 7-2) Vector Address Interrupt Device FFEA - FFEB Timer Input Capture 3 FFEC - FFED Timer Input Capture 2 FFEE - FFEF Timer Input Capture 1 Input Capture (IC) Edge Control EDGxB, EDGxA - edge control bits for ICx pin bits 5 0 of TCTL2 register @ $1021 determine which edge transition on pin ICx triggers time capture EDGxB EDGxA Active Pin Transition 0 0 capture disabled 0 1 capture on rising edge 1 0 capture on falling edge 1 1 capture on both edges EE3170/CC/Lecture#14-PartIA 25 EE3170/CC/Lecture#14-PartIA 26 Function 4 - Output Compare Function 4 - Output Compare Function Free-running counter The program stores a value into a 16-bit Timer OMx OLx Output Compare (TOC) register. Hardware comparators continuously compare the Comparator OCx TOC registers to TCNT. if the TCNT register = a TOC register. then assert a signal on an OC output pin TCNT rolls over the equality will eventually occur. OCx interrupt TOCx Action control The TOC =TCNT event can also cause an interrupt. OCxI (Interrupt OCxF enable) (OCx flag) EE3170/CC/Lecture#14-PartIA 27 EE3170/CC/Lecture#14-PartIA 28

Output Compare (OC) Time Registers Input Capture and Output Capture Ports There are 5 OC output bits (OC1 OC5) Scheduled output time for pin OCx is stored in register TOCx. Time for OC1 pin in TOC1 register @ $1016:$1017 Time for OC2 pin in TOC2 register @ $1018:$1019 Time for OC3 pin in TOC3 register @ $101A:$101B Time for OC4 pin in TOC4 register @ $101C:$101D Time for OC5 pin in TOC5 register @ $101E:$101F IC and OC both use PORTA PA7 is bidirectional controlled by DDRA7 PA7/PAI/OC1 PA6/OC2/OC1 PA5/OC3/OC1 PA4/OC4/OC1 PA3/OC5/OC1 PA2/IC1 PA1/IC2 PA0/IC3 PULSE ACCUMULATOR Input Capture Pins Port A (DDRA7 = 0) Output Capture Pins Port A (DDRA7 = 1) PORT A TIMER SYSTEM COP PERIODIC INTERRUPT $1000 OC1 OC2 OC3 OC4 OC5 IC1 IC2 IC3 PORTA $1026 DDRA7 PACTL EE3170/CC/Lecture#14-PartIA 29 EE3170/CC/Lecture#14-PartIA 30 Output Compare Output Compare Hardware OCxF = OC flag bit for pin OCx OC1F OC5F = bits 7 3 of TFLG1 register @ $1023 OCxF bit is set when TOCx register = TCNT register $1023 OC1F OC2F OC3F OC4F OC5F IC1F IC2F IC3F TFLG1 OCxI = OC Interrupt enable bit for pin OCx OC1I OC5I = bits 7 3 of TMSK1 register @ $1022 if OCxI = 1 then OCx interrupt is enabled $1022 OC1I OC2I OC3I OC4I OC5I IC1I IC2I IC3I TMSK1 Output Compare (OC) Action Control OMx and OLx - action control bits for OCx pin OM2,OL2 OM5,OL5 = bits 7 0 of TCTL1 register @ $1020 OM1,OL1 = a special case OMx and OLx determine output on pin OCx Omx Olx Action Taken on Compare 0 0 OC output disabled (disconnect) 0 1 Toggle current pin output (complement) 1 0 Set output pin low 1 1 Set output pin high EE3170/CC/Lecture#14-PartIA 31 EE3170/CC/Lecture#14-PartIA 32

Output Compare Interrupt (table 7-2) Vector Address Interrupt Device FFE0 - FFE1 Timer Output Compare 5 FFE2 - FFE3 Timer Output Compare 4 FFE4 - FFE5 Timer Output Compare 3 FFE6 - FFE7 Timer Output Compare 2 FFE8 - FFE9 Timer Output Compare 1 RTI Interrupt Example RTI counts up to a certain time then Sets RTIF Flag (bit6 of TFLG2 Reg. @ $1025) If RTII bit (bit6 of TMSK2 Reg. @ $1024) is set, then causes RTI Interrupt Period determined by RTR1, RTR0 bits RTR1 RTR0 D RTI period (8 MHz) ) 0 0 2 13 4.1 ms. 0 1 2 14 8.2 ms. 1 0 2 15 16.4 ms. 1 1 2 16 32.8 ms. EE3170/CC/Lecture#14-PartIA 33 EE3170/CC/Lecture#14-PartIA 34 RTI Example RTI Example Typical Application: running a real-time clock (rtclk) Pick maximum period (32.8 ms) Maintain a 32-bit derived real-time clock 16-bit rollover period = 32.8ms x 2 16 = 35.8 minutes 32-bit rollover period = 32.8ms x 2 32 = 4.5 years /initialization //init SP //init rti int period //enable rti int /end INIT LDS $2FFF LDAA #$03 * Set RTI Period STAA PACTL * To 32.8 ms LDAA #$40 * Enable RTI STAA #TMSK2 CLI EE3170/CC/Lecture#14-PartIA 35 EE3170/CC/Lecture#14-PartIA 36

RTI Example IC3 Interrupt RTIISR /clear RTI Flag /inc rtclk low-order = 0? Y /inc rtclk high-order return N RTISR LDAA #$40 STAA TFLG2 RET LDD RTC_LO ADDD #1 STD RTC_LO * Inc RTC_LO BNE RET * Test for Rollover LDD RTC_HI ADDD #1 * Inc RTC_HI STD RTC_HI RTI Input Capture uses counter TCNT Records the TCNT value as an input arrives For input ICx, it stores in 16-bit register TICx Sets ICxF flag If ICxI bit is set, then causes TICx interrupt EDGxB, EDGxA define capture edge EDGxB EDGxA Active Pin Transition 0 0 capture disabled 0 1 capture on rising edge 1 0 capture on falling edge 1 1 capture on both edges EE3170/CC/Lecture#14-PartIA 37 EE3170/CC/Lecture#14-PartIA 38 IC3 Interrupt Typical Application -- Measuring Interval Between Events Calculate time between 2 rising edges on IC3. Pick maximum TCNT tick interval (8 μs) TCNT clock period set by bits PR1, PR0 PR1 PR0 D TCNT Prec TOF period 0 0 1 0.5 μs 32.8 ms 0 1 4 2.0 μs 131.1 ms 1 0 8 4.0 μs 262.1 ms 1 1 16 8.0 μs 524.3 ms OC2 Interrupt Output Compare uses counter TCNT Flags when TOCx register = TCNT value For input OCx, it value is in 16-bit register TOCx Sets OCxF flag If OCxI bit is set, then causes TOCx interrupt OMx and OLx define action taken at pin OCx OMx OLx Action Taken on Compare 0 0 OC output disabled 0 1 Toggle current pin output 1 0 Set output pin low 1 1 Set output pin high EE3170/CC/Lecture#14-PartIA 39 EE3170/CC/Lecture#14-PartIA 40

OC2 Interrupt Typical Application -- Generate Slow External Clock Toggle OC2 each $2000 ticks of TCNT. Pick maximum TCNT tick interval (8 μs). TCNT clock period set by bits PR1, PR0 PR1 PR0 D TCNT Prec TOF period 0 0 1 0.5 μs 32.8 ms 0 1 4 2.0 μs 131.1 ms 1 0 8 4.0 μs 262.1 ms 1 1 16 8.0 μs 524.3 ms EE3170/CC/Lecture#14-PartIA 41