1. Introduction Macronix MX25Lxxx45G Serial NOR flash support DTR (Double Transfer Rate) Reads in the x1, x2, and x4 I/O modes. DTR allows address and data to be transferred on both the rising and falling edge of the clock () effectively doubling the read throughput as compared to systems using a STR (Single Transfer Rate) bus. The MX25Lxxx45G Macronix 3V Quad I/O capable Serial flash with DTR product family will be available in densities ranging from 128Mb to 1Gb: 128Mb = MX25L12845G, 256Mb = MX25L25645G, 512Mb = MX25L51245G, 1Gb = MX66L1G45G This application note will review the MX25Lxxx45G Serial flash DTR Read commands. 2. Serial Flash DTR Operation Macronix MX25Lxxx45G Serial Flash memory support a serial addressing protocol where 1 byte of instruction operation code is followed by a 4-byte (32-bit) address (3-byte for 128Mb density). Macronix MX25Lxxx45G series serial flash can accept single I/O mode (x1 bus width) and dual I/O mode (x2 bus width) read commands when they are shipped. However, if the Macronix serial flash will be used in Quad I/O mode (x4 bus width), the non-volatile QE (Quad Enable) bit must be set to 1. The QE bit is Bit-6 of the Macronix serial flash Status Register. After the QE bit is set, all of the Fast Read (x1 and x2) commands are still supported along with the QSPI (x4) Fast Read commands. The Flash I/O pins SIO2 and SIO3 will tristate when not driving. The WP# and Reset# pin functions are now disabled. The 4-byte DTR command set is typically preferred (Table 2-1), but the legacy 3-byte command set (Table 2-2) can be used with 4 bytes of address as well, by first entering 4-Byte mode (B7h) before any 3-byte Read, and then supplying an extra byte of address, or using the Extended Address Register. The 3-byte command set should also be used for the 128Mb flash. Table 2-1: MX25Lxxx45G DTR Read Commands (4-Byte Address Command Set) Instruction Description Operation Number of Channels for: Mode Code Command Address - Data FASTDTRD Single I/O (x1) DTR Read 0Eh SPI 1-1 - 1 2DTRD4B Dual I/O (X2) DTR Read BEh DSPI 1-2 - 2 4DTRD4B Quad I/O (x4) DTR Read EEh QSPI 1-4 - 4 4DTRD4B Quad I/O (x4) DTR Read EEh QPI 4-4 - 4 Table 2-2: MX25Lxxx45G DTR Read Commands (3-Byte Address Command Set) Instruction Description Operation Number of Channels for: Mode Code Command Address - Data FASTDTRD Single I/O (x1) DTR Read 0Dh SPI 1-1 - 1 2DTRD4B Dual I/O (X2) DTR Read BDh DSPI 1-2 - 2 4DTRD4B Quad I/O (x4) DTR Read EDh QSPI 1-4 - 4 4DTRD4B Quad I/O (x4) DTR Read EDh QPI 4-4 - 4 P/N: AN-0318 1
Figure 2-1 shows how the Macronix serial flash communicates with the Host in DTR (Single I/O) mode. The flash synchronously receives the command, address, and data serially shifted in on one input pin SI (Serial In) followed by data being clocked out on SO (Serial Out). The FASTDTRD Read timing waveform is shown in Figure 2-2. Figure 2-1: Single I/O SPI Mode Single I/O Mode: 4 unidirectional signal lines. CPU MOSI MISO SI SO Serial NOR Flash Figure 2-2: FASTDTRD Read (1-1-1) Waveform Flash receives Commands on SI only in STR mode with 8 clocks. Flash receives 4-byte Address on SI only in DTR mode with 16 clocks. After Dummy cycles, the flash sends Data on SO only at the rate of 1byte every 4 clocks. The minimum number of Configurable Dummy Cycles shown in Figure 2-2 is provided in the device datasheet and is determined by the maximum FASTDTRD Read frequency. P/N: AN-0318 2
Figure 2-3 shows how the Macronix serial flash communicates with the Host in 4DTRD (Quad I/O) mode. The flash synchronously receives the command on one I/O pin SIO[0], the address on 4 I/Os SIO[3:0], and then the data is clocked out on the same 4 I/Os SIO[3:0]. The 4DTRD QSPI Read timing waveform is shown in Figure 2-4. Figure 2-3: Quad I/O (QSPI) Mode Quad Mode: 2 unidirectional and 4 bidirectional signal lines CPU SIO0 SIO1 SIO2 SIO0 SIO1 SIO2 Serial NOR Flash SIO3 SIO3 Figure 2-4: 4DTRD QSPI DTR Read Waveform [4 I/O Read = (1-4-4)] Flash receives Commands on SI only in STR mode in 8 clocks. Flash receives 4-byte Address on SIO[3:0] in DTR mode in 4 clocks. Flash sends each byte of Data on SIO[3:0] in DTR mode with each clock. P/N: AN-0318 3
The minimum number of Configurable Dummy Cycles shown in Figure 2-4 is provided in the device datasheet and is determined by the maximum 4DTRD Read frequency. The 8 data bits contained in the first cycle of the 6 dummy cycles shown in Figure 2-4 are used to enter or exit the Performance Enhance Mode. In this mode, only the start read address is required for the next read, not the read command, saving 8 clocks in QSPI mode (great for back-to-back reads at different addresses). To enter and stay in Performance Enhance Mode, toggle the dummy cycle bits in the first cycle, after the address cycles. To exit Performance Enhance Mode, do not toggle the Performance Enhance Mode bits (see datasheet for details). The 4DTRD QPI Read timing waveform is shown in Figure 2-5. Similar to the 4DTRD QSPI waveform of Figure 2-4, The flash synchronously receives the address on 4 I/Os SIO[3:0], and then the data is clocked out on the same 4 I/Os SIO[3:0]. In QPI mode however, the command is also sent on 4 channels. To accept QPI instructions, it is not necessary to set the QE bit in the Status Register. The command EQIO (35h) is issued to enter QPI mode and is sent as a x1 serial stream. But once the serial flash receives this command and enters QPI mode, the serial flash expects subsequent commands, addresses, and data to be sent on 4 lines. When QPI is enabled (QE state is a "don't care"), only 4-4-4 mode is supported. Figure 2-5: 4DRTD QPI DTR Read Waveform [4 I/O Read = (4-4-4)] Flash receives Commands on SIO[3:0] in STR mode in 2 clocks. Flash receives 4-byte Address on SIO[3:0] in DTR mode in 4 clocks. Flash sends each byte of Data on SIO[3:0] in DTR mode with each clock. P/N: AN-0318 4
In DTR mode, the data is valid for less than half a clock cycle, which can make it difficult for the host to sample valid data at high clock frequencies. For this reason, Macronix provides a fixed 8-bit (Preamble Bit) data pattern (00110100) in the 512Mb and 1Gb flash. The Preamble Bit data pattern assists the system memory controller to determine when the output data is valid and improve data capture reliability while the flash memory is running at higher frequencies. The controller can continuously adjust the incoming data sampling point, until the preamble bits are read correctly on each I/O, and internally adjust/delay the received preamble pattern to the center of the received data eye for greatest margin. The Preamble Bit data pattern can be enabled or disabled by setting bit-4 of the Configuration register (Preamble Bit Enable bit). Once the CR<4> is set, the Preamble Bit pattern is output by the flash during DTR FastRead dummy cycles (Figure 2-6). Figure 2-6: 4DTRD QSPI Read (1-4-4) with Preamble Bit Learning Pattern Performance Enhance bits (or Toggle Bits as shown in Figure 2-6) are still input in the first cycle after the address. P/N: AN-0318 5
3. Summary APPLICATION NOTE Macronix serial flash read speeds can nearly double when using DTR. Macronix offers the MX25Lxxx45G 3V, Serial Flash family with Multi-I/O interfaces and DTR, which is backward compatible to Single I/O STR Serial flash offered by Macronix. When performing DTR Reads, the Macronix 512Mb and 1Gb MX25xxx45G series serial flash have the ability to enable a Preamble Bit data learning pattern to assists the system memory controller in determining when the output data is valid and improve data capture reliability. 4. Reference Documents Table 4-1 shows the datasheet versions used in this application note. For the most current Macronix specification, please refer to the Macronix Website at http://www.macronix.com Table 4-1: Datasheet Version Datasheet Location Date Issued Versions MX25L12845G - Jul. 2014 Rev 0.00 MX25L25645G - May 2014 Rev 0.00 MX25L51245G Macronix Website Jul. 2014 Rev. 1.1 MX66L1G45G Macronix Website Dec. 2013 Rev 0.00 5. Revision History Revision Date Description 01 August 12, 2014 Initial release P/N: AN-0318 6
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