High-Performance Digital Radio Baseband Processor with Seamless Blending The Si469x dual DAB/DAB+ radio co-processor provides significant advances in size, power consumption, and performance to enable DAB/DAB+ Radio reception with DAB- DAB-FM seamless blending in automotive infotainment systems and car radios. It is designed to work with the high-performance automotive Si479x family of radio tuners. Applications OEM automotive infotainment systems Aftermarket car radio systems FM Input DAB I/Q Input0 DAB I/Q Input1 DICLK DIFS DIN ZIFI0 ZIFQ0 ZIFFS0 ZIFCLK0 ZIFI1 ZIFQ1 ZIFFS ZIFCLK11 Si4692 ASRC ASRC CLK Gen XTALI/RCLK XTALO DAB/DAB+ Decoder DAB/DAB+ Decoder Audio (FM) Power Supply VIO VD Audio Audio FLASH Interface NVSCLK NVSSB NVMOSI NVMISO FM-DAB-DAB Seamless Linking SMODE I2C / SPI Host Interface SCLK/SCL SSB/A1 MISO/A0 MOSI/SDA INTB RSTB SRAM DOUT DCLK DFS KEY FEATURES Dual DAB/DAB+ co-processor (Si4692) Single DAB/DAB+ co-processor (Si4690) Integrated DAB/DAB/FM (Si4692) and DAB/FM (Si4690) time and level alignment and seamless blending PAD/XPAD outputs available FIC decoder Ensemble info Service list Component info Service linking info Full support for data services Packet mode Packet mode with Data Groups Enhanced Packet mode MOT, TPEG packet outputs No external RAM required for channel decoding or seamless blending Flash memory interface for application program load Support for Si479xx Zero-IF DAB I/Q at 2.048 MS/s Support for audio from third tuner Integrated crystal oscillator Reference clock input SPI, I2C control interfaces LGA 72-pin, 10 x 10 x 1 mm Pb-free/RoHS compliant AEC-Q100 qualified silabs.com Building a more connected world. Preliminary Rev. 0.1 This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Pin Descriptions 1. Pin Descriptions CONN1 CONN0 VD VIO DOUT DFS DCLK MISO/A0 MOSI/SDA 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 1 54 SCLK/SCL 2 53 SSB/A1 3 52 RSTB 4 51 DIN INTB 5 50 DICLK 6 49 DIFS 7 48 8 47 9 46 ZIFI0 10 45 ZIFQ0 11 44 ZIFCLK0 12 43 ZIFFS0 13 42 14 41 XTALO 15 40 XTALI/RCLK 16 39 17 38 SMODE 18 37 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 NVSCLK NVSSB NVMOSI NVMISO ZIFFS1 ZIFCLK1 ZIFQ1 ZIFI1 Figure 1.1. Si4692 Pinout Diagram silabs.com Building a more connected world. Preliminary Rev. 0.1 2
Package Outline 2. Package Outline Figure 2.2. 10 x 10 mm 72-Pin LGA silabs.com Building a more connected world. Preliminary Rev. 0.1 3
Package Outline Table 2.1. Package Dimensions Dimension Min Nom Max A 1.00 1.08 1.20 b 0.15 0.25 0.35 D 10.0 BSC D2 7.20 7.30 7.40 D3 8.50 BSC D4 1.00 1.10 1.20 e E 0.50 BSC 10.0 BSC E2 7.50 7.60 7.70 E3 8.50 BSC E4 1.30 1.40 1.50 L 0.225 0.325 0.425 L1 0.05 0.10 0.15 L2 0.575 0.625 0.675 ed1 ed2 ed3 ee1 ee2 ee3 ee4 ee5 ee6 1.30 BSC 3.15 BSC 2.55 BSC 1.30 BSC 3.00 BSC 2.70 BSC aaa 0.10 bbb 0.10 ccc 0.10 ddd 0.10 eee 0.10 Note: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Solid State Outline MO-220. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. silabs.com Building a more connected world. Preliminary Rev. 0.1 4
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