Using the Xilinx CORE Generator in Foundation ISE 3.1i with ModelSim

Using the Xilinx CORE Generator in Foundation ISE 3.1i with ModelSim Installing Foundation ISE, CORE Generator, and ModelSim Foundation ISE This section explains how to install the Xilinx Foundation ISE and CORE Generator software tools from the Xilinx Foundation Series ISE 3.1i CD. The CORE Generator software is automatically installed with Foundation ISE in the 3.1i release. 1. Select Start Run. Type d:\setup.exe in the Open field of the Run window and click OK. (If your CD-ROM drive is not the "d" drive, substitute the appropriate drive designation.) 2. Follow the instructions on the screen to install the software. You will be asked to register the product from the Welcome screen during install. You can register via the web, email, or fax. In order to register the product, you need to provide the following information: Product ID Your product ID number is located on the back of your software CD pack. Your name Company Mailing address Phone number email address When you register, Xilinx gives you a Registration ID. You must have the registration ID in order to complete the installation. The installer first installs all of the Xilinx software and then invokes the installer for FPGA Express. Make sure that you install FPGA Express in the default directory indicated. Your FPGA Express synthesis FlexLM license file will be emailed to you. When install is complete, remove the CD. You may need to reboot your PC to allow the environment variables and path statement to take effect before you can run the design implementation tools. The Install program will inform you if you need to reboot. For detailed information on installing Foundation ISE refer to the Foundation ISE 3.1i Installation Guide and Release Notes which came with the CD. MXE Installing MXE Software: This CD contains the ModelSim Xilinx Edition (MXE) simulator from MTI. To install the MXE software, perform the following steps: 1. Insert the ModelSim Xilinx Edition CD. 2. Select Start Programs Foundation Series ISE 3.1i Partner Products Install ModelSim Xilinx Edition. When you install this software, you are prompted for licensing. Follow the instructions on the screen to license and install the product. 3. Remove the CD when installation is complete. PE, EE/SE Foundation ISE is compatible with any version of ModelSim. For PE, EE/SE installation and purchasing instructions see http://www.model.com Setting up CORE Generator simulation models The.V and the.vhd behavioral models for each CORE Generator module are not copied to your project directory. The CORE Generator System only writes out.veo and.vho HDL instantiation template files.

These instantiation template files contain pointers to the generic, parameterized HDL simulation models in the XilinxCoreLib libraries. We will first describe the setup for the CORE Generator Verilog simulation models. The CORE Generator Verilog simulation library is located at $XILINX/verilog/src/XilinxCoreLib. The pointers in these Verilog modules must be updated to match the users install or commented out for the simulation to work. To comment out the path: 1. Using the Windows Search/Find feature, browse to the $XILINX/verilog/src/XilinxCoreLib directory and find all files containing the following string: XilinxCoreLib. 2. Open the files one at a time and comment out the `include "XilinxCoreLib/<corename>.v" line. You can comment out this code line by inserting two forward slashes (//) at the beginning of the line. Once ModelSim has compiled the library, the `include statement is no longer be necessary. 3. Save the file and Exit. To update the paths: 1. Using the Windows Search/Find feature, browse to the $XILINX/verilog/src/XilinxCoreLib directory and find all files containing the following string: XilinxCoreLib. 2. Open the files one at a time and do a Change/Replace of XilinxCoreLib with D:/Xilinx/verilog/src/XilinxCoreLib, where D:/Xilinx is the install directory. 3. Save the file and Exit. NOTE: The paths must be updated for all newly installed models after an IP Update is installed. Compiling the Simulation Libraries After the Verilog Simulation Library paths have been updated the libraries are ready for compilation using the ModelSim simulator. The CORE Generator Library comes pre-compiled with the ModelSim Xilinx Edition Software. The compilation step is only required for PE or EE/SE versions of ModelSim. 1. Analyze_order verilog_analyze_order File: This file lists the CORE Generator Verilog behavioral models in the order in which it is suggested that they be compiled before performing a behavioral simulation in a compiled simulator. This file is located in $XILINX/verilog/src/XilinxCoreLib/verilog_analyze_order vhdl_analyze_order File: This file lists the CORE Generator VHDL behavioral models in the order in which they must be compiled for simulation. More than one compile order may be valid for the library. This file is located in $XILINX/vhdl/src/XilinxCoreLib/vhdl_analyze_order 2. Map and compile the XilinxCoreLib library in ModelSim. The VHDL and Verilog commands listed below are run at the ModelSim prompt: Verilog vlib xilinxcorelib_ver vmap xilinxcorelib_ver xilinxcorelib_ver vlog -work xilinxcorelib_ver <destination_directory>/xilinxcorelib/*.v NOTE: The verilog_analyze_order file does not need to be followed when compiling the Verilog models. In this case we have simply specified *.v to compile all of the XilinxCoreLib Verilog models. However, when compiling the models in this manner, you may encounter additional warnings, which can be ignored, about missing lower level modules. VHDL vlib xilinxcorelib vmap xilinxcorelib xilinxcorelib vcom -work xilinxcorelib <destination_directory>/xilinxcorelib/filename.vhd NOTE: The vlog and vcom commands must be run multiple times on the individual Verilog and VHDL models using the order information in the analyze_order files. For additional information, see solution record 8066: http://support.xilinx.com/techdocs/8066.htm

IP Updates IP Updates add addition core support to the CORE Generator. The IP Updates are available as downloadable files from the IP Center. The following web page provides the download as well as documentation for the new cores. http://support.xilinx.com/ipcenter/coregen/updates.htm#update Once the file has been downloaded to a temporary directory, unzip the file to the $XILINX directory. When the installation has completed the Compiling the Simulation Libraries must be completed again. For additional information, see solution record 9332: http://support.xilinx.com/techdocs/9332.htm (Check Answers Database and search on known issues for the specific release on the Xilinx Search page) Generating a CORE in Foundation ISE Foundation ISE provides full support of CORE Generator 3.1i. This section will discuss starting CORE Generator, selecting the desired core, creating the core, and adding of the core to the Foundation ISE current project. Starting CORE Generator The CORE Generator is opened from Foundation ISE using the Project -> New Source menu pick. The New Source dialog box will open allowing the user to select from the list of supported sources. Select Coregen IP and enter a File Name. Then click Next and Finish to open the CORE Generator. NOTE: The File Name is not used for Core creation yet, this is a limitation of the New Source dialog. The Core name must be specified in the CORE Generator GUI. CORE Generator GUI The main view of the Core Generator is the Core Generator Browser. Cores that fall into particular application categories are grouped into folders to assist you in locating the core appropriate to your needs. The left hand of the Core Generator Browser allows you to browse through these folders. To select a folder, click once on the folder name in the left panel. To expand a folder, double-click the folder icon to the left of the folder name. The folder expands to reveal more folders. To close a folder, double-click the open folder icon. Some folders have a + icon or a - icon to their left. You can open or close the folder with a single click on the icon. The cores in the selected folder are displayed in the right hand panel of the Core Browser. Cores are listed by name and also have type, version, family and vendor information displayed in columns. Some cores in the right panel of the main window appear to be grayed out. This means that these cores are not available for the currently selected Xilinx FPGA family. The family information is supplied to CORE Generator based upon the family selected for the current Foundation ISE project. The status panel at the bottom of the core browser window displays the results of actions and displays appropriate messages if any errors or warnings occur. A core can be selected by clicking the name of the core in the right panel. After a core has been selected the data sheet can be viewed by clicking on the Data Sheet button on the Core Browser toolbar. Customizing a Core Most cores have a customization GUI. To open a customization GUI, navigate to the module of your choice. From here, you can display the customization GUI for a core by proceeding with one of the following steps: Double-click the core in the right panel of the Core Browser, or Click on the Customize button on the Core Generator Browser toolbar, or Select the core in the left panel and select Core Customize, or Press the right mouse button over a core in the right panel of the main window. The customization GUI is only available for cores that support the currently selected Xilinx FPGA family. While the customization GUIs are unique for each core, there are some characteristics that are common to all modules. For more information, see chapter 3 of the CORE Generator User Guide: http://toolbox.xilinx.com/docsan/3_1i/data/common/cgn/chap03/cgn03002.htm

After the Core has been customized simply generate the Core and exit the CORE Generator. Foundation ISE Upon closing the CORE Generator, Foundation ISE adds the instantiation template to the Language Template. This allows for easy instantiation into the users source code. Figure 1 gives an example of the Language Template. Figure 1: Language Template CORE Generator Instantiation Template Foundation ISE also adds the CORE Generator XCO file to the project. Double clicking on the XCO file opens the CORE Generator Customization GUI for the specified core and displays the settings used to generate the core. This allows the user to make a simple change and easily regenerate the core. Instantiating the CORE VHDL & Verilog Instantiation of the core in the VHDL or Verilog can be done directly from the Language Template. There are two methods of copying the instantiation from the Language Template to the source file. One thing to note, several sections of the instantiation template are used for simulation. These sections will be described in the Simulation section. 1. For VHDL, cut the Component Declaration and Instantiation Template directly from the Language Template and paste it in the source file. For Verilog, in the Language Template, cut the Instantiation section ONLY, from Instantiation Template and paste it directly in the source file. 2. In the Templates Window, click and drag the core directly into the source file. Releasing the mouse button causes the data to be pasted in the source. Then delete the unnecessary sections of the template. For example, in figure 1 select the core ten2 and drag it into the source. NOTE: If the core instantiation template is not added to the Language Template, this information can be found in the VHO or VEO file in the project directory. Schematic : Generating a symbol After the CORE Generator is closed a schematic symbol is automatically created and accessible in the schematic editor.

If the symbol has not been created, the follow steps outline how to create a symbol. 1. In Project Navigator, select File -> Open... and browse for the <core>.vho or <core>.veo file. 2. Select File -> Save As... and save the <core>.veo file as <core>.v or the <core>.vho file as <core>.vhd. 3. Close the HDL Editor. 4. Select Project -> Add Source and browse for the <core>.vhd or <core>.v file. This will add the file to the project. 5. In the Source Window select <core>.vhd or <core>.v, then double click on the Create Schematic Symbol process under the Design Entry Utilities. Behavioral Simulation of the Core in ModelSim VHDL : Configuration Statements What is the purpose of a configuration statement: 1. Define which entity and architecture pair is used to bind a component. 2. Used to map the COREGEN component and parameters to the behavioral simulation model. 3. Used to map lower-level configurations to current entity/architecture pair. Two examples will be used to explain how configuration statements are used. The first example will illustrate the core being instantiated in the top level source. The second example will illustrate the core being instantiated in a lower level module. Example 1: tenths is the CORE Generator component Test Bench Entity: testbench Architecture: testbench_arch Component Declaration: stopwatch Top Level Source Entity: stopwatch Architecture: behavioral Component Declaration: tenths Here are the configuration statements required for each file. Configuration Statement placed at the end of the Test Bench: configuration stopwatch_cfg of testbench is for testbench_arch for all: stopwatch use configuration work.cfg_tenths; end stopwatch_cfg; Configuration Statement placed at the end of the Lower Level Source, the information in the generic map is obtained from the Instantiation Template generated by the CORE Generator: -- synopsys translate_off Library XilinxCoreLib; configuration cfg_tenths of stopwatch is for behavioral for all : tenths use entity XilinxCoreLib.C_COUNTER_BINARY_V1_0(behavioral) generic map( c_sinit_val => "0",

end cfg_tenths; c_has_ce => 1, c_has_aclr => 0, c_count_by => "0001", c_restrict_count => 1, c_enable_rlocs => 1); -- synopsys translate_on Example 2: state_mach is the CORE Generator component Test Bench Entity: testbench Architecture: testbench_arch Component Declaration: wrapper Top Level Source Entity: wrapper Architecture: behavioral Component Declaration: state_bram Lower Level Source Entity: state_bram Architecture: behavioral Component Declaration: state_mach Here are the configuration statements required for each file. Configuration Statement placed at the end of the Test Bench: configuration top_cfg of testbench is for testbench_arch for all : wrapper use entity work.wrapper(behavioral); for behavioral for all: state_bram use configuration work.cfg_my_design; end top_cfg; NOTE: For additional layers of hierarchy this configuration statement is altered. The italic lines are replicated for each additional layer of hierarchy. Simply change the entity, architecture, and component names accordingly. No additional configuration statements are required in the hierarchy. Configuration statements are only required in the test bench and the source where the core is instantiated. No Configuration Statement placed at the end of the Top Level Source.

Configuration Statement placed at the end of the Lower Level Source, the information in the generic map is obtained from the Instantiation Template generated by the CORE Generator: --synopsys translate_off Library XilinxCoreLib; configuration cfg_my_design of state_bram is for behavioral for all : state_mach use entity XilinxCoreLib.C_MEM_SP_BLOCK_V1_0(behavioral) generic map( c_has_rst => 1, c_address_width => 8, c_read_mif => 1, c_depth => 256, c_pipe_stages => 0, c_mem_init_radix => 2, c_default_data => "0", c_mem_init_file => "state_bram.mif", c_we_polarity => 1, c_generate_mif => 1); end cfg_my_design; -- synopsys translate_on Remember to simulate the top-level configuration, not the top-level entity!!! Verilog The <core>.xco file contains all of the information necessary to perform a behavioral simulation. The <core>.xco file is added automatically to the Foundation ISE project. All that is required is instantiatation of the core in the source file. Schematic: See solution 8883 for more information http://support.xilinx.com/techdocs/8883.htm By default the schematic is written out as a VHDL model. Therefore the VHDL methodology explained above must be used. In a schematic design containing a CORE Generator macro, a hierarchical configuration statement must be added to the testbench which provides the stimulus for the schematic. Here is a template of the configuration that must be added to the bottom of the testbench: library XilinxCoreLib; configuration <cfg_name> OF <testbench_entity> IS for <testbench_arch> for all : <instantiated_comp> use entity work.<entity>(<architecture>); for <architecture> for all : <core_name> use entity XilinxCoreLib.C_DECODE_BINARY_V1_0(behavioral) generic map( c_has_rst => 1, c_address_width => 8, c_read_mif => 1, c_pipe_stages => 0, c_generate_mif => 1);

end TOP_cfg; If a Verilog macro symbol has been added to the schematic, then a Verilog netlist is written to represent the schematic design. In this case the Verilog methodology explained above is used. Setting up the ModelSim Simulator in Foundation ISE By selecting the Test Bench in the Source Window, the Process Window displays the ModelSim Simulator process. By right clicking on the Simulate Functional VHDL (or Verilog) Model and selecting Properties, the user can control the simulation. For VHDL, select the VHDL Functional Simulation Options tab and change the Design Unit from testbench to the top level configuration name. If this is not done the core will not simulate. No changes are required for Verilog simulation.