CERN European Organization for Nuclear Research Beams Department Radio Frequency RF Feedbacks and Beam Control TEST REPORT POWER SUPPLY AND THERMAL V2 By: Petri Leinonen BE-RF-FB Date: 27.06.2012
TABLE OF CONTENTS 1. INTRODUCTION... 3 2. TEST SETUP... 4 2.1. Device under test (DUT)... 5 2.2. Measurement setup in the lab... 6 2.3. Communication setup... 6 3. POWER SUPPLY TESTS... 7 3.1. Experiment 1: power supply voltages... 7 3.1.1. Objective... 7 3.1.2. Test setup... 7 3.1.3. Test results... 7 3.1.4. Analysis of the results... 7 3.2. Experiment 2: Power rail noise... 8 3.2.1. Objective... 8 3.2.2. Test setup... 8 3.2.3. Test results... 8 3.2.4. Analysis of the results... 8 4. THERMAL TESTS... 9 4.1. Experiment 3: Thermal measurement... 9 4.1.1. Objective... 9 4.1.2. Test setup... 9 4.1.3. Test results... 9 4.1.4. Analysis of the results... 9 5. CONCLUSION... 10 6. APPENDIX... 11
3 1. INTRODUCTION This document describes the results of the power supply and thermal tests of the version 2 of the FMC-DAC-4-CH-16bit-250MSPS mezzanine card; EDA-02069 1. The mezzanine card provides four independent channels, each generating a sample and hold analogue voltage proportional to its 16 bit input digital word fed through the connector linking it to the carrier board. The on-board Digital-to-Analogue Converters (DAC) generate a current which full scale value can be programmed via a Serial Peripheral Interface (SPI) between values ranging from 8.64mA to 31.7mA. After this stage an I-to-V-conversion is performed. The produced voltage is amplified and fed to a dual-position attenuator (typically 0dB and -18 db). The aim of this latter circuit is to extend the dynamic range of the output from 16 to 19 bits. When the digital signal has low amplitude, it is digitally amplified by 18 db and simultaneously attenuated by the same amount in the analogue domain. This result in more bits involved for the same output amplitude and thus more resolution. The signal is then further amplified and filtered to remove the sampling aliases. The sampling rate is from DC to 250 Ms/s. The mezzanine card is designed to be plugged on a carrier card which has a High Pin Count (HPC) FMC 400-pin connector and includes an FPGA where the mezzanine card data is being processed. This unit is foreseen to be used in a so-called beam control system, typically to generate a radio frequency (RF) modulated signal that feeds, after amplification, the accelerating cavities. In this latter context, the firmware block controlling this DAC board is called SDDS (Slave Direct Digital Synthesizer). Within the beam control system, the sampling clock is a high harmonic of the particles revolution frequency, provided by another FMC mezzanine board called Master Direct Digital Synthesizer or MDDS. This sampling rate value was chosen in order to ease the creation of the accelerating voltage which is also a harmonic of the revolution. 1 CERN Identification number for documents in EDMS(Equipment Data Management Service) EDA-02069: https://edms.cern.ch/nav/p:eda-02069:v0
4 2. TEST SETUP The test setup consists of three boards: a DAC mezzanine card, a transition board and a ML605 evaluation board. The ML605 provides the data processing (in a Virtex 6 FPGA) and the power via the transition board to the mezzanine card. In addition, the ML605 evaluation kit provides various interfaces and connectors to be used with the external world. The transition board provides a clock signal for the DAC board and it is used to change some voltage levels in order to be compliant with the 2.5V FPGA IOs.
5 2.1. Device under test (DUT) Figure 1. The mezzanine card hardware V2: a) the bottom side b) and the top side.
6 2.2. Measurement setup in the lab Figure 2. DUT, Transition board and ML605 evaluation kit test setup (from top to bottom). 2.3. Communication setup The evaluation kit provides a test platform for the firmware and the daughter card hardware. At first, the communication channel was established between the daughter card and the ML605 board. The programming of the FPGA is done with the JTAG connection. After initializing the JTAG chain under Xilinx ISE, the FPGA was loaded with the firmware code. The communication itself happens through an UART-port. The data is sent from the computer and received by the evaluation kit, via a USB-cable, in serial format. The evolution kit has an USB-to-UART bridge on board which allows the data to be transferred via the USB port. The baud rate of the connection is 9600 bps. Python was used for programming the computer user interface. Python is a high-level object orientated language and it was selected to be the test interface with the evaluation kit. Python provides an open-source environment and easily readable code structure. In addition, it is a scripting language which makes it a powerful tool for hardware testing.
7 3. POWER SUPPLY TESTS 3.1. Experiment 1: power supply voltages 3.1.1. Objective The aim is to verify the power supply voltages and to find out whether they are within the ±5% tolerance as specified in the FMC standard. 3.1.2. Test setup The power supply was measured with an oscilloscope (LeCroy waverunner 64Xi, 600 MHz, 10Gs/s) and with a multimeter (Fluke 87). The transition board works as an adapter and routes the power pins (+12V, +3.3V, +3.3VAUX and the VADJ of +3.3V) from the ML605 evaluation kit to the DAC mezzanine card. The schematic of the DAC mezzanine card (EDA-02069) and the transition board (EDA-02227) can be found from the CERN EDMS web site. 3.1.3. Test results Table 1 shows the results of the DAC mezzanine card power supply with the peak-to-peak noise amplitudes. The Appendix 1 shows the power distribution network of the mezzanine card. The +0.4V in Table 1 is the common mode voltage which is needed for the differential clock input of the D/A-converter. Table 1: Measured power supply values with their tolerances Power supply Measured value 5% tolerance +12V +12.07V, ok +[12.600 11.400]V +5V Digital, +5V Analog, +5.058, ok +[5.250 4.750]V -5V -4.977V, ok -[5.250 4.750]V +3.3V +3.284V, ok +[3.465 3.135]V +3.3V filtered_analog +3.284V, ok +[3.465 3.135]V +3.3VAUX +3.296V, ok +[3.465 3.135]V +1.8V +1.799V, ok +[1.890 1.710]V +0.4V +0.400V, ok +[0.420 0.380]V 3.1.4. Analysis of the results The version 1 hardware had a voltage drop of 221mV in the -5V power rail. The hardware version 2 was designed with another switching regulator (MAX1846EUB) and that fixed the problem and provided expected results from the hardware.
8 3.2. Experiment 2: Power rail noise 3.2.1. Objective The aim is to measure the power rail noise level. See 3.1.2. 3.2.2. Test setup 3.2.3. Test results The test results can be found from the CERN Open Hardware Repository web page http://www.ohwr.org/projects/fmc-dac-250m16b4cha/documents under the Power supply and thermal tests version 2. Table 2 lists and summarizes all the noise levels from the measurements. Table 2: Power supply voltages with their peak-to-peak noise levels. Power supply Peak-to-peak noise +12V 283mV +5V Digital, +5V Analog, 314mV Digital, 50mV Analog -5V 190mV +3.3V 141mV +3.3V filtered_analog 95mV +3.3VAUX 64mV +1.8V 76mV +0.4V 50mV 3.2.4. Analysis of the results The power and ground planes suffer from a switching noise generated by the MAX1846 and LT3503. The MAX1846 generates noise which can be seen at the 300kHz and 600kHz. The LT3503 generates a switching noise at 1.1MHz. Also the evaluation kit ML605 has DC-DC converter modules, PTD08A010W and PTD08A020W, which work with 500 khz frequency but this is not visible in the test results as it was in the version 1 measurement results. 1.1MHz switching noise can be filtered with relatively small components but the noise in the khz range would require big components on the board, and that becomes a problem as the mezzanine card is very dense. Further tests will reveal if the noise levels affect dramatically to the functionality of the mezzanine card.
9 4. THERMAL TESTS 4.1. Experiment 3: Thermal measurement 4.1.1. Objective The aim of the thermal measurement is to measure the overall temperature on the board. 4.1.2. Test setup Thermal tests were carried out by using a Fluke Ti20 Thermal imager. The instrument measures the temperature on the board in Celsius and shows the results real time with an infra-red image. 4.1.3. Test results All the prototypes have an overall temperature of 30 C throughout the board. Figure 3 shows eight IC chips which heat up slightly more than the average temperature on the board. The temperature of those 8 components is between 39 and 45 C. Figure 3. Thermal image of the DAC mezzanine card. 4.1.4. Analysis of the results During the measurements the pointer of the imager was placed on different spots on the board and the measurements showed that the average temperature is 30 C as expected. The use of a fan reduced the temperature by 2 C. The hardware version 1 had a problem with an overheating regulator. For the version 2 this regulator was changed and the results are now as expected.
10 5. CONCLUSION The power supply and thermal test results of the DAC mezzanine card EDA-02069 version 2 show that most of the voltages are within tolerance of ±5%. +12V, +5V, -5V, +3.3V, +3.3V filtered_analog, +3.3VAUX, +1.8V and +0.4V were measured and all of them were sufficient to supply the power on the mezzanine card. The power supply noise levels were also measured and some of them were still too high compared to the version 1 hardware. Better filtering on board can be applied to reduce the switching noise of the voltage regulators. Version 1 hardware had a heating problem concerning one of the voltage regulators. The measurements show that the version 2 hardware does not have the same problem and the mezzanine card works as expected.
11 6. APPENDIX Appendix 1. Simplified model of the power distribution network of the version 2 of the DAC mezzanine card