Intra Optical Data Center Interconnection Session 2: Debating Intra-DC solutions and Photonic Integration approaches

Intra Optical Data Center Interconnection Session 2: Debating Intra-DC solutions and Photonic Integration approaches Co-Organizer/Presider/Session Chair: Dr. Ioannis Tomkos Networks and Optical Communications group NOC

Session 2 Speakers & Panelists - I Chris Pfistner, Vice President, Datacom Product Line Management, Lumentum Chris joined the company in October 2015, bringing over 20 years of experience in Marketing, Sales, and Product Line Management in the global fiber optic module and systems market. Prior to Lumentum, Chris managed Finisar s product management team for optical transceivers. Before Finisar he built the transceiver business at NeoPhotonics. He was also a co-founder of Terawave, and held marketing and product management positions at AFC and Pirelli. During his career Chris has developed and launched several disruptive products based on innovative technologies and turned them into successful businesses. Chris holds Ph.D. and MS. degrees in Applied Physics from the University of Berne, in Switzerland. Brad Booth, Principal Engineer, Microsoft Brad Booth is a long-time leader in Ethernet technology development and standardization, currently heading up the 25/50G Ethernet Consortium and the Consortium for On-Board Optics (COBO). At Microsoft, he leads the development of hyperscale interconnect strategy for Microsoft s cloud datacenters. He is also the founder and past Chairman of the Ethernet Alliance. Brad was previously a Distinguished Engineer in the Office of the CTO at Dell Networking. He has also held senior strategist and engineering positions at Applied Micro, Intel, and PMC-Sierra. He was listed as one of the 50 most powerful people in networking by Network World magazine. 2

Session 2 Speakers & Panelists - II James Regan, CEO, Effect Photonics James has over 30 years of experience in the photonic component business, in product development, marketing, sales and general management in building successful businesses within large companies (Nortel, JDSU) and start-ups (Agility Communications). Silvio Abrate, Head of Applied Photonics, ISMB Silvio Abrate is head of the Applied Photonics research group at ISMB and manager of the PhotonLab research facility, held in cooperation with Politecnico di Torino. Mauro Macchi, Director SP EMEAR, Cisco Mauro s 20+ years career in telecom industry includes Engineering and Product Management roles in Pirelli, Cisco and Juniper Networks. He is currently leading EMEAR Business Overlay team for IP, Optical and Data Center technologies. 3

Why Photonic Integration? Why integration? Look back at the electronics! Pictures taken at: Whirlwind, MIT, 1952 EAI 580 patch panel, Electronic Associates, 1968 Today s state of computing is based on: Integration and scaling of the logic functions (CMOS electronics) Integration and scaling of the interconnects (PCB technology & assembly) 4 For optical interconnects, this resembles: Electro-optical integration and scaling of transceiver technology Integration of optical connectivity and signal distribution

What is possible with InP today? Fully integrated monolithic 8-channel OS- and AO-OFDM Tx InP PIC fabricated! EU project ASTRON Tx PIC presentation at ECOC 2016! OS-OFDM Tx PIC Source: EU project ASTRON (partner HHI) AO-OFDM Tx PIC ASTRON designed, fabricated and characterized fully integrated monolithic 8-channel OS-/AO- OFDM InP transmitter PIC, for the first time, integrating 8 IQ modulators and the other passive Tx building blocks (8- port AWG, 1x8 splitter/combiner) on a single PIC 5

Comparison of InP and SiPh technologies The development of the SiPh technology has helped to drive large-scale manufacturing of PICs at low costs, since they can leverage highly developed fabrication processes from the microelectronics industry. However, some analysts claim that InP platforms can, depending on yields, have production costs equal to or lower than SiPh, for the production volumes expected for telecom and DC applications. The table summarizes the pros and cons of InP and silicon photonics for PIC manufacturing Silicon photonics also has also the added advantage compared to InP that it can be integrated with electronic Ics, using 2.5D and 3D packaging, thus saving cost, footprint, and power. 6

Factors affecting PIC costs The PIC market is growing at a phenomenal rate as it provides significant improvements in system size, power consumption, reliability and cost. Many factors can affect the projected costs of a new technology, among which are: the scale of production (e.g. annual production volume), the manufacturing location (e.g. the difference between producing in the USA and East Asia), the cost and size of wafers, the maturity of the manufacturing process, and most importantly the production yields achievable for each technology 7

Relative cost per PIC The simple relation between achievable number of PICs per wafer and PIC size: Current InP SotA It is obvious that the decreasing number of available PICs per wafer, with increasing PIC size, is accompanied by increasing costs. The relative cost with decreasing number of PICs per wafer, for different substrate sizes and while assuming 100%(!) on-wafer yield is also shown. The cost calculation refers to a single MZ modulator fabricated on a 3-inch InP wafer as a reference (i.e. on-wafer cost of a single MZM = 1). This cost will be reduced by a factor of 2 if a 4-inch InP substrate is used instead of a 3-inch one, and even more with larger substrate sizes. 8 SiP can support larger wafers compared to InP and therefore, just for that, can result in lower cost PICs Source: EU project ASTRON (partner HHI)

Evolution of chip complexity for InPand SiPh- based ICs In the figure we can observe, the evolution of chip complexity for InPbased IC (blue) and SiPh-based IC without laser (red) and with heterogeneously integrated lasers (green) The problem of laser integration on silicon stems from the fact that silicon has an indirect bandgap and hence is a very inefficient light emitter. A possible energy-efficient and costeffective solution is wafer bonding of III V materials that can be wafer bonded to the silicon photonic chip to co-fabricate lasers that are lithographically aligned to the silicon waveguide circuit. 9 Source: M. J. R. Heck et al. Hybrid silicon photonic integrated circuit technology, IEEE J. Sel. Topics in Quantum Electronics, 2013

Integration approaches Photonic integration strategies can be divided into three main categories, each of them having its own pros and cons. In hybrid integration, multiple single-function devices are assembled into a single package, sometimes with associated ICs, and inter-connected to each other by electronic and/or optical couplings internal to the package. Several problems may arise from the use of this integration technology: alignment tolerances of 1-2microns are sometimes necessary; different materials for different components may have different optical, mechanical and thermal characteristics, etc. In semi-hybrid integration, specialized regions are grown in appropriate materials over a common substrate (normally silicon). Finally, in monolithic integration, devices are built into a common substrate, providing significant packaging consolidation, testing simplification, reduction in fibre couplings, improved reliability and maximum possible reduction in space and power consumption per device. In hybrid integration, the process steps whose yields have the biggest impact on cost are mainly the backend assembly steps, whereas in monolithic integration it is the frontend processes that have a greater impact. In principle significant savings can be expected when moving from hybrid integration to monolithic integration, provided that the process yield can be maintained high. 10

Integration Roadmap for SiP Cost-advantages through further integration Cost of optics determines the application scope Silicon photonics versatile and cost-efficient Si: indirect bandgap additional material for laser sources required Today: external laser source must be coupled expensive and high losses Already demonstrated: hybrid III-V on silicon integration (on-chip) DIMENSION breakthrough: processing of III-V devices at silicon wafer level Hybrid State-of-the-art Source: EU project DIMENSION (partner IBM) Semi-Hybrid demonstrated Monolithic 11 III-V on silicon integration

Directly Modulated Lasers on Silicon www.dimension-h2020.eu

DIMENSION approach Combining BiCMOS electronics, photonics and III-V on a new technology platform for monolithic electro-optical integration Integrated devices, with CMOS, photonic and III-V functionality at the cost of silicon volume fabrication Source: EU project DIMENSION (partner IBM) Si CMOS wafer at front-end level including silicon photonics Concept IP protected Bonding a III-V photonic membrane onto the first dielectric oxide (ILD1) 13 Metal interconnection of the III-V with the CMOS underneath Structuring of the III-V active photonics

Concept and Main Objectives Technology platform for monolithic integration of BiCMOS electronics with Si- and III-V photonics: Bonding or growth of ultra-thin (<500 nm) III-V quantum well stack on the FEOL (Bi)CMOS Cost-effective embedding of high-quality III-V structures in (Bi)CMOS BEOL Efficient optical coupling between silicon and III-V layer based on adiabatic mode conversion with high modal overlap for low power consumption and high-speed modulation Laser feedback and passive optical structures in silicon layer DIMENSION implementation of III-V materials in between the front-end-of-line and the back-end-of-line of a BiCMOS process Source: EU project DIMENSION (partner IBM) 14

Issues to be discussed/debated 15 Material system: InP vs. SiP vs.??? Integration approaches: monolithic vs. hybrid? Packaging approaches? Wavelength of operation: 850nm vs. 1310nm vs. 1550nm? Laser type: VCSELs vs. DFBs vs.??? Direct vs. external modulation? The road to 400G and then to 800G/1600G? Modulation formats: PAM vs. DMT vs. QAM? Direct vs. coherent detection? Extend of use of DSP? Optical switching in the DC? Others???

Session 2 Speakers & Panelists - I Chris Pfistner, Vice President, Datacom Product Line Management, Lumentum Chris joined the company in October 2015, bringing over 20 years of experience in Marketing, Sales, and Product Line Management in the global fiber optic module and systems market. Prior to Lumentum, Chris managed Finisar s product management team for optical transceivers. Before Finisar he built the transceiver business at NeoPhotonics. He was also a co-founder of Terawave, and held marketing and product management positions at AFC and Pirelli. During his career Chris has developed and launched several disruptive products based on innovative technologies and turned them into successful businesses. Chris holds Ph.D. and MS. degrees in Applied Physics from the University of Berne, in Switzerland. Brad Booth, Principal Engineer, Microsoft 16 Brad Booth is a long-time leader in Ethernet technology development and standardization, currently heading up the 25/50G Ethernet Consortium and the Consortium for On-Board Optics (COBO). At Microsoft, he leads the development of hyperscale interconnect strategy for Microsoft s cloud datacenters. He is also the founder and past Chairman of the Ethernet Alliance. Brad was previously a Distinguished Engineer in the Office of the CTO at Dell Networking. He has also held senior strategist and engineering positions at Applied Micro, Intel, and PMC-Sierra. The holder of 14 patents related to networking technologies, he has received awards from the IEEE Standards Association for work on Ethernet standards and awards for his contributions to Gigabit Ethernet, 10 Gigabit Ethernet, Backplane Ethernet and Ethernet in the First Mile. He was listed as one of the 50 most powerful people in networking by Network World magazine.