Hyunmin Yoon (fulcanelli86@gmail.com)
2 Interrupt vs. Polling INTERRUPT 2
3 Polling (Programmed I/O) Processor has direct control over I/O Processor waits for I/O module to complete operation Processor determines state of device Command-ready Busy Error Busy-wait cycle to wait for I/O 3
4 Interrupt (Interrupt-driven I/O) 1. Processor issues commands for I/O operations 2. Processor does other work while I/O devices do the operations 3. I/O devices send hardware interrupt signal to processor when they complete the operations 4. Processor stops the work, and then starts ISR (interrupt service routine) 5. Processor redo the work that is stopped by interrupt 4
5 Interrupt USR IRQ interrupt stop current work ISR return to previous work 5
6 Interrupt Service Routine ARM PROCESSOR FUNDAMENTALS #3 6
7 Registers Register size 32 bits 18 Active registers 16 data registers (r0 to r15) 2 processor status registers CPSR = current psr SPSR = saved psr 20 Banked registers ARM System Developer s Guide 7
8 Processor Status Register ARM System Developer s Guide 8
9 Mode Switch (1) Mode switch by Hardware when the core responds to an exception or interrupt Software that writes directly to the mode bits of cpsr Except USR mode Banked register All processor modes have a set of associated banked registers Except SYS mode A banked register maps one-to-one onto a USR mode register 9
10 Mode Switch (2) Example : When processor changes from USR mode to IRQ mode cpsr of previous mode (USR) is automatically saved into spsr of the next mode (IRQ) Return address is saved into r14_irq Processor read r13 and r14 of the current mode when it accesses them PRE : r0 = 0x00, r13 = 0x10, r13_irq = 0x20, cpsr = IRQ mode mov r0, r13 POST : r0 = 0x20, r13 = 0x10, r13_irq = 0x20, cpsr = IRQ mode 10
11 Vector Table When an exception or interrupt occurs Suspend normal execution Set the pc to a specific memory address ARM System Developer s Guide Start address of vector table can be changed (rose/hal/kernel/entry-armv.s) 11
12 ISR (timer) (rose/hal/kernel/entry-armv.s) (rose/hal/irq/gic.c) interrupt from device (rose/hal/io/timer.c) (rose/hal/kernel/entry-armv.s) 12
13 Write codes for the return from ISR to user application HOMEWORK #1 13
14 Homework #1 Complete vector_irq and ret_to_usr rose/hal/kernel/entry-armv.s Do not use branch instructions 14
15 Purpose USR IRQ Consider that processor runs counting program as below interrupt stop current work ISR void main(void) { unsigned int cnt = 0; while(1) cnt++; } return to previous work And, timer interrupt request is generated during the program execution Processor register has cnt value But, that register is using on ISR also -> cnt value will be corrupted OS has to restore previous program execution states including cnt value before the return from ISR 15
16 Process Control Block (rose/kernel/sched.c) point at PCB of current program task_struct (rose/hal/kernel/entry-armv.s) task_struct PCB List task_struct (rose/include/rose/sched.h) Memory 16
17 H1-A Save context 1. Save r0-r12 of USR mode onto reg[r0]-reg[r12] 2. Save cpsr of USR mode onto reg[cpsr] 3. Save return address (from IRQ to USR) onto reg[ret] r0~r12 of USR address lr+80 lr+76 lr+72 lr+68 lr+64 value class state pid alloc reg[ret] lr+60 lr+56 reg[cpsr] reg[lr] task_struct lr+52 reg[sp] address value lr+48 reg[12].. cpsr of USR sp Return Address lr lr+8 lr+4 reg[r2] reg[r1] reg[r0] MEMORY MEMORY 17
18 H1-B Restore context 1. Make stack area and fill it for RFE instruction by using reg[cpsr] and reg[ret] 2. Restore r0-r12 of USR mode by using reg[r0]-reg[r12] address sp cpsr_usr Return Address value r0~r12 of USR cpsr of USR address lr+80 lr+76 lr+72 lr+68 lr+64 lr+60 lr lr+56 lr+52 lr+48 lr+8 lr+4 value class state pid alloc reg[ret] reg[cpsr] reg[lr] reg[sp] reg[12].. reg[r2] reg[r1] reg[r0] task_struct MEMORY MEMORY 18
19 Result (1) Now, we can use shell program 19
20 Result (2) Do Not Use This Command! It will work after Homework #2 20