introduction to interrupts

introduction to interrupts Geoffrey Brown Chris Haynes Bryce Himebaugh C335 Fall 2013

Overview Why interrupts? Basic interrupt processing Sources of interrupts Handling interrupts Issues with interrupt handlers 2

Polling Continually query devices for work. Consider putchar -- if we have to wait for the UART, then every character will consume (at 9600 baud) roughly 1ms -- this is wasted time Polling makes it challenging to meet real-time constraints -- consider feeding an audio signal to an external amplifier. Every sample must be provided at exactly the right interval. 3

Interrupts! Interrupts provide a general architecture for satisfying real-time software requirements. Rather than repeatedly asking devices if they need anything (polling them), let them interrupt the processor. 4

the big idea For each type of event that needs real-time handling, define a subroutinelike handler that is called when (or not long after) the hardware is informed the service of the need and returns when done. Handlers are sometimes known as callbacks and are also used in related situations such as handling GUI events. Handlers are said to run in the foreground, while other code runs in the background. Before every background instruction is executed, check if any event needs to be handled, and if so synchronize an interrupt by calling the associated handler. When the handler returns, continue with the instruction that was about to be executed. What must be saved with each handler call and restored when the handler returns? 5

Interrupt Service Background program code Interrupt handler some inst next inst some sort of ReTurn from Interrupt instruction RETI 6

Fetch-execute cycle with interrupts while(1) { if (I && Enabled(I)) } {// Synchronize interrupt I push pc; push sr; Disable(I); pc = Handler(I); } else { inst = Mem[pc]; pc += 4; eval(inst); } Processor External I Device Three processor specific functions Enabled(I) Disable(I) Handler(I) 7

Why SR Must be Saved Interrupted Program Interrupt Handler adds r2,... adc r3,... adds r5 RETI Many instructions effect SR Interrupt bit must be cleared to prevent handler being interrupted before it starts 8

general Interrupt state diagram Reset Disabled Enable Disable Disable Enabled IRQ Pending Synch Handling RETI 9

Key PoinTs If interrupts are enabled, they can occur at any point in the execution of a program. Interrupts must be disabled when when the handler is called (at least those from the same source) and re-enabled when the handler returns. Interrupt handlers are similar to procedures with some important caveats. They must save everything: not just the program counter, but also all other registers they use, including status bits. Other caveats discussed soon. 10

Preserving Registers Interrupted Program Interrupt Handler adds r2,... addc r3,... push r2 add r2,... pop r2 RETI 11

Memory Layout Interrupt Stack User Stack Heap Separating user and interrupt stacks makes it easier to guarantee interrupts will have the stack space they need. Code Vector Table 12

Sources of Interrupts External device interrupts, such as timer UART (serial interface) button Processor exceptions, such as memory faults Software interrupts (special program instructions) Interrupts of all kinds are more generally called exceptions. 13

cortex processor modes Depending on their source, exceptions may have very different requirements for latency: response time efficiency: some may be very frequent, others rare Exceptions require privileged assess to memory and other processor resources that is best denied user code. Hence Cortex processors have two modes with differing priority (latency), privilege and other characteristics. each mode can have its own stack space 14

Modes 2.1.1 Processor mode and privilege levels for software execution The processor modes are: Thread mode Handler mode Used to execute application software. The processor enters Thread mode when it comes out of reset. Used to handle exceptions. The processor returns to Thread mode when it has finished exception processing. The privilege levels for software execution are: Unprivileged The software: Has limited access to the MSR and MRS instructions, and cannot use the CPS instruction Cannot access the system timer, NVIC, or system control block Might have restricted access to memory or peripherals. Unprivileged software executes at the unprivileged level. Privileged options The software can use all the instructions and has access to all resources. Privileged software executes at the privileged level. Processor mode Used to execute Privilege level for software execution Stack used Thread Applications Privileged or unprivileged (1) Main stack or process stack (1) Handler Exception handlers Always privileged Main stack 1. See CONTROL register on page 22. 15

Cortex Registers Figure 2. Processor core registers R0 R1 R2 Low registers R3 R4 R5 R6 General-purpose registers R7 R8 R9 High registers R10 R11 R12 Stack Pointer SP (R13) PSP MSP Banked version of SP Link Register LR (R14) Program Counter PC (R15) PSR PRIMASK Program status register FAULTMASK Exception mask registers Special registers BASEPRI CONTROL CONTROL register ai15996 16

Privilege and Stacks The processor supports two separate stacks: Process stack Main stack You can configure Thread mode to use the process stack. Thread mode uses the main stack out of reset. SP_process is the Stack Pointer (SP) register for the process stack. Handler mode uses the main stack. SP_main is the SP register for the main stack. Only one stack, the process stack or the main stack, is visible at any time. After pushing the eight registers, the ISR uses the main stack, and all subsequent interrupt pre-emptions use the main stack. The stack that saves context is as follows: Thread mode uses either the main stack or the process stack, depending on the value of the CONTROL bit [1] that Move to Status Register (MSR) or Move to Register from Status (MRS) can access. Appropriate EXC_RETURN values can also set this bit when exiting an ISR. An exception that pre-empts a user thread saves the context of the user thread on the stack that the Thread mode is using. All exceptions use the main stack for their own local variables. Using the process stack for the Thread mode and the main stack for exceptions supports Operating System (OS) scheduling. To reschedule, the kernel only requires to save the eight registers not pushed by hardware, r4-r11, and to copy SP_process into the Thread Control Block (TCB). If the processor saved the context on the main stack, the kernel would have to copy the 16 registers to the TCB. Note M S R a n d M R S i n s t r u c t i o n s h ave v i s i b i l i t y o17 f b o t h s t a c k s.

Stacking When the processor invokes an exception, it automatically pushes the following eight registers to the SP in the following order: Program Counter (PC) Processor Status Register (xpsr) r0-r3 r12 Link Register (LR). The SP is decremented by eight words by the completion of the stack push. Figure 5-1 shows the contents of the stack after an exception pre-empts the current program flow. Old SP SP <previous> xpsr PC LR r12 r3 r2 r1 r0 Figure 5-1 Stack contents after a pre-emption Note 18

Exceptions The exception types are: Reset NMI Hard fault Reset is invoked on power up or a warm reset. The exception model treats reset as a special form of exception. When reset is asserted, the operation of the processor stops, potentially at any point in an instruction. When reset is deasserted, execution restarts from the address provided by the reset entry in the vector table. Execution restarts as privileged execution in Thread mode. A NonMaskable Interrupt (NMI) can be signalled by a peripheral or triggered by software. This is the highest priority exception other than reset. It is permanently enabled and has a fixed priority of -2. NMIs cannot be: Masked or prevented from activation by any other exception Preempted by any exception other than Reset. A hard fault is an exception that occurs because of an error during exception processing, or because an exception cannot be managed by any other exception mechanism. Hard faults have a fixed priority of -1, meaning they have higher priority than any exception with configurable priority. Memory management fault A memory management fault is an exception that occurs because of a memory protection related fault. The fixed memory protection constraints determines this fault, for both instruction and data memory transactions. This fault is used to abort instruction accesses to Execute Never (XN) memory regions. 19

Exceptions Bus fault Usage fault SVCall PendSV SysTick Interrupt (IRQ) A bus fault is an exception that occurs because of a memory related fault for an instruction or data memory transaction. This might be from an error detected on a bus in the memory system. A usage fault is an exception that occurs because of a fault related to instruction execution. This includes: An undefined instruction An illegal unaligned access Invalid state on instruction execution An error on exception return. The following can cause a usage fault when the core is configured to report them: An unaligned address on word and halfword memory access Division by zero A supervisor call (SVC) is an exception that is triggered by the SVC instruction. In an OS environment, applications can use SVC instructions to access OS kernel functions and device drivers. PendSV is an interrupt-driven request for system-level service. In an OS environment, use PendSV for context switching when no other exception is active. A SysTick exception is an exception the system timer generates when it reaches zero. Software can also generate a SysTick exception. In an OS environment, the processor can use this exception as system tick. A interrupt, or IRQ, is an exception signalled by a peripheral, or generated by a software request. All interrupts are asynchronous to instruction execution. In the system, peripherals use interrupts to communicate with the processor. 20

Vector Table Figure 12. Vector table Exception number IRQ number Offset Vector 83 67 0x014C IRQ67......... 18 17 16 15 14 13 2 1 0-1 -2 0x004C 0x0048 0x0044 0x0040 0x003C 0x0038 IRQ2 IRQ1 IRQ0 Systick PendSV Reserved 12 Reserved for Debug 11 10-5 0x002C SVCall 9 8 Reserved 7 6 5 4 3 2 1-10 -11-12 -13-14 0x0018 0x0014 0x0010 0x000C 0x0008 0x0004 0x0000 Usage fault Bus fault Memory management fault Hard fault NMI Reset Initial SP value 21 ai15995

Some Interrupts Table 50. Vector table for STM32F100xx devices (continued) Position Priority Type of priority Acronym Description Address 23 30 settable EXTI9_5 EXTI Line[9:5] interrupts 0x0000_009C 24 31 settable TIM1_BRK_TIM15 25 32 settable TIM1_UP_TIM16 TIM1 Break and TIM15 global interrupt TIM1 Update and TIM16 global interrupts 0x0000_00A0 0x0000_00A4 26 33 settable TIM1_TRG_COM_T IM17 TIM1 Trigger and Commutation and TIM17 global interrupts 0x0000_00A8 27 34 settable TIM1_CC TIM1 Capture Compare interrupt 0x0000_00AC 28 35 settable TIM2 TIM2 global interrupt 0x0000_00B0 29 36 settable TIM3 TIM3 global interrupt 0x0000_00B4 30 37 settable TIM4 TIM4 global interrupt 0x0000_00B8 31 38 settable I2C1_EV I 2 C1 event interrupt 0x0000_00BC 32 39 settable I2C1_ER I 2 C1 error interrupt 0x0000_00C0 33 40 settable I2C2_EV I 2 C2 event interrupt 0x0000_00C4 34 41 settable I2C2_ER I 2 C2 error interrupt 0x0000_00C8 35 42 settable SPI1 SPI1 global interrupt 0x0000_00CC 36 43 settable SPI2 SPI2 global interrupt 0x0000_00D0 37 44 settable USART1 USART1 global interrupt 0x0000_00D4 38 45 settable USART2 USART2 global interrupt 0x0000_00D8 39 46 settable USART3 USART3 global interrupt 0x0000_00DC 40 47 settable EXTI15_10 EXTI Line[15:10] interrupts 0x0000_00E0 RTC Alarms (A and B) through EXTI 22

Placement in Memory 23

startup Code startup_stm32f10x.c 24

Cortex-M3 Figure 1. STM32 Cortex-M3 implementation STM32 Cortex-M3 processor NVIC Processor core Embedded Trace Macrocell Debug access port Flash patch Data watchpoints Serial wire viewer Code interface Bus matrix SRAM and peripheral interface ai15994 25

NVIC 4.3 Nested vectored interrupt controller (NVIC) This section describes the Nested Vectored Interrupt Controller (NVIC) and the registers it uses. The NVIC supports: up to 81 interrupts (depends on the STM32 device type, refer to the datasheets) A programmable priority level of 0-15 for each interrupt. A higher level corresponds to a lower priority, so level 0 is the highest interrupt priority Level and pulse detection of interrupt signals Dynamic reprioritization of interrupts Grouping of priority values into group priority and subpriority fields Interrupt tail-chaining An external Non-maskable interrupt (NMI) The processor automatically stacks its state on exception entry and unstacks this state on exception exit, with no instruction overhead. This provides low latency exception handling. The hardware implementation of the NVIC registers is: 26

NVIC -- interrupt enable 4.3.2 Interrupt set-enable registers (NVIC_ISERx) Address offset: 0x00-0x0B Reset value: 0x0000 0000 Required privilege: Privileged 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SETENA[31:16] rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SETENA[15:0] rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs Bits 31:0 SETENA[31:0]: Interrupt set-enable bits. Write: 0: No effect 1: Enable interrupt Read: 0: Interrupt disabled 1: Interrupt enabled. See Table 41: Mapping of interrupts to the interrupt variables on page 120 for the 27

Interrupt Active 4.3.6 Interrupt active bit registers (NVIC_IABRx) Address offset: 0x00-0x0B Reset value: 0x0000 0000 Required privilege: Privileged The IABR0-IABR2 registers indicate which interrupts are active. The bit assignments are: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ACTIVE[31:16] r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ACTIVE[15:0] r r r r r r r r r r r r r r r r Bits 31:0 ACTIVE[31:0]: Interrupt active flags 0: Interrupt not active 1: Interrupt active 28

Pending 4.3.5 Interrupt clear-pending registers (NVIC_ICPRx) Address offset: 0x00-0x0B Reset value: 0x0000 0000 Required privilege: Privileged The ICPR0-ICPR2 registers remove the pending state from interrupts, and show which interrupts are pending. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CLRPEND[31:16] rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CLRPEND[15:0] rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 Bits 31:0 CLRPEND[31:0]: Interrupt clear-pending bits Write: 0: No effect 1: Removes the pending state of an interrupt Read: 0: Interrupt is not pending 1: Interrupt is pending See Table 41: Mapping of interrupts to the interrupt variables on page 120 for the 29

Software Trigger 4.3.8 Software trigger interrupt register (NVIC_STIR) Address offset: 0xE00 Reset value: 0x0000 0000 Required privilege: When the USERSETMPEND bit in the SCR is set to 1, unprivileged software can access the STIR, see Section 4.4.6: System control register (SCB_SCR). Only privileged software can enable unprivileged access to the STIR. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved INTID[8:0] w w w w w w w w w Bits 31:9 Reserved, must be kept cleared. Bits 8:0 NTID[8:0] Software generated interrupt ID Write to the STIR to generate a Software Generated Interrupt (SGI). The value to be written is the Interrupt ID of the required SGI, in the range 0-239. For example, a value of 0b000000011 specifies interrupt IRQ3. 30

Interrupt Priority 4.3.7 Interrupt priority registers (NVIC_IPRx) Address offset: 0x00-0x0B Reset value: 0x0000 0000 Required privilege: Privileged The IPR0-IPR16 registers provide a 4-bit priority field for each interrupt. These registers are byte-accessible. Each register holds four priority fields, that map to four elements in the CMSIS interrupt priority array IP[0] to IP[67], as shown in Figure 19. Figure 19. NVIC IPRx register mapping 31 24 23 16 15 8 7 0 IPR20 Reserved Reserved Reserved IP[80]...... IPRm...... IP[4m + 3] IP[4m + 2] IP[4m + 1] IP[4m ] IPR0 IP[3] IP[2] IP[1] IP[0] Table 42. IPR bit assignments Bits Name Function [31:24] Priority, byte offset 3 [23:16] Priority, byte offset 2 [15:8] Priority, byte offset 1 [7:0] Priority, byte offset 0 Each priority field holds a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. The processor implements only bits[7:4] of each field, bits[3:0] read as zero and ignore writes. See The CMSIS mapping of the Cortex-M3 NVIC registers on page 120 for more 31

Tasks For Interrupt Handler 1. Determine interrupt cause 2. Remove interrupt cause (e.g. clear bit, reset timer, read data) 3. Do anything else that needs to be done 4. Re-enable interrupt and return 32

Systick Interrupt void default_handler (void) { while(1); } void SysTick_Handler (void) attribute ((weak, alias ("default_handler"))); 33

Vector names For F3, vectors are in file: startup_stm32f30x.s 34

Handler Template 35

Enabling Interrupts 36

External Interrupts 37

Configuring External Interrupts 38

Preserve, Preserve, Preserve Interrupt handlers must not have unintended side effects. Save and restore all registers used. Don t modify application data. Don t use application I/O resources. 39

Issues With Interrupts Shared Procedures Handler 1 Main() Shared Data Shared Devices Handler n Main code and handlers execute asynchronously to each other. 40

what could it print? include <stdio.h> int c = 0xff; // volatile prevents use in register volatile int done = 0; void handler(void) { c = c >> 1; done = 1; } int main () { // enable handler c++; while (!done); printf("%d", c); return 0; } 41

Shocking answer! 128 or 256 What s going on! 42

Here s the assembly handler: ldr r3,.l2 ldr r2, [r3, #0] asr r2, r2, #1 str r2, [r3, #0] mov r2, #1 ldr r3,.l2+4 str r2, [r3, #0] bx lr.l3:.align 2.L2:.word.LANCHOR0.word.LANCHOR1 main:.l5:.l8:.l7: push {r3, lr} ldr r3,.l7 ldr r1, [r3, #0] add r1, r1, #1 str r1, [r3, #0] ldr r2,.l7+4 ldr r3, [r2, #0] cmp r3, #0 beq.l5 ldr r0,.l7+8 bl printf mov r0, #0 pop {r3, pc}.align 2.word.word.word.LANCHOR0.LANCHOR1.LC0

Synchronization problem! If the handler interrupt comes after the FETCH instruction but before the STORE instruction, the handler store value is lost due to the main STORE, based on the FETCH value. This is an example of a read/write synchronization problem. If the handler could itself be interrupted and main execution resume before the handler finishes (as might be possible in a more complex operating environment), or if the handler ran on a separate processor (core), the value 127 might also be printed! 44