Rev. 0 February 007 User manual Document information Info Content Keywords ispa, ispb, usb, universal serial bus, peripheral Abstract This document explains the ISPx microcontroller eval kit. This kit enables you to evaluate the ISPx, and also perform firmware and product prototype development. Remark: The file name of the previous revision is _MCU_EVAL_KIT_MANUAL- 0.pdf. Remark: ISPx denotes the ISPA and the ISPB, and any future derivative.
Revision history Rev Date Description 0 0070 First release. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com _ User manual Rev. 0 February 007 of
. Introduction. System requirements Remark: ISPx denotes the ISPA and the ISPB, and any future derivative. The ISPx is a full-speed cost-optimized and feature-optimized Universal Serial Bus (USB) Peripheral Controller with up to configurable endpoints. It has a high-speed general-purpose parallel interface to communicate with many types of microcontrollers or microprocessors. It supports bus configurations and local Direct Memory Access (DMA) transfers of up to 6 bytes per cycle. To a microcontroller, the ISPx appears as a memory device with an -bit or 6-bit data bus and a -bit address bus. The ISPx supports both multiplexed and nonmultiplexed address and data bus. The ISPx can also be configured as a DMA slave device to allow more efficient data transfer. One of the endpoint FIFOs may directly transfer data to or from the local shared memory. Feature evaluation of the ISPx, firmware and product prototype development can easily be done with this set up. The ISPx microcontroller evaluation (eval) kit comes with the ISPx, microcontroller boards, test application program, USB driver, and sample firmware source codes. The firmware provided with the kit is written in the C language, allowing you to port it to other platforms for compilation. With this kit, you can develop your USB peripherals through firmware and hardware schematics. Running the kit only requires a new-generation PC, motherboard with the USB port, with Microsoft Windows or Windows 000 operating system.. Jumper settings on the ISPx board Jumpers JP and JP set bus configuration mode of the ISPx. Table shows Mode of the bus configuration as the default setting. Table. Default setting for the bus configuration JP and JP Jumper number Default setting JP Short pins and JP Short pin and Jumpers JP and JP are for debugging. When used, all the signals from the ISPx can be propagated. For the JP and JP pin outs, see Section 7. Table. Default setting for the bus configuration JP Jumper number Default setting JP Short pin and 0 The ISPx has four bus configuration modes, selected using pins BUS_CONF and BUS_CONF0: Mode 0: 6-bit port shared with the 6-bit DMA port Mode : reserved _ User manual Rev. 0 February 007 of
Mode : -bit port shared with the -bit DMA port Mode : reserved Table shows the bus configuration for each of these modes. Table. Bus configuration modes Mode BUS_CONF[:0] PIO data width DMA data width (DMAWD = 0) DMA data width (DMAWD = ) 0 00 DATA[:0], 6-bit - 6-bit on D[:0] = DMA DATA[:0] 0 reserved reserved reserved 0 DATA[7:0], -bit -bit on D[7:0] = DMA DATA [7:0] - reserved reserved reserved. Pin signal information of connectors Table. Pin description for JP and JP Pin Type Description Power V CC The connection between the ISPx microcontroller board and the ISPx board is through a 0-pin connector on the ISPx microcontroller board (JP) and the ISPx board (JP), respectively. Table shows the pin description of JP and JP. Power V CC DATA0 I ISPx EOT DATA 6 O ISPx DREQ: This line is an asynchronous channel request used by the peripheral to gain DMA service. Bringing the DRQ line to active HIGH generates a DMA request. 7 DATA I ISPx DACK: This line is used to acknowledge the DMA request and is active LOW. DATA 0 Power ISA-V DATA Power ISA-V DATA I ISPx CS# DATA6 6 I ISPx WR#: This command line instructs an device to read data on the data bus. The processor or the DMA controller may drive it. This signal is active LOW. _ User manual Rev. 0 February 007 of
Pin Type Description 7 DATA7 I ISPx RD#: This command line instructs an device to drive its data on the data bus. The processor or the DMA controller may drive it. This signal is active LOW. DATA 0 I ISPx WAKEUP DATA O ISPx READY DATA0 O ISPx SUSPEND DATA 6 O ISPx INT: This line is rising edge-triggered. Raising this line HIGH and holding until the processor acknowledges it generates an interrupt request. 7 DATA Power DATA 0 I DATA Power DATA I ISPx RESET# Power 6 Power 7 I ISPx A0 O ISPx CLKOUT Power 0 Power. Installation of hardware, firmware, INF and driver. Connect JP on the ISPx microcontroller board to JP on the ISPx board.. Connect the USB cable between J on the ISPx board and the host PC.. If it is the first time that the eval board is connected to the host PC, the host operating system Device Manager will prompt for the installation of INF and driver. _ User manual Rev. 0 February 007 of
6. Using the host applet. Select the location of TEST.INF and TEST.SYS from the ISPx evaluation CD, and complete the installation procedure. TEST.INF and TEST.SYS are located under ISP MCU Driver (Win&K) Ver..zip. After unzipping files, run the ISP MCU Driver (Win&K) Ver..exe and click through the install shield process to successfully install the driver on your PC. The default installation directory is C:\Program Files\NXP\ISP MCU Driver(Win_K) Ver.. Test applet TEST.EXE exercises all ISPx endpoints as shown in Fig. Fig. Applet TEST Further testing of control endpoints can be done using standard USB Chapter test programs. Table describes the endpoint operations on the ISPx eval board. _ User manual Rev. 0 February 007 6 of
Table. Description of endpoint operations The test applet and the ISPx eval board support three test modes: loopback, print and scan. The firmware uses accesses on this endpoint Endpoint number Endpoint type Operations ISO-OUT This pipe is defined as an isochronous OUT pipe. ISO-IN This pipe is defined as an isochronous IN pipe. Bulk-OUT This pipe is defined as a bulk OUT pipe. Bulk-IN This pipe is defined as a bulk IN pipe. Three test modes: Scan mode: In this mode, the ISPx eval board acts like a scanner. It sends data packets to the host PC as fast as possible. Use this mode to evaluate the isochronous IN and bulk IN transfer rates. Print mode: In this mode, the ISPx eval board acts like a printer. It receives data packets from the host PC as fast as possible. Use this mode to evaluate the isochronous OUT and bulk OUT transfer rates. Loopback mode: In this mode, the ISPx eval board receives data packets on the isochronous OUT or bulk OUT endpoint and sends them back to the host PC on the isochronous IN or bulk IN endpoint. Use this mode to test the data integrity of transfers. The Buffer Size setting on the test applet is determined by firmware and hardware capability of the eval board. For the microcontroller eval kit, the maximum size is limited to 6000 for the bulk transfer. Remark: The DMA Enabled checkbox in the upper-right corner of TEST must be enabled. Repeat Times for the loopback test controls the numbers of iterations of loopback, which is useful for debugging. To run the test infinite times, set Repeat Times as. _ User manual Rev. 0 February 007 7 of
7. Schematics RP 6 7 6 7.7 kω RP.7 kω 6 0 6 0 RESET MCU-X EA T ISP-INT ISP-RESET# LE LE IO-CS# ISP-WAKEUP ISP-READY 0 U RST XTAL EA/VPP RXD/P.0 INT0/P. INT/P. T0/P. T/P. P0.0/A P0./A 7 P0./A 6 P0.A P0./A P0./A P0.6/A P0.7/A P.0 P. P. 0 VSS 0C(0) 0 PSEN XTAL 7 RD/P.7 6 WR/P.6 TXD/P. /PROG 0 P.7/A 7 P.6/A 6 P./A P./A P./A P./A0 P./A P.0/A P. P.6 7 P. P. P. PSEN# MCU-X RD# WR# DMA-RESET# A A A A A A0 A A PB PB 6 7 RP.7 kω DMA-INTRANSFER DMA-START/ PAUSE T 6 0 R 0 kω MCU-X EA PSEN# A A A A A A0 A A JP 0 0 0 0 HEADER 0X JP IO-CS# ISP-WAKEUP ISP-READY T DMA-START/ PAUSE 0 DMA-INTRANSFER PB PB RESET T 0 DMA-RESET# ISP-INT ISP-RESET# LE LE 0 WR# RD# MCU-X MCU-X 0 HEADER 0X R kω ISP-CLKOUT R * 0 Ω * do not mount Y MCU-X R 0 Ω PB PB S SW-PB S SW-PB 0-RST S SW-PB R 0 Ω C 0 μf/6 V R6. kω RESET C 0 pf MHz C6 0 pf R7 60 Ω LED R 60 Ω LED EV-CPLD EV-CPLD.sch EV-MEM EV-MEM.sch LE LE C 0 μf/6 V C Fig. Schematics _ User manual Rev. 0 February 00 of
SRAM can be 6K* or K* ns or higher speed grade SRAM-A6 SRAM-A SRAM-A SRAM-A SRAM-A SRAM-A SRAM-A0 SRAM-A SRAM-A SRAM-A7 SRAM-A6 SRAM-A SRAM-A SRAM-A SRAM-A SRAM-A SRAM-A0 6 7 6 7 0 U A6 A A A A A A0 A A A7 A6 A A A A A A0 0 7 NC 6 0 CE WE OE CE R0 0 kω SRAM-WR# SRAM-RD# SRAM-CS# R0 0 kω SRAM-A6 SRAM-A SRAM-A SRAM-A SRAM-A SRAM-A SRAM-A0 SRAM-A SRAM-A SRAM-A7 SRAM-A6 SRAM-A SRAM-A SRAM-A SRAM-A SRAM-A SRAM-A0 6 7 6 7 0 U A6 A A A A A A0 A A A7 A6 A A A A A A0 0 7 NC 6 CE 0 WE OE CE 0 D D R 0 kω SRAM-WR# SRAM-RD# SRAM-CS# R 0 kω SRAM K* (SOIC) SRAM K* (SOIC) C 0 μf/6 V C C 0 μf/6 V C Fig. Schematics _ User manual Rev. 0 February 007 of
D D 0 ISP-A0 JP 0 0 0 0 ISP-EOT ISP-DREQ ISP-DACK ISA-V ISP-CS# ISP-WR# ISP-RD# ISP-WAKEUP ISP-READY ISP-SUSPEND ISP-INT ISP-RESET# ISP-CLKOUT (V) R6 0 Ω CPLD- R7 0 Ω TCK TDO TMS TDI * * do not mount R kω CPLD- R kω R kω R kω JP 0 HEADER X CPLD- HEADER 0X 7 6 SRAM-RD# RD# SRAM-RD# SRAM-A 6 DMA-START/PAUSE 7 SRAM-A SRAM-A 0 SRAM-A6 T CPLD-CLK 6 IO-CS# 7 CLKOUT SRAM-A ISP-EOT 0 SRAM-A0 SRAM-A7 WR# SRAM-WR# 7 ISP-CS# SRAM-A 6 XC7XL-0 TDI TMS TCK TDO U 6 0 6 7 0 6 7 60 6 6 6 6 DMA-INTRANSFER SRAM-WR# ISP-A0 SRAM-CS# SRAM-CS# ISP-DACK SRAM-A T A ISP-SUSPEND SRAM-A ISP-DREQ SRAM-A SRAM-A SRAM-A SRAM-A ISP-RD# 0-RST SRAM-A SRAM-A0 SRAM-A ISP-WR# DMA-RESET# CPLD- C6 C7 C C 0 C 0 μf U LM7 IN OUT ADJ R 0 Ω / % C C7 0 μf R Ω / % TDI TMS TCK TDO (V) C C0 MHz OE CLOCK Y -CLKOUT R 0 Ω R 0 Ω CPLD-CLK * * do not mount Fig. Schematics _ User manual Rev. 0 February 007 0 of
User manual Rev. 0 February 007 of _ R R.7 kω.7 kω R.7 kω R R.7 kω.7 kω R6.7 kω JP JUMPER JP JUMPER Fig. Schematics R 0 Ω D D 0 ISP-WR# ISP-RD# ISP-CS# ISP-READY ISP-A0 ISP-INT ISP-WAKEUP ISP-SUSPEND ISP-DREQ ISP-DACK ISP-EOT BUS-CONF0 BUS-CONF R 0 kω R 0 kω SDRD# SDWR# 0 7 0 0 6 0 7 U A DATA DATA DATA DATA DATA DATA6 DATA7 DATA DATA DATA0 DATA DATA DATA DATA DATA WR RD CS TEST A0 INT WAKEUP SUSPEND DREQ DACK EOT BUS_CONF0 BUS_CONF TEST TEST ISP _p _p.sch RESET VBUS D+ D VREG(.) 6 (.) 6 REG D+ D ISP-X ISP-X ISP-GL# ISP-CLKOUT VREG(V) bus-power ISP-RESET# R 0 kω 6 VBUS-SENSE XTAL XTAL 7 GL 7 CLKOUT 7 V REF 6 (V) VREF C C0 C C7 R0 kω R MΩ ISP-GL# JP ISP-X ISP-X ISP-CLKOUT ISP-RESET# 0 ISP-CS# ISP-WR# ISP-RD# ISP-A0 0 (V) 0 0 D D VREF 6 C 0 μf LED R7 60 Ω VREG(V) HEADER X C μf/ 6 V ISP-X 6 MHz ISP-X C pf Y VREG(V) VREF pf C VREG(V) D D+ VBUS-SENSE ISP-GL# ISP-WAKEUP ISP-SUSPEND ISP-EOT ISP-DREQ ISP-DACK SDWR# SDRD# ISP-INT ISP-READY BUS-CONF0 BUS-CONF 0 JP6 HEADER X (V) JP 0 0 0 0 6 HEADER X (V) JP HEADER X NXP Semiconductors
JP7 VREG(V) R. kω * R6 MΩ D D 0 ISP-A0 0 0 0 0 ISP-EOT ISP-DREQ ISP-DACK ISA-V ISP-CS# ISP-WR# ISP-RD# ISP-WAKEUP ISP-READY ISP-SUSPEND ISP-INT ISP-RESET# ISP-CLKOUT HEADER 0X D+ D R Ω / ± % R Ω / ± % C6 pf C7 pf R7 MΩ bus-power R0 R L BLMA0 0 Ω 0 Ω BLMA0 C L bus-power USBD USBD+ USB J VBUS D D+ CHASSIS C USB_UPCON 0.07 μf, kv D D 0 ISP-A0 JP 0 0 0 0 ISP-EOT ISP-DREQ ISP-DACK ISA-V ISP-CS# ISP-WR# ISP-RD# ISP-WAKEUP ISP-READY ISP-INT ISP-RESET# ISP-CLKOUT S ISA-V CONN 0X LED C C 0 μf /6 V SW DPDT self-power bus-power C6 0 μf L BLMA0 C C C 0 μf S POWER-RCA R 60 Ω * do not mount Fig 6. Schematics _ User manual Rev. 0 February 007 of
. References ISPA Full-speed Universal Serial Bus peripheral controller data sheet ISPB Full-speed Universal Serial Bus peripheral controller data sheet Universal Serial Bus Specification Rev..0. _ User manual Rev. 0 February 007 of
. Legal information. Definitions Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information.. Disclaimers General Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is for the customer s own risk. Applications Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.. Trademarks Notice: All referenced brands, product names, service names and trademarks are property of their respective owners. _ User manual Rev. 0 February 007 of
0. Contents. Introduction.... System requirements.... Jumper settings on the ISPx board.... Pin signal information of connectors.... Installation of hardware, firmware, INF and driver... 6. Using the host applet...6 7. Schematics.... References.... Legal information.... Definitions.... Disclaimers.... Trademarks... 0. Contents... Please be aware that important notices concerning this document and the product(s) described herein, have been included in the section Legal information. For more information, please visit: http://www.nxp.com. For sales office addresses, email to: salesaddresses@nxp.com. Date of release: February 007 Document identifier: _