vii TABLE OF CONTENTS CHAPTER NO. TITLE PAGE NO. ABSTRACT LIST OF TABLES LIST OF FIGURES LIST OF SYMBOLS AND ABBREVIATION iii xii xiv xvii 1 INTRODUCTION 1 1.1 GENERAL 1 1.2 TYPES OF WIRELESS COMMUNICATION NETWORKS 1 1.3 EVOLUTION OF WIRELESS COMMUNICATION NETWORKS 3 1.4 SECURITY ISSUES IN WIRELESS COMMUNICATION 5 1.4.1 Wireless Security Threats 5 1.4.2 Security Objectives and Services 6 1.5 NEED FOR SOFTWARE-DEFINED RADIO 7 1.6 SECURITY ISSUES IN SOFTWARE DEFINED RADIO 8 1.7 MOTIVATION OF RESEARCH 16 1.8 OBJECTIVES OF THESIS 18 1.9 ORGANIZATION OF THESIS 18
viii CHAPTER NO. TITLE PAGE NO. 2 LITERATURE REVIEW 20 2.1 INTRODUCTION 20 2.2 SECURITY ISSUES IN SDR A SURVEY 21 2.3 HARDWARE IMPLEMENTATION OF CRYPTOGRAPHIC ALGORITHM A SURVEY 24 2.4 CONCLUSION 29 3 DESIGN AND DEVELOPMENT OF RECONFIGURABLE ARCHITECTURE FOR DATA INTEGRITY UNIT 31 3.1 INTRODUCTION 31 3.2 HASHING ALGORITHM SHA-192 34 3.2.1 Algorithm Description 35 3.2.2 Mathematical Model 36 3.2.3 Operations on Words 37 3.2.4 Message Padding 37 3.2.5 SHA-192 Hash Computation 37 3.2.6 Computing Message Digest 38 3.2.7 Security Analysis 40 3.3 MD-5 ALGORITHM 41 3.3.1 Algorithm Description 41 3.4 HARDWARE IMPLEMENTATION OF MD5 45 3.5 UNIFIED ARCHITECTURE OF MD5 AND SHA- 192 47 3.5.1 Hash Function Core 48 3.6 RESULTS AND DISCUSSION 53
ix CHAPTER NO. TITLE PAGE NO. 3.6.1 Synthesis Output 53 3.6.2 Area Delay Product Analysis 55 3.6.3 Throughput Analysis 56 3.7 OUTCOME OF PLACING AND ROUTING 57 3.8 POWER CONSUMPTION 59 3.9 VERIFICATION AND VALIDATION OF THE RECONFIGURABLE HARDWARE 60 3.9.1 Verification of the Hardware 60 3.9.2 Testing Of Reconfigurable Hardware 62 3.10 PERFORMANCE COMPARISON 62 3.11 SUMMARY 63 4 DESIGN AND DEVELOPMENT OF RECONFIGURABLE ARCHITECTURE FOR AUTHENTICATION UNIT 65 4.1 INTRODUCTION 65 4.2 PROPOSED METHODOLOGY 66 4.2.1 RSA Algorithm 67 4.2.1.1 RSA Signature Algorithm 68 4.2.2 D.H Algorithm 69 4.3 ARCHITECTURE FOR AUTHENTICATION UNIT 70 4.3.1 Implementation of Divider Architecture 70 4.3.2 Modular Inverse 73 4.3.3 Modular Exponentiation 75 4.3.3.1 Montgomery Multiplication 76 4.3.3.2 Montgomery Multiplication for RSA Exponentiation 79
x CHAPTER NO. TITLE PAGE NO. 4.4 IMPLEMENTATION OF AUTHENTICATION UNIT 80 4.5 VERIFICATION AND TESTING 81 4.6 OUTCOME OF PLACING AND ROUTING 83 4.7 POWER CONSUMPTION 84 4.8 PERFORMANCE ANALYSIS 85 4.9 SUMMARY 86 5 DESIGN AND DEVELOPMENT OF AES-128/192/256 ENCRYPTOR AND DECRYPTOR UNIT 88 5.1 INTRODUCTION 88 5.2 ENCRYPTOR / DECRYPTOR ARCHITECTURE AES-128/192/256 90 5.3 IMPLEMENTATION OF AES-128/192/256 ENCRYPTION ARCHITECTURE 91 5.3.1 Encryption Module 93 5.3.1.1 Results and Discussion 94 5.3.1.2 Substitution Bytes (S - Box) 94 5.3.1.3 Shift Rows 96 5.3.1.4 Mix-Column 97 5.3.1.5 Key expansion 98 5.3.1.6 Add round key 99 5.4 IMPLEMENTATION OF AES-128/192/256 DECRYPTION ARCHITECTURE 102 5.4.1 Inverse Shift Rows 103 5.4.2 Inverse Byte Substitution 104
xi CHAPTER NO. TITLE PAGE NO. 5.4.3 Inverse Mix Column 105 5.4.4 Decryption Architecture 106 5.5 IMPLEMENTATION OF AES ENCRYPTOR AND DECRYPTOR 107 5.5.1 Synthesis Output 107 5.5.2 Testing and Verification 108 5.6 VERIFICATION AND VALIDATION OF THE RECONFIGURABLE HARDWARE 110 5.6.1 Verification of the Hardware 110 5.7 PERFORMANCE ANALYSIS 113 5.8 SUMMARY 115 6 CONCLUSION AND FUTURE WORK 116 6.1 CONCLUSION 116 6.2 SCOPE FOR FUTURE WORK 117 REFERENCES 119 LIST OF PUBLICATIONS 129 VITAE 130
xii LIST OF TABLES TABLE NO. TITLE PAGE NO. 1.1 Basic Enforcement of SDR Security Mechanism 15 3.1 Attacks on Standard Hash Function 40 3.2 Device e Utilization Summary of MD5, SHA-192 and Combined Architecture 54 3.3 Throughput Analysis MD5, SHA-192 and Combined Architecture 56 3.4 Power Consumed by Target Device 60 3.5 Performance Comparison of Proposed Unified Architecture with Previous Work 63 4.1 Binary (radix 2) Non- Restoring Division 71 4.2 Hardware Utilization of Divider 73 4.3 Algorithm to Compute Extended GCD of Two Factors 74 4.4 Hardware Utilization of Inverse Algorithm 75 4.5 Algorithm to perform A*B mod n 76 4.6 Algorithm to perform Four-to-two CSA Montgomery Multiplication 77 4.7 Device utilization summary of Montgomery Multiplication 78 4.8 Algorithm to Perform Modified Modular Multiplier Exponentiation C d Mod n 79 4.9 Device utilization summary of Modular Exponentiation 80 4.10 Device utilization summary of RSA and DH Algorithms 81 4.11 Device Utilization of Unified Architecture 81
xiii TABLE NO. TITLE PAGE NO. 4.12 Performance Comparison of Proposed Design with Previous Works 86 5.1 Device Utilization Summary for Synthesizing Target Device 108 5.2 Comparison of Hardware Performance of All AES Candidates Using Different Architecture 113 5.3 Comparison of Performance of Proposed Architecture with Different Devices 114
xiv LIST OF FIGURES FIGURE NO. TITLE PAGE NO. 1.1 Types of Wireless Communication Networks 2 1.2 Evolution History of WWAN Systems 3 1.3 Accessing Multiple Networks and Services Through Multi-Mode Software 7 1.4 An Overview of Proposed Models 17 3.1 SHA-192 Compression Function 36 3.2. Compression Function MD5 43 3.3 Operation Of Single Step Of MD5 43 3.4 Hardware Architecture of MD5 45 3.5 Data Transformation in MD5 Hardware Architecture 47 3.6 Unified Hardware Architecture of MD5 And SHA-192 Hash Function 48 3.7 Data Transformation for Combined Hash Computation 51 3.8 Area-Delay Product Comparisons 55 3.9 Throughput Comparisons of Proposed Design 56 3.10 RTL Schematic of Combined Architecture 57 3.11 Schematic Block Diagram of Integrity Unit 58 3.12 View of Integrity Unit after Routing 58 3.13 Hash Output for MD-5 Unified Architecture 61 3.14 Hash Output for SHA-192 Unified Architecture 61 4.1. Block Diagram of Reconfigurable Authentication Unit 66 4.2 Flow chart of Non-restoring Division 72 4.3 Non-Restoring Divider Architecture 72 4.4 Block Diagram of 4 to 2 CSA 78 4.5 Area Utilization Comparisons 82
xv FIGURE NO. TITLE PAGE NO. 4.6 Schematic Diagram of Authentication Unit 83 4.7 View of Authentication Unit after Routing 84 4.8 Power Consumption Comparisons 85 5.1 Block Diagram of AES- 128/192/256 Encryptor and Decryptor Architecture 92 5.2 Encryption Process of AES 94 5.3 Schematic Diagram of substitution bytes 95 5.4 Block Diagram of FDC 95 5.5 Schematic Blocks Inside substitution byte 96 5.6 Schematic Diagram of Shift Rows 96 5.7 Functional Blocks Inside Shift Row Module 97 5.8 Schematic Diagram of Mix-column 97 5.9 Functional Blocks Inside Mix-Column Module 98 5.10 Blocks Inside Polynomial Multiplication Block 98 5.11 Schematic Diagram For Key Expansion 99 5.12 Schematic Diagram Of Add Round key 100 5.13 Functional Blocks Inside Add Round key 100 5.14 Functional Blocks Inside Processing Block 101 5.15 Gates Inside Block 101 5.16 Schematic Diagram of Encryption Module 102 5.17 Decryption Process of AES 103 5.18 Schematic Diagram of Inverse Shift Row 104 5.19 Schematic Diagram of Inverse Byte Substitution Operation 104 5.20 Functional Blocks Inside Inverse Byte Substitution module 105 5.21 Schematic Diagram of Inverse Mix Column 106
xvi FIGURE NO. TITLE PAGE NO. 5.22 Schematic Diagram of Decryption Module 106 5.23 Schematic Diagram of Encryptor and Decryptor 107 5.24 RTL schematic of Encryptor and Decryptor 109 5.25 Simulated Output of 256 bit key 110 5.26 Simulated Output of 198 bit key 111 5.27 Simulated Output of 128-bit key 112
xvii LIST OF SYMBOLS AND ABBREVIATIONS Symbols A, B, C, D - 32-bit registers Y q - 512-bit block of message H i - Buffer to Store Initial Hash Values CV q - Chaining Variable C - Cipher Text Kt - Constant Words K i - Constant Input X<< s - Circularly Shifting X Left by S Bit Position d - Decryption Key A V B - Denotes Bit-Wise Logical OR of A and B A B - Denotes Bit-Wise Logical AND of A and B ~ (A) - Denotes Bit-Wise Logical Complement of A A XOR B - Denotes Bit-Wise Logical Exclusive OR of A and B, X XOR Y - Denotes Bit-Wise XOR of X and Y XY - Denote The Bit Wise AND of X and Y. e - Encryption Key MHz - Frequency in Mega Hertz GF(p) - Galois Field gcd - Greatest Common Divisor Nk - Key Length p,q - Large Prime Numbers - Less than or Equal to < - Less Than V - Logical or operation - Logical AND operation Mbps - Megabits per second
xviii m i - Message input + - Modulo-2 32 addition Nb - Number of blocks Nr - Number of rounds ft (A,B,C) - Nonlinear function of (A,B,C) mw - Power in mill watts n - Product of two primes p and q - Primitive Root of q M - Plain Text R(x) - Round Key (n) - toteint function W i - words of the message schedule Abbreviation AC - Attribute certificate AES - Advanced Encryption Standard ASICs - Application Specific Integrated Circuits CDMA - Code Division Multiple Access CLBs - Combinational Logical Blocks CLR - Clear input CODEC - coder/decoder CSR - Carry Save Representation D-AES - Diversified- Advanced Encryption Standard DES - Data Encryption Standard Dffs - D-flip-flops DH - Diffie- Hellman Algorithm DSPs - Digital Signal Processors FCC - Federal Communication Commission FIPS - Federal Information Processing Standard FPGA - Field Programmable Gate Array
xix HMAC - Medium Access Control I/Os - Input/output Blocks IP - Internal Protocol LUT - Look up Table MD4 - Message Digest 4 MD5 - Message Digest 5 MIMO - Multiple Input Multiple Output NIST - National Institute of Standards and Technology NSA - National Security Agency OFDMA - Orthogonal Frequency Division Multiple Access PDA - Personal Digital Assistants PKC - Public key Certificate RSA RISC - Reduced Instruction Set Computing processor RSA - Rivest Shamir Adelmen SCA - Software Communication Architecture SDR - Software-Defined Radio SHA-1 - Secure Hash Algorithm-1 SHA-192 - Secure Hash Algorithm-192 SP-network - Substitution Permutation network TDMA - Time Division Multiple Access VHDL - Very High Speed Integrated Circuit Hardware Description Language VLSI - Very Large Scale Integrated circuit WAP - Wireless Application Protocol WPAN - Wireless Personal Area Networks WLAN - Wireless Local Area Networks WMAN - Wireless Metro Area Network WWAN - Wireless Wide Area Networks WCDMA - Wireless Code Division Multiple Access