Readings, exercises: Chapter 11 (Due: 10/4) Homework keys Study group(s) Prelim 1 10/6!

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Homework Readings, exercises: Chapter 11 (Due: 10/4) Homework keys Study group(s) Prelim 1 10/6! Copyright c 2002 2017 UMaine School of Computing and Information S 1 / 20

COS 140: Foundations of : Daisy Chain Buses Fall 2017 Copyright c 2002 2017 UMaine School of Computing and Information S 2 / 20

The problem The problem What is a Bus? Memory the I/O Module the CPU Interrupts Some Bus Terminology Need to get information from one component to another Components can be: functional units inside the CPU CPU and memory CPU/memory and I/O devices Maybe too expensive/impractical to have point-to-point communication How to have devices share communication pathways? Copyright c 2002 2017 UMaine School of Computing and Information S 3 / 20

The problem The problem What is a Bus? Memory the I/O Module the CPU Interrupts Some Bus Terminology Need to get information from one component to another Components can be: functional units inside the CPU CPU and memory CPU/memory and I/O devices Maybe too expensive/impractical to have point-to-point communication How to have devices share communication pathways? Use a communication bus Copyright c 2002 2017 UMaine School of Computing and Information S 3 / 20

What is a Bus? The problem What is a Bus? Memory the I/O Module the CPU Interrupts Some Bus Terminology The method of communication between components of the architecture. Multiple lines. Each line sends a 1 or 0. Lines are grouped together and bits are sent in parallel. Multiple devices can send and receive. No privacy. If all devices send, have a garbled message. Copyright c 2002 2017 UMaine School of Computing and Information S 4 / 20

Communication with Memory The problem What is a Bus? Memory the I/O Module the CPU Interrupts Some Bus Terminology words of data read or written to memory address of word control to specify read or write Copyright c 2002 2017 UMaine School of Computing and Information S 5 / 20

Communication with the I/O Module The problem What is a Bus? Memory the I/O Module the CPU Interrupts Some Bus Terminology data address read or write control select for a particular I/O device interrupt CPU Copyright c 2002 2017 UMaine School of Computing and Information S 6 / 20

Communication with the CPU The problem What is a Bus? Memory the I/O Module the CPU Interrupts Some Bus Terminology read instructions read and write data control signals to make system work handle interrupts Copyright c 2002 2017 UMaine School of Computing and Information S 7 / 20

Interrupts The problem What is a Bus? Memory the I/O Module the CPU Interrupts Some Bus Terminology Interrupts alert CPU to something important that has happened CPU does not have to constantly check for each potential situation. Devices put a 1 on an interrupt line to signal interrupt CPU checks for interrupts at specific points in its functioning. If it finds an interrupt, it suspends what it is doing (e.g., the user s program) to handle the interrupt. When the interrupt has been handled, the CPU returns to what it was doing before the interrupt was discovered. Copyright c 2002 2017 UMaine School of Computing and Information S 8 / 20

Some Bus Terminology The problem What is a Bus? Memory the I/O Module the CPU Interrupts Some Bus Terminology System bus: connects memory, CPU and I/O Bus width: number of lines Assert: put information on a line Negate: remove information from a line Copyright c 2002 2017 UMaine School of Computing and Information S 9 / 20

Centralized Arbitration Decentralized Arbitration No physical reason why all devices on the bus can t use the bus at the same time If more than one device tries to send information on the bus at once: information garbled Bus arbitration: controls which device will get the bus. Many schemes for bus arbitration for each all devices have to follow the rules do not send information unless they have permission Copyright c 2002 2017 UMaine School of Computing and Information S 10 / 20

Centralized Arbitration Centralized Arbitration Decentralized Arbitration One arbiter makes choice and informs devices on bus. Advantage: Can use very simple scheme to select which device will have control. Devices do not have to put any resources toward arbitration. Disadvantages: Cost of arbiter. Single point of failure at arbiter. If arbiter goes down, can t use the bus. Copyright c 2002 2017 UMaine School of Computing and Information S 11 / 20

Decentralized Arbitration Centralized Arbitration Decentralized Arbitration All devices participate in selecting which device will control the bus next. Advantages: Less costly because do not have to have an arbiter. If a device goes down, can continue to use bus. Disadvantage: Schemes are more complicated than those for centralized arbitration. Copyright c 2002 2017 UMaine School of Computing and Information S 12 / 20

Daisy Chaining Architecture Issues Priorities Arbiter Device 1 Device 2 Device 3 Release Line The bus has additional control lines: grant, request, and release Copyright c 2002 2017 UMaine School of Computing and Information S 13 / 20

Daisy Chaining Architecture Issues Priorities Arbiter Device 1 Device 2 Device 3 Release Line When a device wants the bus it asserts its request line Copyright c 2002 2017 UMaine School of Computing and Information S 13 / 20

Daisy Chaining Architecture Issues Priorities Arbiter Device 1 Device 2 Device 3 Release Line The arbiter senses the request, then it asserts the grant line Copyright c 2002 2017 UMaine School of Computing and Information S 13 / 20

Daisy Chaining Architecture Issues Priorities Arbiter Device 1 Device 2 Device 3 Release Line If a node (a bus master) receives the grant line, but hasn t requested the bus, it passes it through Copyright c 2002 2017 UMaine School of Computing and Information S 13 / 20

Daisy Chaining Architecture Issues Priorities Arbiter Device 1 Device 2 Device 3 Release Line When the node requesting the bus gets the grant line, it can start using the bus Copyright c 2002 2017 UMaine School of Computing and Information S 13 / 20

Daisy Chaining Architecture Issues Priorities Arbiter Device 1 Device 2 Device 3 Release Line When the node is done with the bus, it releases the request line Copyright c 2002 2017 UMaine School of Computing and Information S 13 / 20

Daisy Chaining Architecture Issues Priorities Arbiter Device 1 Device 2 Device 3 Release Line It then tells the arbiter it s done by raising the release line Copyright c 2002 2017 UMaine School of Computing and Information S 13 / 20

Daisy Chaining Architecture Issues Priorities Arbiter Device 1 Device 2 Device 3 Release Line The arbiter then drops the grant line Copyright c 2002 2017 UMaine School of Computing and Information S 13 / 20

Daisy Chaining Architecture Issues Priorities Arbiter Device 1 Device 2 Device 3 Release Line At this point, it s back to the initial state Copyright c 2002 2017 UMaine School of Computing and Information S 13 / 20

Daisy Chaining Architecture Issues Priorities Arbiter Device 1 Device 2 Device 3 Release Line Now another device can request the bus Copyright c 2002 2017 UMaine School of Computing and Information S 13 / 20

Daisy Chaining Issues Issues Priorities Arbiter Device 1 Device 2 Device 3 Release Line How do devices know that the bus is busy and they can t take control? Which device most often gets control of the bus? Do you think that s fair? Can one device suffer from starvation never getting any resources? Copyright c 2002 2017 UMaine School of Computing and Information S 14 / 20

Adding Priorities to Daisy Chaining Issues Priorities Arbiter Device 1 Device 1 Device 2 Device 3 Device 2 Device 3 Highest Priority Can add request and grant lines to create priorities. Devices are assigned priorities and make requests and seek grants of the bus from the lines for their priorities. Can have several priority levels. Device 1 Device 2 Device 3 Lowest Priority The arbiter has to assert the grant line corresponding to the highest priority request line that is asserted. For each priority level, arbitration works the same way for the device. Copyright c 2002 2017 UMaine School of Computing and Information S 15 / 20

Hidden Arbitration Hidden arbitration In current scheme, arbitration occurs when the bus is available. Data is not sent when arbitration is going on. Less data sent over the bus waste time on arbitration. Hidden arbitration means that arbitration takes place while the bus is being used, so arbitration is hidden from the bus usage. Copyright c 2002 2017 UMaine School of Computing and Information S 16 / 20

Hidden Arbitration in Daisy Chaining Hidden arbitration Arbiter ACK Device 1 Device 2 Device 3 Bus The device that controls the bus is chosen in the same way as with regular daisy chaining. Copyright c 2002 2017 UMaine School of Computing and Information S 17 / 20

Hidden Arbitration in Daisy Chaining Hidden arbitration Arbiter ACK Device 1 Device 2 Device 3 Bus The device that controls the bus is chosen in the same way as with regular daisy chaining. When a device takes control of the bus, it asserts an acknowledgment (ACK) line, which is noticed by arbiter Copyright c 2002 2017 UMaine School of Computing and Information S 17 / 20

Hidden Arbitration in Daisy Chaining Hidden arbitration Arbiter ACK Device 1 Device 2 Device 3 Bus The device that controls the bus is chosen in the same way as with regular daisy chaining. When a device takes control of the bus, it asserts an acknowledgment (ACK) line, which is noticed by arbiter The arbiter then negates the grant line Copyright c 2002 2017 UMaine School of Computing and Information S 17 / 20

Hidden Arbitration in Daisy Chaining Hidden arbitration Arbiter ACK Device 1 Device 2 Device 3 Bus Once grant line is negated... Copyright c 2002 2017 UMaine School of Computing and Information S 18 / 20

Hidden Arbitration in Daisy Chaining Arbiter Hidden arbitration ACK Device 1 Device 2 Device 3 Bus Once grant line is negated... Others may request bus... Copyright c 2002 2017 UMaine School of Computing and Information S 18 / 20

Hidden Arbitration in Daisy Chaining Hidden arbitration Arbiter ACK Device 1 Device 2 Device 3 Bus Once grant line is negated... Others may request bus...and are selected in the usual way Copyright c 2002 2017 UMaine School of Computing and Information S 18 / 20

Hidden Arbitration in Daisy Chaining Hidden arbitration Arbiter ACK Device 1 Device 2 Device 3 Bus Once grant line is negated... Others may request bus...and are selected in the usual way When the first device is finished, it negates ACK line Copyright c 2002 2017 UMaine School of Computing and Information S 18 / 20

Hidden Arbitration in Daisy Chaining Hidden arbitration Arbiter ACK Device 1 Device 2 Device 3 Bus Once grant line is negated... Others may request bus...and are selected in the usual way When the first device is finished, it negates ACK line Next device starts using bus as soon as ACK negated Copyright c 2002 2017 UMaine School of Computing and Information S 18 / 20

Hidden Arbitration in Daisy Chaining Hidden arbitration Arbiter ACK Device 1 Device 2 Device 3 Bus Once grant line is negated... Others may request bus...and are selected in the usual way When the first device is finished, it negates ACK line Next device starts using bus as soon as ACK negated Copyright c 2002 2017 UMaine School of Computing and Information S 18 / 20

Chain The arbiter is replaced with an asserted grant line. Add a busy line to show when bus is busy and cannot change grant line. Take control of bus as with centralized daisy chain (with addition of busy line). Copyright c 2002 2017 UMaine School of Computing and Information S 19 / 20

Decentralized 1 Busy Line Device 1 Device 2 Device 3 Bus Initially, grant line passed throughout chain Copyright c 2002 2017 UMaine School of Computing and Information S 20 / 20

Decentralized 1 Busy Line Device 1 Device 2 Device 3 Bus When device wants bus and busy negated, negate grant line, assert busy Copyright c 2002 2017 UMaine School of Computing and Information S 20 / 20

Decentralized 1 Busy Line Device 1 Device 2 Device 3 Bus Takes control of bus Copyright c 2002 2017 UMaine School of Computing and Information S 20 / 20

Decentralized 1 Busy Line Device 1 Device 2 Device 3 Bus If another wants bus, senses busy, waits Copyright c 2002 2017 UMaine School of Computing and Information S 20 / 20

Decentralized 1 Busy Line Device 1 Device 2 Device 3 Bus When finished, negates busy Copyright c 2002 2017 UMaine School of Computing and Information S 20 / 20

Decentralized 1 Busy Line Device 1 Device 2 Device 3 Bus Device wanting bus now notices busy negated, asserts it and negates grant downstream Copyright c 2002 2017 UMaine School of Computing and Information S 20 / 20

Decentralized 1 Busy Line Device 1 Device 2 Device 3 Bus Device begins using bus Copyright c 2002 2017 UMaine School of Computing and Information S 20 / 20

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