Topics! SRAM-based FPGA fabrics:! Xilinx.! Altera. SRAM-based FPGAs! Program logic functions, using SRAM.! Advantages:! Re-programmable;! dynamically reconfigurable;! uses standard processes.! isadvantages:! SRAM burns power.! Possible to steal, disrupt configuration bits. Logic elements LUT-based logic element! Logic element includes combinational function + register(s). inputs n! Use SRAM as for combinational function. Lookup configuration bits 1 Can multiplex at put or address at input Example 111 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0, 01 0 1 Evaluation of SRAM-based LUT! N-input LUT can handle function of 2 n inputs.! All logic functions take the same amount of space.! All functions have the same delay.! SRAM is larger than static gate equivalent of function.! Burns power at idle.! Want to selectively add register to :
Registers in logic elements! Register may be selected into the circuit: Configuration bit Other features! Multiple logic functions in an.! Addition logic:! carry chain.! Partitioned s. LUT COUT F5IN YB Xilinx Spartan-II CLB! Each CLB has two identical slices.! Slice has two logic cells:! LUT.! Carry logic.! Registers. G4 G3 G2 G1 BY SR F4 F3 F2 F1 carry/ control logic carry/ control logic Y Y YB Y Y BX CE CLK CIN Spartan-II CLB details! Each can be used as a 16-bit synchronous RAM or 16-bit shift register.! Arithmetic logic includes an XOR gate.! Each slice includes a mux to ocmbine the results of the two functino generators in the slice.! Register can be configured as FF or latch.! Has three-state drivers (BUFTs) for on-chip busses. Spartan-II CLB operation! Arithmetic:! Carry block includes XOR gate.! Use LUT for carry, XOR for sum.! Each slice uses F5 mux to combine results of multiplexers.! F6 mux combines puts of F5 muxes.! Registers can be FF/latch; clock and clock enable.! Includes three-state put for on-chip bus.
carry in cascade in load clear Altera APEX II logic element! Each logic array block has 10 logic elements.! Logic elements share some logic. data3 data4 carry chain cascade chain synchronous load/clear logic labclr1 labclr2 asynchronous clear/preset/ load logic chip reset labclk1 labclk2 labclkena1 labclkena2 Apex II modes APEX-II normal mode! Modes of operation:! Normal.! Arithmetic.! Counter. data3 data4 carry in 4-input cascade in enable cascade APEX-II arithmetic mode APEX-II counter mode carry in cascade in enable carry in synchronous load synchronous clear cascade in enable cascade data3 cascade carry carry
dedicated clocks fast global signals APEX-II control logic Programmable! MOS switch controlled by configuration bit: Programmable vs. fixed! Switch adds delay.! Transistor off-state is worse in advanced technologies.! FPGA has extra length = added capacitance. Interconnect strategies! Some wires will not be utilized.! Congestion will not be same through chip.! Types of wires:! Short wires: connections.! Global wires: long-distance, buffered communication.! Special wires: clocks, etc. Paths in! Connection may be long, complex: Interconnect architecture! Connections from wiring s to s.! Connections between wires in the wiring s. Wiring
Interconnect richness Switchbox! Within a :! How many wires.! Length of segments.! Connections from to.! Between s:! Number of connections between s.! Channel structure. Spartan-II! Types of :! ;! general-purpose;! dedicated;! I/O pin. Spartan-II general-purpose network! Provides majority of ring resources:! General ring matrix (GRM) connects horizontal/vertical s and CLBs.! Interconnect between adjacent GRMs.! Hex lines connect GRM to GRMs six blocks away.! 12 longlines span the chip. Spartan-II ring! Relationship between GRM, hex lines, and : Spartan-II three-state bus! Horizontal on-chip busses: CLB CLB
Spartan-II clock distribution APEX II clock pin row clock rows clock rows column MegaLAB row clock rows clock spine column column Spartan-II I/O Spartan-II I/O block diagram! Supports multiple I/O standards:! LVTTL, PCI, LVCMOS2, AGP2X, etc.! Provides registers.! Programmable delay for pin-dependent hold time.! Programmable weak keeper circuit. Configuration Configuration ROM! Need to set all configuration SRAM bits:! minimum pin cost;! reasonable speed.! Configure SRAM as shift register to read configuration bits.! Configuration can also be read back for testing.! Configured on start-up from ROM: FPGA Configuration memory
Spartan-II configuration! Configuration length depends on size of chip:! 200,000 to 1.3 million bits.! Configuration modes:! Master serial for first chip in chain.! Slave serial for follow-on chips.! Slave parallel.! Boundary-scan. Scan chain! Scan chain: shift register used to access internal state.! Logic-sensitive scan design (LSS): scan structure that uses some hardware for normal mode and scan. JTAG boundary scan Chip-on-board testing! JTAG: Joint Test Action Group.! Boundary scan decouples chips:! Boundary scan:! provide scan chain at pins;! allow control of chip interior;! decouple chip from rest of board for test. board Boundary scan concepts! TAP: test access port.! Requires three pins not shared with other logic.! Test reset, test clock, test mode select, test data in, test data.! TAP controller recognizes pins, controls boundary scan registers.! Instruction register defines boundary scan mode.