NAND Flash Architecture and Specification Trends Michael Abraham (mabraham@micron.com) NAND Solutions Group Architect Micron Technology, Inc. August 2011 1
Topics NAND Flash trends SSD/Enterprise application requirements A look to the future August 2011 3
60 50 NAND Process Migration: Shrinking Faster than Moore s Law 50nm Class Process Node (nm) 40 30 20 20nm Class 30nm Class 10 Q1-07 Q2-07 Q3-07 Q4-07 Q1-08 Q2-08 Q3-08 Q4-08 Q1-09 Q2-09 Q3-09 Q4-09 Q1-10 Q2-10 Q3-10 Q4-10 Q1-11 Q2-11 Q3-11 Q4-11 Q1-12 Volume Production Dates Company A Company B Company C Company D August 2011 4 Data based on publicly available information
Memory Organization Trends NAND block size is increasing Larger page sizes and more planes increase sequential throughput More pages per block reduce die size 8388608 2097152 524288 131072 32768 8192 2048 512 128 32 8 Block size (B) Data Bytes per Operation Pages per Block August 2011 5
Consumer-Grade NAND Flash: Endurance and ECC Trends Process shrinks lead to fewer electrons per floating gate ECC used to improve data retention and endurance To adjust for increasing RBERs, ECC is increasing exponentially to achieve equivalent UBERs Endurance (cycles) 100,000 10,000 1,000 SLC Endurance MLC-2 Endurance SLC ECC MLC-2 ECC 45 40 35 30 25 20 15 10 5 0 ECC (bits) August 2011 6
Larger Page Sizes Improve Sequential Write Performance For a fixed page size, write throughput decreases as NAND process shrinks NAND vendors increase the page size to compensate for slowing array performance Write throughput decreases with more bits per cell 100.0 80.0 60.0 40.0 20.0 0.0 SLC MLC-2 MLC-3 512 2048 8192 16384 32768 4096 8192 16384 32768 8192 16384 Data Bytes per Operation (Page Size * # of Planes) Sequential Programming Throughput (MB/s) August 2011 7
More Pages Per Block Affect Random Write Performance 1000 800 600 400 200 The block copy time is the largest limiting factor for random write performance As block copy time increases, random performance decreases Number of pages per block is the dominant factor Increase of t PROG is the next largest factor Increase in I/O transfer time due to increasing page size (effect not shown below) is also a factor Some card interfaces have write timeout specs at 250ms, which means that block management algorithms manage partial blocks SLC MLC-2 MLC-3 0 32 / 300 64 / 250 64 / 300 128 / 250 128 / 600 128 / 900 256 / 900 256 / 1200 192 / 2000+ 384 / 2000+ Pages per Block / tprog (typ) Block Copy Time (ms) August 2011 8
NAND Interface Trends Interface Standard (x8) Max Throughput (MT/s) No standard 40 ONFI 1.0 NV-SDR (12/06) 50 ONFI 2.0 NV-DDR (2/08) 133 ONFI 2.1-2.3 NV-DDR (1/09, 9/09, 8/10) 200 Toggle Mode (not yet published) 200 ONFI 3.0 NV-DDR2 (3/11) 400 Toggle Mode 2 (not yet published) 400 August 2011 9
MT/s Single Channel Package 900 800 700 600 500 400 300 200 100 0 NV-SDR The ONFI Advantage Dual Channel Package ONFI 1.0 ONFI 2.0 ONFI 2.x ONFI 3.0 NV-DDR NV-DDR2 Supports simultaneous READ, PROGRAM, and ERASE operations on multiple die on the same chip enable since ONFI 1.0 Only industry-standard NAND interface capable of 400 MT/sec data rate from a single die Two independent channels in a single package (doubles the I/O bandwidth) ONFI 3.0 published and available at onfi.org August 2011 10
SSD/Enterprise vs. Consumer Applications SSD/Enterprise applications are different than typical consumer applications in several ways Higher total system density More throughput required, including in random operations Fixed data sizes for example, database: 4KB or 8KB Higher endurance/reliability requirements More consistent use over time Power within budget for parallel operations August 2011 11
Meeting SSD/Enterprise Application Requirements Application Requirement Higher system density More throughput Controller Ability to handle many NAND Flash some controllers up to 256 die Page-based block management, DRAM cache, Overprovisioning, More I/O channels, Faster I/O channels, Multiple ECC engines, Simultaneous operations SSD/Enterprise-Grade NAND Flash Lower DPM Faster I/O channel August 2011 12
Meeting SSD/Enterprise Application Requirements, Part 2 Application Requirement Higher endurance / reliability More consistent use over time Power within budget for parallel operations Controller Higher ECC Balanced block management to reduce write amplification Block management throttles parallelism as needed SSD/Enterprise-grade NAND Flash More ECC required, Lower UBER, More endurance Peak power reduction August 2011 13
SSD/Enterprise-Grade NAND Flash Higher endurance: achieves higher endurance than consumer-grade NAND Flash Lower data retention at max endurance No change to data retention at time 0 Enterprise applications tend to use NAND more consistently over its lifetime, so data retention at max cycling becomes less important and is reduced August 2011 14
SSD/Enterprise-Grade NAND Flash, Part 2 ECC tuned for lower UBER Providing more ECC to a consumer-grade NAND Flash does not necessarily improve endurance SSD/Enterprise-grade NAND Flash is tuned to improve endurance while reducing UBER, requiring more ECC Modest performance NAND array performance is modestly slower than consumer-grade NAND Flash Controller helps achieve better system throughput through more channels, faster interface speeds, overprovisioning, higher parallelism August 2011 15
SSD/Enterprise-Grade NAND Flash, Part 3 Fast I/O interface Allows better utilization of I/O channels higher bandwidth Immediately useful for single die read performance Modest improvement for write performance with multiple die Reduces I/O channels required on controller Support 200 MB/s today with 400 MB/s coming August 2011 16
Look to the (Near) Future ECC is going to continue to increase to the point that it will be a significant amount of real estate on a multi-channel controller 1000000 800000 600000 400000 200000 0 Logic Gates BCH (t=16) BCH (t=29) BCH (t=60) RS/TCM LDPC Logic Gates August 2011 17
How to Handle Increasing ECC? ECC is technology dependent and typically requires a new controller to support higher levels Block management and drivers aren t technology dependent and can be updated in software/firmware Solution: Move ECC to the NAND package and tightly coupled to the underlying NAND technology Also covers NAND aggregation, reducing channel loading Other benefits In package data copying Volume addressing allows multiple CE#s to be combined into one For more benefits, see System Benefits of EZNAND/Enhanced ClearNAND Flash by Carla Lay in Session 305 on Thursday at 9:50 AM August 2011 18
Questions? Revisit the Micron FMS presentations at www.micron.com/fms August 2011 19
About Michael Abraham Architect in the NAND Solutions Group at Micron Covers advanced NAND and PCM interfaces and system solutions BS degree in Computer Engineering from Brigham Young University 2011 Micron Technology, Inc. All rights reserved. Products are warranted only to meet Micron s production data sheet specifications. Information, products and/or specifications are subject to change without notice. All information is provided on an AS IS basis without warranties of any kind. Dates are estimates only. Drawings not to scale. Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. August 2011 20