Section 31. Instruction Set

31 HIGHLIGHTS Section 31. Instruction Set Instruction Set This section of the manual contains the following major topics: 31.1 Introduction... 31-2 31.2 Data Memory Map... 31-3 31.3 Instruction Formats... 31-9 31.4 Special Function Registers as Source/Destination... 31-12 31.5 Fast Register Stack... 31-13 31.6 Q Cycle Activity... 31-13 31.7 Instruction Descriptions... 31-14 31.8 Design Tips... 31-136 31.9 Related Application tes... 31-137 31.10 Revision History... 31-138 2000 Microchip Technology Inc. DS39532A-page 31-1

PIC18C Reference Manual 31.1 Introduction The PIC18CXXX instruction set adds many enhancements to the previous PICmicro instruction sets, while maintaining an easy migration from these PICmicro instruction sets. Most instructions are a single program memory word (16-bits), but to address customer requests, some new instructions have been added that require two program memory locations. The Instruction Set Summary, shown in Table 31-1, lists the instructions recognized by the Microchip assembler (MPASM). Table 31-2 gives the instruction description conventions. Each instruction is divided into an OPCODE that specifies the instruction type and one or more operands which further specify the of the instruction. The instruction set is highly orthogonal and is grouped into four basic categories: Byte-oriented s Bit-oriented s Literal s Control s Most byte-oriented instructions have three operands: 1. The File Register (specified by the value of f ) 2. The destination of the result (specified by the value of d ) 3. The accessed memory (specified by the value of a ) 'f' represents a File Register Designator and 'd' represents a Destination Designator. The File Register Designator specifies which File Register is to be used by the instruction. The access indicator a specifies if the BSR selects the bank or if the access bank is used. The destination designator specifies where the result of the is to be placed. If 'd' is zero, the result is placed in the WREG Register. If 'd' is one, the result is placed in the File Register specified in the instruction. All bit-oriented instructions have three operands: 1. The File Register (specified by the value of f ) 2. The bit in the File Register (specified by the value of b ) 3. The accessed memory (specified by the value of a ) 'b' represents a bit field designator that selects the number of the bit affected by the, while 'f' represents the number of the file in which the bit is located. The access indicator a specifies if the BSR selects the bank or if the access bank is used. The literal instructions may use some of the following operands: A literal value to be loaded into a File Register (specified by the value of k ) The desired FSR Register to load the literal value into (specified by the value of f ) operand required (specified by the value of ) The control instructions may use some of the following operands: A program memory address (specified by the value of n ) The mode of the CALL or RETURN instructions (specified by the value of s ) The mode of the Table Read and Table Write instructions (specified by the value of m ) operand required (specified by the value of ) All instructions are a single word except for three double word instructions. These three instructions were made double word instructions so that all the required information is available in these 32 bits. In the second word, the 4-MSb s, are 1 s. If this second word is executed as an instruction (by itself), it will execute as a NOP. All single word instructions are executed in a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of the instruction. In these cases, the execution takes two instruction cycles with the additional instruction cycle(s) executed as a NOP. The double word instructions (that do not modify the PC) execute in two instruction cycles. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 µs. If a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 µs. Two word branch instructions (if true) would take 3 µs. DS39532A-page 31-2 2000 Microchip Technology Inc.

31.2 Data Memory Map Section 31. Instruction Set The Data Memory Map has 16 banks of 256 bytes. The Instruction Set and architecture allows s across all banks (such as MOVFF). A Segment of Bank 0 and a segment of Bank 15 comprise the access bank. See Section 31.2.1 for description of the access bank. Figure 31-1: The Data Memory Map and the Access Bank BSR<3:0> = 0000b Data Memory Map Segment 0 Bank 0 00h 31 Instruction Set = 0001b Bank 1 Bank n Access Bank Segment 0 Segment 1 00h FFh Device Dependent Segment Boundary = 1110b = 1111b Bank 14 Bank 15 Segment 1 FFh When the instructions a bit = 0, The BSR is ignored and this Access Bank is used. The Segment 0 General Purpose RAM is from Bank 0. The Segment 1 Special Function Registers is from Bank 15. Whena=1, the BSR is used to specify the RAM location that the instruction uses. 31.2.1 Access Bank The access bank is an architectural enhancement that is very useful for C compiler code optimization. The techniques used by the C compiler may also be useful for programs written in assembly. This memory region can be used for Intermediate computational values Local variables of subroutine Faster context saving/switching of variables Common variables Faster evaluation/control of SFRs (no banking) The access bank is comprised of 2 segments: Segment 0 and Segment 1. Segment 0 is the RAM that is mapped in Bank 0. Segment 1 is the SFRs that are mapped in Bank 15. Each Segment can be of different sizes. The sum of RAM mapped by Segment 0 and Segment 1 is 256 bytes. When forced in the access bank (a = 0 ), the last address in Segment 0 is followed by the first address in Segment 1. Segment 1 maps the Special Function Registers so that these registers can be accessed without any software overhead. This is useful for testing status flags and modifying control bits. 2000 Microchip Technology Inc. DS39532A-page 31-3

PIC18C Reference Manual Example 31-1 shows how registers are affected depending on the value of the access bit. Register MYREG has an 8-bit address. This address specifies the location in the specified bank to perform the. The specified bank is either the bank specified by the Bank Select Register (BSR) (when a = 1), or the access bank (when a = 0). Example 31-1:Operation of Destination and Access Bits ; ; The following symbols are defined in the Microchip supplied ; device header file: ; ; For destination bit: ; F = 1 ; Result is placed in File Register ; W = 0 ; Result is placed in WREG Register ; ; For access bit: ; B = 1 ; Register used specified by BSR Bank Register ; A = 0 ; Register used is in Access Bank ; ; MYREG is a register with an 8-bit address value between 0h and FFh. ; For this example we will assign MYREG to bank 5, though it could ; be in any (or all) banks. ; MOVLB 5 ; BSR points to RAM bank 5 ; ; Contents of ; Addr(MYREG) in ; MYREG access bank WREG ; Starting Value 0x7F 0x5A x ; DECF MYREG, F, B ; 0x7E --- --- DECF MYREG, F, A ; --- 0x59 --- ; DECF MYREG, W, B ; --- --- 0x7D DECF MYREG, W, A ; --- --- 0x58 te: If the register is specified with the full 12-bit address, the assembler will automatically force the access bit to a 0 (when the address is in the access RAM area) or a 1 (for all other addresses). DS39532A-page 31-4 2000 Microchip Technology Inc.

Section 31. Instruction Set The common assembler usage should be that all RAM and SFR addresses are 12-bit. This means that the assembler can determine from the address of the register, whether the access bit needs to be set or cleared. Example 31-2 shows this, as well as forcing the use of the access bank. Example 31-2:Code ; ; The following symbols are defined in the Microchip supplied ; device header file: ; ; For destination bit: ; F = 1 ; Result is placed in File Register ; W = 0 ; Result is placed in WREG Register ; ; For access bit: ; B = 1 ; Register used specified by BSR Bank Register ; A = 0 ; Register used is in Access Bank ; ; Register Name Address ; Loop_CNTR 0x000 ; MYREG 0x524 ; SFR1 0xA9F ; MOVLB 5 ; BSR points to RAM bank 5 ; Addr 24 ; a-bit MYREG Loop_CNTR SFR1 WREG Bank0 ; Starting Value --- 0x7F 0x7F 0x7F x 0xA9 ; DECF Loop_CNTR, F ; 0 --- 0x7E --- --- --- DECF MYREG, F ; 1 0x7E --- --- --- --- DECF SFR1, F ; 0 --- --- 0x7E --- --- ; ; DECF Loop_CNTR, W ; 0 --- --- --- 0x7D --- DECF MYREG, W ; 1 --- --- --- 0x7D --- DECF SFR1, W ; 0 --- --- --- 0x7D --- 31 Instruction Set INCF MYREG, F, A ; 0 --- --- --- --- 0xAA INCF MYREG, W, A ; 0 --- --- --- 0x7F --- 2000 Microchip Technology Inc. DS39532A-page 31-5

PIC18C Reference Manual Table 31-1: PIC18CXXX Instruction Set Summary Mnemonic, Operands Description BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ADDWFC ANDWF CLRF COMF CPFSEQ CPFSGT CPFSLT DECF DECFSZ DCFSNZ INCF INCFSZ INFSNZ IORWF MOVF MOVFF MOVWF MULWF NEGF RLCF RLNCF RRCF RRNCF SETF SUBFWB SUBWF SUBWFB SWAPF TSTFSZ XORWF f, d, a f, d, a f, d, a f, a f, d, a f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f s,f d f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, a f, d, a f, d, a f, d, a f, d, a f, a f, d, a Add WREG and f Add WREG and Carry bit to f AND WREG with f Clear f Complement f Compare f with WREG, skip = Compare f with WREG, skip > Compare f with WREG, skip < Decrement f Decrement f, Skip if 0 Decrement f, Skip if t 0 Increment f Increment f, Skip if 0 Increment f, Skip if t 0 Inclusive OR WREG with f Move f Move f s (source) to 1st word f d (destination) 2nd word Move WREG to f Multiply WREG with f Negate f Rotate Left f through Carry Rotate Left f ( Carry) Rotate Right f through Carry Rotate Right f ( Carry) Set f Subtract f from WREG with borrow Subtract WREG from f Subtract WREG from f with borrow Swap nibbles in f Test f, skip if 0 ExclusiveORWREGwithf BIT-ORIENTED FILE REGISTER OPERATIONS BCF BSF BTFSC BTFSS BTG f, b, a f, b, a f, b, a f, b, a f, d, a Bit Clear f Bit Set f BitTestf,SkipifClear BitTestf,SkipifSet Bit Toggle f Cycles 1 1 1 1 1 1(2or3) 1(2or3) 1(2or3) 1 1(2or3) 1(2or3) 1 1(2or3) 1(2or3) 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1(2or3) 1 1 1 1(2or3) 1(2or3) 1 16-Bit Instruction Word MSb 0010 0010 0001 0110 0001 0110 0110 0110 0000 0010 0100 0010 0011 0100 0001 0101 1100 1111 0110 0000 0110 0011 0100 0011 0100 0110 0101 0101 0101 0011 0110 0001 1001 1000 1011 1010 0111 01da 00da 01da 101a 11da 001a 010a 000a 01da 11da 11da 10da 11da 10da 00da 00da 111a 001a 110a 01da 01da 00da 00da 100a 01da 11da 10da 10da 011a 10da bbba bbba bbba bbba bbba LSb Status Affected C,DC,Z,OV,N C,DC,Z,OV,N Z, N Z Z, N ne ne ne C,DC,Z,OV,N ne ne C,DC,Z,OV,N ne ne Z, N Z, N ne ne ne C,DC,Z,OV,N C, Z, N Z, N C, Z, N Z, N ne C,DC,Z,OV,N C,DC,Z,OV,N C,DC,Z,OV,N ne ne Z, N ne ne ne ne ne tes 1, 2, 3 1, 2, 3 1,2, 3 2, 3 1, 2, 3 4 4 2 1, 2, 3, 4 1, 2, 3, 4 1, 2 1, 2, 3, 4 1, 2, 4 1, 2 1, 2 1, 2 2 2 1, 2 1, 2 1, 2 1, 2 1, 2 2 1, 2 1, 2 1, 2 1, 2, 4 2 te 1: When a PORT Register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the latch is '1' for a pin configured as input and is driven low by an external device, the will be written back with a '0'. 2: If this instruction is executed on the TMR0 Register (and, where applicable, d = 1), the prescaler will be cleared if assigned. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are 2 word instructions. The second word of these instructions will be executed as a NOP, unless the first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all program memory locations have a valid instruction. 5: If the table write starts the write cycle to internal program memory, the write continues until terminated. 1, 2 1, 2 3, 4 3, 4 1, 2 DS39532A-page 31-6 2000 Microchip Technology Inc.

Table 31-1: Mnemonic, Operands CONTROL OPERATIONS BC BN BNC BNN BNOV BNZ BOV BRA BZ CALL CLRWDT DAW GOTO NOP NOP POP PUSH RCALL RESET RETFIE RETLW RETURN SLEEP n n n n n n n n n n, s n n s k s Branch if Carry Branch if Negative Branch if t Carry Branch if t Negative Branch if t Overflow Branch if t Zero Branch if Overflow Branch Unconditionally Branch if Zero Call subroutine 1st word 2nd word Clear Watchdog Timer Decimal Adjust WREG Go to address 1st word 2nd word Operation Operation Pop top of return stack (TOS) Push top of return stack (TOS) Relative Call Software device RESET Return from interrupt enable Section 31. Instruction Set PIC18CXXX Instruction Set Summary (Continued) Description Return with literal in WREG Return from Subroutine Go into standby mode 1(2) 1(2) 1(2) 1(2) 1(2) 1(2) 1(2) 2 1(2) 2 1 1 2 1 1 1 1 2 1 2 2 2 1 Cycles 16-Bit Instruction Word 1110 1110 1110 1110 1110 1110 1110 1101 1110 1110 1111 0000 0000 1110 1111 0000 1111 0000 0000 1101 0000 0000 0000 0000 0000 0010 0110 0011 0111 0101 0001 0100 0nnn 0000 110s kkkk 0000 0000 1111 kkkk 0000 xxxx 0000 0000 1nnn 0000 0000 1100 0000 0000 nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0000 0000 kkkk kkkk 0000 xxxx 0000 0000 nnnn 1111 0001 kkkk 0001 0000 nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0100 0111 kkkk kkkk 0000 xxxx 0110 0101 nnnn 1111 000s kkkk 001s 0011 ne ne ne ne ne ne ne ne ne ne Status Affected TO, PD C ne ne ne ne ne ne All GIE/GIEH, PEIE/GIEL ne ne TO, PD 4 tes te 1: When a PORT Register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the latch is '1' for a pin configured as input and is driven low by an external device, the will be written back with a '0'. 2: If this instruction is executed on the TMR0 Register (and, where applicable, d = 1), the prescaler will be cleared if assigned. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are 2 word instructions. The second word of these instructions will be executed as a NOP, unless the first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all program memory locations have a valid instruction. 5: If the table write starts the write cycle to internal program memory, the write continues until terminated. MSb LSb 31 Instruction Set 2000 Microchip Technology Inc. DS39532A-page 31-7

PIC18C Reference Manual Table 31-1: PIC18CXXX Instruction Set Summary (Continued) Mnemonic, Operands LITERAL OPERATIONS ADDLW ANDLW IORLW LFSR MOVLB MOVLW MULLW RETLW SUBLW XORLW k k k f, k k k k k k k Add literal and WREG AND literal with WREG Inclusive OR literal with WREG Move literal (12-bit) 1st word to FSRx 2nd word Move literal to BSR<3:0> Move literal to WREG Multiply literal with WREG Return with literal in WREG Subtract WREG from literal Exclusive OR literal with WREG DATA MEMORY PROGRAM MEMORY OPERATIONS TBLRD* TBLRD*+ TBLRD*- TBLRD+* TBLWT* TBLWT*+ TBLWT*- TBLWT+* Description Table Read Table Read with post-increment Table Read with post-decrement Table Read with pre-increment Table Write Table Write with post-increment Table Write with post-decrement Table Write with pre-increment 1 1 1 2 1 1 1 2 1 1 Cycles 2 2 2 2 2 (5) 2 (5) 2 (5) 2 (5) 16-Bit Instruction Word 0000 0000 0000 1110 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1111 1011 1001 1110 0000 0001 1110 1101 1100 1000 1010 0000 0000 0000 0000 0000 0000 0000 0000 kkkk kkkk kkkk 00ff kkkk 0000 kkkk kkkk kkkk kkkk kkkk 0000 0000 0000 0000 0000 0000 0000 0000 kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk 1000 1001 1010 1011 1100 1101 1110 1111 C,DC,Z,OV,N Z, N Z, N ne ne ne ne ne C,DC,Z,OV,N Z, N ne ne ne ne ne ne ne ne Status Affected tes te 1: When a PORT Register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the latch is '1' for a pin configured as input and is driven low by an external device, the will be written back with a '0'. 2: If this instruction is executed on the TMR0 Register (and, where applicable, d = 1), the prescaler will be cleared if assigned. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are 2 word instructions. The second word of these instructions will be executed as a NOP, unless the first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all program memory locations have a valid instruction. 5: If the table write starts the write cycle to internal program memory, the write continues until terminated. MSb LSb DS39532A-page 31-8 2000 Microchip Technology Inc.

31.3 Instruction Formats Section 31. Instruction Set Figure 31-2 shows the three general formats that the instructions can have. As can be seen from the general format of the instructions, the opcode portion of the instruction word varies from 3-bits to 6-bits of information. This is what allows the Enhanced Instruction Set to have 75 instructions. te: Any unused opcode is Reserved. Use of any reserved opcode may cause unexpected. All instruction examples use the following format to represent a hexadecimal number: 0xhh where h signifies a hexadecimal digit. To represent a binary number: 00000100b where b is a binary string identifier. Figure 31-2: General Format for Instructions Byte-oriented File Register s 15 10 9 8 7 0 OPCODE d a f (FILE #) d=0forresultdestinationtobewregregister d=1forresultdestinationtobefileregister(f) a = 0 to force Access Bank a=1forbsrtoselectbank f = 8-bit File Register address Example Instruction ADDWF MYREG, W, B 31 Instruction Set Byte to Byte move s (2-word) 15 12 11 0 OPCODE f (Source FILE #) 15 12 11 0 1111 f (Destination FILE #) MOVFF MYREG1, MYREG2 f = 12-bit File Register address Bit-oriented File Register s 15 12 11 9 8 7 0 OPCODE b (BIT #) a f (FILE #) BSF MYREG, bit, B b = 3-bit position of bit in File Register (f) a=0toforceaccessbank a=1forbsrtoselectbank f = 8-bit File Register address Literal s 15 8 7 0 OPCODE k (literal) k = 8-bit immediate value MOVLW 0x7F Control s CALL, GOTO, and Branch s 15 8 7 0 OPCODE n<7:0> (literal) 15 12 11 0 1111 n<19:8> (literal) GOTO label n = 20-bit immediate value 2000 Microchip Technology Inc. DS39532A-page 31-9

PIC18C Reference Manual Table 31-2: Instruction Description Conventions Field a Description RAM access bit a = 0: RAM location in access bank (BSR Register is ignored) a = 1: RAM bank is specified by BSR Register bbb Bit address within an 8-bit File Register (0 to 7) BSR Bank Select Register. Used to select the current RAM bank. d Destination select bit; d = 0: store result in WREG, d = 1: store result in File Register f. dest Destination either the WREG Register or the specified register file location f 8-bit Register file address (0x00 to 0xFF) fs 12-bit Register file address (0x000 to 0xFFF). This is the source address. fd 12-bit Register file address (0x000 to 0xFFF). This is the destination address. k Literal field, constant or label (may be either an 8-bit, 12-bit or a 20-bit value) label Label name mm The mode of the TBLPTR Register for the Table Read and Table Write instructions Only used with Table Read and Table Write instructions: * Change to Register (such as TBLPTR with Table reads and writes) *+ Post-Increment Register (such as TBLPTR with Table reads and writes) *- Post-Decrement Register (such as TBLPTR with Table reads and writes) +* Pre-Increment Register (such as TBLPTR with Table reads and writes) n The relative address (2 s complement number) for relative branch instructions, or the direct address for Call/Branch and Return instructions PRODH Product of Multiply high byte PRODL Product of Multiply low byte s Fast Call / Return mode select bit. s = 0: do not update into/from Shadow Registers s = 1: certain registers loaded into/from Shadow Registers u Unused or Unchanged WREG Working Register (accumulator) x Don'tcare(0or1) The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. TBLPTR 21-bit Table Pointer (points to a Program Memory location) TABLAT 8-bit Table Latch TOS Top of Stack INDF Any one of the indirect addressing registers, such as INDF0, INDF1, or INDF2 FSR Any one of the file select register pairs, such as FSR0H:FSR0L, FSR1H:FSR1L, or FSR2H:FSR2L DS39532A-page 31-10 2000 Microchip Technology Inc.

Table 31-2: Field Section 31. Instruction Set PC Program Counter PCL Program Counter Low Byte PCH Program Counter High Byte PCLATH Program Counter High Byte Latch PCLATU Program Counter Upper Byte Latch GIE Global Interrupt Enable bit WDT Watchdog Timer TO Time-out bit PD Power-down bit C,DC, ALU status bits Carry, Digit Carry, Zero, Overflow, Negative Z,OV,N [ ] Optional ( ) Contents of Assigned to < > Register bit field In the set of italics Instruction Description Conventions (Continued) User defined term (font is courier) Description 31 Instruction Set Table 31-3: Field *FSRn *FSRn++ *FSRn-- *(++FSRn) *(FSRn+W) Indirect Addressing Symbols Description Selects INDFn Register Selects POSTINCn Register Selects POSTDECn Register Selects PREINCn Register Selects PLUSWn Register 2000 Microchip Technology Inc. DS39532A-page 31-11

PIC18C Reference Manual 31.4 Special Function Registers as Source/Destination The Section 31. Instruction Set s Orthogonal Instruction Set allows read and write of all File Registers, including Special Function Registers. The user should be aware of some special situations which are explained in the following subsections. 31.4.1 STATUS Register as Destination 31.4.2 Bit Manipulation If an instruction writes to the STATUS Register, the Z, C, DC, OV, and N bits may be set or cleared as a result of the instruction and overwrite the original bits. For example, executing CLRF STATUS will clear Register STATUS, and then set the Z bit leaving 0000 0100b in the register. All bit manipulation instructions will first read the entire register, operate on the selected bit and then write the result back to (read-modify-write (R-M-W)) the specified register. The user should keep this in mind when operating on some Special Function Registers, such as the Port Pin Register. te: 31.4.3 PCL as Source or Destination Status bits that are manipulated by the device (including the interrupt flag bits) are set or cleared in the Q1 cycle, so there is no issue with executing R-M-W instructions on registers that contain these bits. Read, write or read-modify-write (R-M-W) on PCL may have the following results: Read PCL: PCL destination ; Reading PCL causes the following PCH PCLATH PCU PCLATU Write PCL: 8-bit destination value PCL ; Writing PCL causes the following PCLATH PCH PCLATU PCU Read-Modify-Write: PCL ALU operand ; R-M-W of PCL causes the following PCH PCLATH PCU PCLATU ; PCL is modified 8-bit result PCL ; result is written back to PCL PCLATH PCH PCLATU PCU Where PCH = program counter high byte (not an addressable register), PCLATH = Program counter high holding latch, PCU = program counter upper byte (not an addressable register), PCLATU = Program counter upper holding latch, destination = Register file f. DS39532A-page 31-12 2000 Microchip Technology Inc.

31.5 Fast Register Stack Section 31. Instruction Set At times it is desirable to be able to quickly access and return from a function. This function may be called as a subroutine, or an interrupt routine of the device. To reduce the overhead for accessing/returning from these functions, the architecture has the ability to save three key registers in a one deep Register Stack. These registers are: WREG Register BSR (Bank Select Register) Register STATUS Register The two events that cause these registers to be loaded onto the Fast Register Stack are: Afastcall(CALL K, fast)(where the fast bit is set ( 1 )) Any interrupt occurs These Fast Stack Registers are not accessible for reading or writing. When doing the return from these subroutine, the values can be restored into their registers executing the fast return: RETFIE fast (where the fast bit is set ( 1 )) RETURN fast (where the fast bit is set ( 1 )) When s (fast) = 0, the Fast Register Stack is not used, when s (fast) = 1, the Fast Register Stack is used. 31.6 Q Cycle Activity Each instruction cycle (Tcy) is comprised of four Q clocks (also called Q cycles). These are referred to as Q1, Q2, Q3, or Q4. The Q cycles provide the timing/designation for the Decode, Read, Data, Write etc., of each instruction cycle. The Figure 31-3 shows the relationship of the Q cycles to the instruction cycle. The four Q cycles that make up an instruction cycle (Tcy) can be generalized as: Q1: Instruction Decode Cycle or forced Operation Q2: Instruction Read Cycle or Operation Q3: the Data Q4: Instruction Write Cycle or Operation Some actions occur on the edge between the end of one Q cycle and the start of the next Q cycle. An example would be a Q2-Q3 action. This action occurs on the clock edge between the end of Q2 cycle and the beginning of the Q3 cycle. The clock source for the Q cycle is normally the device oscillator clock (TOSC). But the clock source is software selectable. So the Q cycle may be independent of the device oscillator cycle (TOSC). In the full description of each instruction, the detailed Q cycle for the instruction will be shown. Figure 31-3: Q Cycle Activity 31 Instruction Set TOSC Tcy1 Tcy2 Tcy3 2000 Microchip Technology Inc. DS39532A-page 31-13

PIC18C Reference Manual 31.7 Instruction Descriptions ADDLW Add Literal to WREG Syntax: [ label ] ADDLW k Operands: 0 k 255 Operation: (WREG) + k WREG Status Affected: C, DC, Z, OV, N Encoding: 0000 1111 kkkk kkkk Description: The eight bit literal k is added to the contents of the WREG and the result is placed in the WREG. Words: 1 Cycles: 1 Q Cycle Activity: Decode Read literal 'k' Write to WREG Register Example1 ADDLW 0x19 ; Add 19h to value in WREG WREG = 0x18 C,DC,Z,OV,N =x WREG = 0x31 C = 0 DC = 1 OV = 0 N = 0 Example 2 ADDLW MYREG ; Add the value of the ; address for MYREG Register ; to WREG WREG = 0x60 Address of MYREG =0x37 MYREG is a symbol for a memory location C, DC, Z, OV, N = x WREG = 0x97 C = 0 DC = 0 OV = 1 N = 1 DS39532A-page 31-14 2000 Microchip Technology Inc.

Section 31. Instruction Set 31 Example 3 ADDLW HIGH (LU_TABLE) ; Add high byte of address ; LU_TABLE to WREG WREG = 0x10 Address of LU_TABLE = 0x9375 LU_TABLE is a label for an address in program memory C, DC, Z, OV, N = x WREG = 0xA3 C = 0 DC = 0 OV = 0 N = 1 Instruction Set Example 4 ADDLW PCL ; Add value of the address ; of Program Counter Low ; byte (PCL) to WREG WREG = 0x02 Address of PCL = 0xFF8 (only low 8-bits are used) PCL is the symbol for the Program Counter low byte location C, DC, Z, OV, N = x WREG = 0xFA C = 0 DC = 0 OV = 0 N = 0 Example 5 ADDLW Offset ; Add the value of symbol ; Offset to WREG WREG = 0x10 Offset = 0x02 C, DC, Z, OV, N = x WREG = 0x12 Offset = 0x02 C = 0 DC = 0 OV = 0 N = 0 2000 Microchip Technology Inc. DS39532A-page 31-15

PIC18C Reference Manual ADDWF Add WREG and f Syntax: [ label ]ADDWF f,d,a Operands: 0 f 255 d [0,1] a [0,1] Operation: (WREG) + (f) destination Status Affected: C, DC, Z, OV, N Encoding: 0010 01da Description: Add the contents of the WREG Register to the contents of Register 'f'. The d bit selects the destination for the. If 'd' is 1; the result is stored back in the File Register 'f'. If 'd' is 0; the result is stored in the WREG Register. The a bit selects which bank is accessed for the. If a is 1; the bank specified by the BSR Register is used. If a is 0; the access bank is used. Words: 1 Cycles: 1 Q Cycle Activity: Decode Read Register 'f' Write to destination Example 1 ADDWF FSR0L, 1, 1 ; Add value in WREG to ; value in the ; FSR0H:FSR0L Register Case 1: WREG = 0x17 FSR0H:FSR0L = 0x2C2 C,DC,Z,OV,N = x WREG = 0x17 FSR0H:FSR0L = 0x2D9 C = 0 DC = 0 OV = 0 N = 1 Case 2: WREG = 0x17 FSR0H:FSR0L = 0x2FF C,DC,Z,OV,N = x WREG = 0x17 FSR0H:FSR0L = 0x316 C = 0 DC = 0 OV = 0 N = 0 DS39532A-page 31-16 2000 Microchip Technology Inc.

Section 31. Instruction Set 31 Example 2 ADDWF INDF0, 1, 1 ; Add value in WREG to ; value in the register ; pointed to (addressed) ; by the FSR0H:FSR0L ; Register WREG = 0x17 FSR0H:FSR0L = 0x6C2 Contents of Address (FSR0) = 0x20 C,DC,Z,OV,N = x WREG = 0x17 FSR0H:FSR0L = 0x6C2 Contents of Address (FSR0) = 0x37 C = 0 DC = 0 OV = 0 N = 0 Instruction Set Example 3 ADDWF INDF0, 1, 0 ; Add value in WREG to ; value in the register ; pointed to (addressed) ; by the FSR0H:FSR0L ; Register WREG = 0x17 FSR0H:FSR0L = 0x0C2 Contents of Address (FSR0) = 0x20 C,DC,Z,OV,N = x WREG = 0x17 FSR0H:FSR0L = 0x0C2 Contents of Address (FSR0) = 0x37 C = 0 DC = 0 OV = 0 N = 0 2000 Microchip Technology Inc. DS39532A-page 31-17

PIC18C Reference Manual Example 4 ADDWF PCL, 1, 1 ; Add the value in WREG to ; the current value in the ; low byte of the program ; counter (PCL) Case 1: WREG = 0x10 PCL = 0x37 C,DC,Z,OV,N = x WREG = 0x10 PCL = 0x47 C = 0 DC = 0 OV = 0 N = 0 Case 2: WREG = 0x10 PCL = 0xF7 PCH = 0x08 C,DC,Z,OV,N = x WREG = 0x10 PCL = 0x07 PCH = 0x08 C = 1 DC = 0 OV = 0 N = 0 DS39532A-page 31-18 2000 Microchip Technology Inc.

Section 31. Instruction Set 31 Example 5 ADDWF MYREG, 1 ; Add the value in WREG to ; the current value in ; MYREG ; (assembler determines ; that MYREG requires ; access bit to be set) Case 1: BSR = 0x01 WREG = 0x10 MYREG = 0x37 ; In Bank 1 C,DC,Z,OV,N = x BSR = 0x01 WREG = 0x10 MYREG = 0x47 ; In Bank 1 C = 0 DC = 0 OV = 0 N = 0 Case 2: BSR = 0x01 WREG = 0x10 MYREG = 0xF7 C,DC,Z,OV,N = x BSR = 0x01 WREG = 0x10 MYREG = 0x07 C = 1 DC = 0 OV = 0 N = 0 ; In Bank 1 ; In Bank 1 Instruction Set 2000 Microchip Technology Inc. DS39532A-page 31-19

PIC18C Reference Manual ADDWFC Add WREG and Carry bit to f Syntax: [ label ]ADDWF f,d,a Operands: 0 f 255 d [0,1] a [0,1] Operation: (WREG) + (f) + (C) destination Status Affected: C, DC, Z, OV, N Encoding: 0010 00da Description: Add the contents of the WREG Register and the Carry bit to the contents of Register 'f'. The d bit selects the destination for the. If 'd' is 1; the result is stored back in the File Register 'f'. If 'd' is 0; the result is stored in the WREG Register. The a bit selects which bank is accessed for the. If a is 1; the bank specified by the BSR Register is used. If a is 0; the access bank is used. Words: 1 Cycles: 1 Q Cycle Activity: Decode Read Register 'f' Write to destination Example 1 ADDWFC FSR0L, 0, 1 ; Add WREG, C bit, and FSR0L ; value (Destination WREG) Case 1: WREG = 0x17 FSR0H:FSR0L = 0x9C2 C = 0 DC,Z,OV,N = x WREG = 0xD9 FSR0H:FSR0L = 0x9C2 C = 0 DC = 0 OV = 0 N = 1 Case 2: WREG = 0x17 FSR0H:FSR0L = 0x7C2 C = 1 DC,Z,OV,N = x WREG = 0xDA FSR0H:FSR0L = 0x7C2 C = 0 DC = 0 OV = 0 N = 1 DS39532A-page 31-20 2000 Microchip Technology Inc.

Section 31. Instruction Set 31 Example 2 ADDWFC INDF0, 1, 1 ; Add WREG and the Carry ; bit to the value pointed ; to by the FSR0H:FSR0L ; (Destination: File ; Register) WREG = 0x17 FSR0H:FSR0L = 0x0C2 Contents of Address (FSR0H:FSR0L) = 0x20 C = 0 DC, Z, OV, N = x WREG = 0x17 FSR0H:FSR0L = 0x0C2 Contents of Address (FSR0H:FSR0L) = 0x37 C = 0 DC = 0 OV = 0 N = 0 Instruction Set Example 3 ADDWFC PCL, 1, 1 ; Add WREG and the Carry ; bit to the PCL Register Case 1: WREG = 0x10 PCL = 0x38 C = 0 DC,Z,OV,N = x WREG = 0x10 PCL = 0x48 C = 0 DC = 0 OV = 0 N = 0 Case 2: WREG = 0x10 PCL = 0xF8 PCH = 0x08 C = 0 DC,Z,OV,N = x WREG = 0x10 PCL = 0x08 PCH = 0x08 C = 1 DC = 0 OV = 0 N = 0 2000 Microchip Technology Inc. DS39532A-page 31-21

PIC18C Reference Manual ANDLW AND Literal with WREG Syntax: [ label ] ANDLW k Operands: 0 k 255 Operation: (WREG).AND. (k) W Status Affected: Z, N Encoding: 0000 1011 kkkk kkkk Description: The contents of WREG Register are AND d with the eight bit literal 'k'. The result is placed in the WREG Register. Words: 1 Cycles: 1 Q Cycle Activity: Decode Read literal 'k' Write to WREG Register Example 1 ANDLW 0x5F ; And constant to WREG WREG = 0xA3 Z, N = x WREG = 0x03 N = 0 ; 0101 1111 (0x5F) ; 1010 0011 (0xA3) ;---------- ------ ; 0000 0011 (0x03) Example 2 ANDLW MYREG ; And address of MYREG ; to WREG WREG = 0xA3 Address of MYREG =0x37 Z, N = x MYREG is a symbol for a memory location WREG = 0x23 N = 0 ; 0011 0111 (0x37) ; 1010 0011 (0xA3) ;---------- ------ ; 0010 0011 (0x23) DS39532A-page 31-22 2000 Microchip Technology Inc.

Section 31. Instruction Set 31 Example 3 ANDLW HIGH (LU_TABLE) WREG = 0xA3 Address of LU_TABLE = 0x9375 Z, N = x LU_TABLE is a label for an address in program memory WREG = 0x83 N = 1 ; And the high byte of ; address LU_TABLE ; with WREG ; 1010 0011 (0xA3) ; 1001 0011 (0x93) ;---------- ------ ; 1000 0011 (0x83) Instruction Set Example 4 ANDLW LOW (LU_TABLE); And the low byte of ; address LU_TABLE ; with WREG WREG = 0xA3 ; 1010 0011 (0xA3) Address of LU_TABLE = 0x9375 Z, N = x LU_TABLE is a label for an address in program memory WREG = 0x21 N = 0 ; 0111 0101 (0x75) ;---------- ------ ; 0010 0001 (0x21) 2000 Microchip Technology Inc. DS39532A-page 31-23

PIC18C Reference Manual ANDWF AND WREG with f Syntax: [ label ]ANDWF f,d,a Operands: 0 f 255 d [0,1] a [0,1] Operation: (WREG).AND. (f) destination Status Affected: Z, N Encoding: 0001 01da Description: The contents of the WREG Register are AND d with the contents of Register 'f'. The d bit selects the destination for the. If 'd' is 1; the result is stored back in the File Register 'f'. If 'd' is 0; the result is stored in the WREG Register. The a bit selects which bank is accessed for the. If a is 1; the bank specified by the BSR Register is used. If a is 0; the access bank is used. Words: 1 Cycles: 1 Q Cycle Activity: Decode Read Register 'f' Write to destination Example 1 ANDWF REG1, 1, 1 ; And WREG with REG1 WREG = 0x17 REG1 = 0xC2 Z, N = x WREG = 0x17 REG1 = 0x02 N = 0 ; 0001 0111 (0x17) ; 1100 0010 (0xC2) ;---------- ------ ; 0000 0010 (0x02) Example 2 ANDWF REG1, 0, 1 ; And WREG with REG1 ; (destination WREG) WREG = 0x17 REG1 = 0xC2 Z, N = x WREG = 0x02 REG1 = 0xC2 N = 0 ; 0001 0111 (0x17) ; 1100 0010 (0xC2) ;---------- ------ ; 0000 0010 (0x02) DS39532A-page 31-24 2000 Microchip Technology Inc.

Section 31. Instruction Set 31 Example 3 ANDWF INDF0, 1, 1 ; And WREG with value pointed ; by FSR0H:FSR0L (FSR0) Case 1: Case 2: WREG = 0x17 FSR0H:FSR0L = 0xFC2 Contents of Address (FSR0) = 0x5A Z, N = x WREG = 0x17 FSR0H:FSR0L = 0xFC2 Contents of Address (FSR0) = 0x12 N = 0 WREG = 0x00 FSR0H:FSR0L = 0x4C2 Contents of Address (FSR0) = 0x5A Z, N = x WREG = 0x00 FSR0H:FSR0L = 0x4C2 Contents of Address (FSR0) = 0x00 Z = 1 N = 0 ; 0001 0111 (0x17) ; 0101 1010 (0x5A) ;---------- ------ ; 0001 0010 (0x12) ; 0000 0000 (0x00) ; 0101 1010 (0x5A) ;---------- ------ ; 0000 0000 (0x00) Instruction Set 2000 Microchip Technology Inc. DS39532A-page 31-25

PIC18C Reference Manual BC Branch if Carry Syntax: [ label ] BC n Operands: -128 f 127 Operation: If carry bit is 1 (PC + 2) + 2n PC Status Affected: ne Encoding: 1110 0010 nnnn nnnn Description: If the Carry bit is 1, then the program will branch. The 2 s complement number 2n (the offset) is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be (PC+2)+2n. This instruction is then a two-cycle instruction. Words: 1 Cycles: 1 (2) Q Cycle Activity: If Branch Decode Read literal 'n' Write to PC If Branch Decode Read literal 'n' Example 1 Case 1: Case 2: HERE NOT_C C_CODE BC GOTO C_CODE MORE_CODE C = 0 PC = address NOT_C C = 1 PC = address C_CODE ; ; If C bit is not set ; execute this code. ; ; else if C bit is set ; this code will execute DS39532A-page 31-26 2000 Microchip Technology Inc.

Section 31. Instruction Set 31 Example 2 Case 1: Case 2: HERE NO_C PLUS0 PLUS1 PLUS2 PLUS3 PLUS4 PLUS5 PLUS6 BC GOTO $ + OFFSET PROCESS_CODE C = 0 PC = address NO_C C = 1 + OFFSET ; If carry bit is set, ; branch to HERE+OFFSET Instruction Set Example 3 Case 1: Case 2: MIN6 MIN5 MIN4 MIN3 MIN2 MIN1 MIN0 HERE NO_C BC GOTO $ - OFFSET PROCESS_CODE C = 0 PC = address NO_C C = 1 - OFFSET ; If carry bit is set, ; branch to HERE-OFFSET te: Assembler will convert the specified address label into the offset to be used. 2000 Microchip Technology Inc. DS39532A-page 31-27

PIC18C Reference Manual BCF Bit Clear f Syntax: [ label ]BCF f,b,a Operands: 0 f 255 0 b 7 a [0,1] Operation: 0 f<b> Status Affected: ne Encoding: 1001 bbba Description: Bit 'b' in Register 'f' of the specified bank is cleared. The a bit selects which bank is accessed for the. If a is 1; the bank specified by the BSR Register is used. If a is 0; the access bank is used. Words: 1 Cycles: 1 Q Cycle Activity: Decode Read Register 'f' Write Register 'f' Example 1 BCF MYREG, 7, 1 ; Clear bit 7 in Register ; MYREG MYREG = 0xC7 MYREG = 0x47 ; 1100 0111 ; 0100 0111 DS39532A-page 31-28 2000 Microchip Technology Inc.

Section 31. Instruction Set 31 Example 2 BCF INDF0, 3, 0 ; Clear bit 7 in the register ; pointed to by the FSR0 ; (FSR0H:FSR0L) Register FSR0 = 0x3C2 Contents of Address (FSR0) = 0x2F ; 0010 1111 FSR0 = 0x3C2 Contents of Address (FSR0) = 0x27 ; 0010 0111 Instruction Set 2000 Microchip Technology Inc. DS39532A-page 31-29

PIC18C Reference Manual BN Branch if Negative Syntax: [ label ] BN n Operands: -128 f 127 Operation: If negative bit is 1 (PC + 2) + 2n PC Status Affected: ne Encoding: 1110 0110 nnnn nnnn Description: If the Negative bit is 1, then the program will branch. The 2 s complement number 2n (the offset) is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be (PC+2)+2n. This instruction is then a two-cycle instruction. Words: 1 Cycles: 1 (2) Q Cycle Activity: If Branch Decode Read literal 'n' Write to PC If Branch Decode Read literal 'n' Example 1 Case 1: Case 2: HERE NOT_N N_CODE BN GOTO N_CODE MORE_CODE N = 0 PC = address NOT_N N = 1 PC = address N_CODE ; If N bit is not set ; execute this code. ; ; ; else if N bit is set ; this code will execute DS39532A-page 31-30 2000 Microchip Technology Inc.

Section 31. Instruction Set 31 Example 2 Case 1: Case 2: HERE NOT_N PLUS0 PLUS1 PLUS2 PLUS3 PLUS4 PLUS5 PLUS6 BN GOTO $ + OFFSET PROCESS_CODE N = 0 PC = address NOT_N N = 1 + OFFSET ; If negative bit is set, ; branch to HERE + OFFSET Instruction Set Example 3 Case 1: Case 2: MIN6 MIN5 MIN4 MIN3 MIN2 MIN1 MIN0 HERE NO_N BN GOTO $ - OFFSET PROCESS_CODE N = 0 PC = address NO_N N = 1 - OFFSET ; If negative bit is set, ; branch to HERE - OFFSET te: Assembler will convert the specified address label into the offset to be used. 2000 Microchip Technology Inc. DS39532A-page 31-31

PIC18C Reference Manual BNC Branch if t Carry Syntax: [ label ] BNC n Operands: -128 f 127 Operation: If carry bit is 0 (PC + 2) + 2n PC Status Affected: ne Encoding: 1110 0011 nnnn nnnn Description: If the Carry bit is 0, then the program will branch. The 2 s complement number 2n (the offset) is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be (PC+2)+2n. This instruction is then a two-cycle instruction. Words: 1 Cycles: 1 (2) Q Cycle Activity: If Branch Decode Read literal 'n' Write to PC If Branch Decode Read literal 'n' Example 1 Case 1: Case 2: HERE CARRY NC_CODE BNC GOTO NC_CODE MORE_CODE C = 0 PC = address NC_CODE C = 1 PC = address CARRY ; If C bit is set ; execute this code. ; ; ; else if C bit is clear ; this code will execute DS39532A-page 31-32 2000 Microchip Technology Inc.

Section 31. Instruction Set 31 Example 2 Case 1: Case 2: HERE CARRY PLUS0 PLUS1 PLUS2 PLUS3 PLUS4 PLUS5 PLUS6 BNC GOTO $ + OFFSET PROCESS_CODE C = 0 + OFFSET C = 1 PC = address CARRY ; If carry bit is clear, ; branch to HERE + OFFSET Instruction Set Example 3 Case 1: Case 2: MIN6 MIN5 MIN4 MIN3 MIN2 MIN1 MIN0 HERE CARRY BNC GOTO $ - OFFSET PROCESS_CODE C = 0 - OFFSET C = 1 PC = address CARRY ; If carry bit is clear, ; branch to HERE - OFFSET te: Assembler will convert the specified address label into the offset to be used. 2000 Microchip Technology Inc. DS39532A-page 31-33

PIC18C Reference Manual BNN Branch if t Negative Syntax: [ label ] BNN n Operands: -128 f 127 Operation: If negative bit is 0 (PC + 2) + 2n PC Status Affected: ne Encoding: 1110 0111 nnnn nnnn Description: If the Negative bit is 0, then the program will branch. The 2 s complement number 2n (the offset) is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be (PC+2)+2n. This instruction is then a two-cycle instruction. Words: 1 Cycles: 1 (2) Q Cycle Activity: If Branch Decode Read literal 'n' Write to PC If Branch Decode Read literal 'n' Example 1 Case 1: Case 2: HERE BNN NEG GOTO POS_CODE POS_CODE MORE_CODE N = 0 PC = address POS_CODE N = 1 PC = address NEG ; If N bit is set ; execute this code. ; ; ; else if N bit is clear ; this code will execute DS39532A-page 31-34 2000 Microchip Technology Inc.

Section 31. Instruction Set 31 Example 2 Case 1: Case 2: HERE NEG PLUS0 PLUS1 PLUS2 PLUS3 PLUS4 PLUS5 PLUS6 BNN GOTO $ + OFFSET PROCESS_CODE N = 0 + OFFSET N = 1 PC = address NEG ; If negative bit is clear, ; branch to HERE + OFFSET Instruction Set Example 3 Case 1: Case 2: MIN6 MIN5 MIN4 MIN3 MIN2 MIN1 MIN0 HERE NEG BNN GOTO $ - OFFSET PROCESS_CODE N = 0 - OFFSET N = 1 PC = address NEG ; If negative bit is clear, ; branch to HERE - OFFSET te: Assembler will convert the specified address label into the offset to be used. 2000 Microchip Technology Inc. DS39532A-page 31-35

PIC18C Reference Manual BNOV Branch if t Overflow Syntax: [ label ] BNOV n Operands: -128 f 127 Operation: If overflow bit is 0 (PC + 2) + 2n PC Status Affected: ne Encoding: 1110 0101 nnnn nnnn Description: If the Overflow bit is 0, then the program will branch. The 2 s complement number 2n (the offset) is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be (PC+2)+2n. This instruction is then a two-cycle instruction. Words: 1 Cycles: 1 (2) Q Cycle Activity: If Branch Decode Read literal 'n' Write to PC If Branch Decode Read literal 'n' Example 1 Case 1: Case 2: HERE BNOV OVFL GOTO NOV_CODE NOV_CODE MORE_CODE OV = 0 PC = address NOV_CODE OV = 1 PC = address OVFL ; If overflow bit is set ; execute this code. ; ; ; else if overflow bit is ; clear this code will ; execute DS39532A-page 31-36 2000 Microchip Technology Inc.

Section 31. Instruction Set 31 Example 2 Case 1: Case 2: HERE OVFL PLUS0 PLUS1 PLUS2 PLUS3 PLUS4 PLUS5 PLUS6 BNOV GOTO $ + OFFSET PROCESS_CODE OV = 0 + OFFSET OV = 1 PC = address OVFL ; If overflow bit is clear, ; branch to HERE + OFFSET Instruction Set Example 3 Case 1: Case 2: MIN6 MIN5 MIN4 MIN3 MIN2 MIN1 MIN0 HERE OVFL BNOV GOTO $ - OFFSET PROCESS_CODE OV = 0 - OFFSET OV = 1 PC = address OVFL ; If overflow bit is clear, ; branch to HERE - OFFSET te: Assembler will convert the specified address label into the offset to be used. 2000 Microchip Technology Inc. DS39532A-page 31-37

PIC18C Reference Manual BNZ Branch if t Zero Syntax: [ label ] BNZ n Operands: -128 f 127 Operation: If zero bit is 0 (PC + 2) + 2n PC Status Affected: ne Encoding: 1110 0001 nnnn nnnn Description: If the Zero bit is 0, then the program will branch. The 2 s complement number 2n (the offset) is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be (PC+2)+2n. This instruction is then a two-cycle instruction. Words: 1 Cycles: 1 (2) Q Cycle Activity: If Branch Decode Read literal 'n' Write to PC If Branch Decode Read literal 'n' Example 1 Case 1: Case 2: HERE ZERO Z_CODE BNZ GOTO Z_CODE MORE_CODE PC = address Z_CODE Z = 1 PC = address ZERO ; If Z bit is set ; execute this code. ; ; ; else if Z bit is clear ; this code will execute DS39532A-page 31-38 2000 Microchip Technology Inc.

Section 31. Instruction Set 31 Example 2 Case 1: Case 2: HERE ZERO PLUS0 PLUS1 PLUS2 PLUS3 PLUS4 PLUS5 PLUS6 BNZ GOTO $ + OFFSET PROCESS_CODE + OFFSET Z = 1 PC = address ZERO ; If zero bit is clear, ; branch to HERE + OFFSET Instruction Set Example 3 Case 1: Case 2: MIN6 MIN5 MIN4 MIN3 MIN2 MIN1 MIN0 HERE ZERO BNZ GOTO $ - OFFSET PROCESS_CODE - OFFSET Z = 1 PC = address ZERO ; If zero bit is clear, ; branch to HERE - OFFSET te: Assembler will convert the specified address label into the offset to be used. 2000 Microchip Technology Inc. DS39532A-page 31-39

PIC18C Reference Manual BOV Branch if Overflow Syntax: [ label ] BOV n Operands: -128 f 127 Operation: If overflow bit is 1 (PC + 2) + 2n PC Status Affected: ne Encoding: 1110 0100 nnnn nnnn Description: If the Overflow bit is 1, then the program will branch. The 2 s complement number 2n (the offset) is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be (PC+2)+2n. This instruction is then a two-cycle instruction. Words: 1 Cycles: 1 (2) Q Cycle Activity: If Branch Decode Read literal 'n' Write to PC If Branch Decode Read literal 'n' Example 1 Case 1: Case 2: HERE OVFL OV_CODE BOV GOTO OV_CODE MORE_CODE OV = 0 PC = address OVFL OV = 1 PC = address OV_CODE ; If OV bit is clear ; execute this code. ; ; ; else if OV bit is set ; this code will execute DS39532A-page 31-40 2000 Microchip Technology Inc.

Section 31. Instruction Set 31 Example 2 Case 1: Case 2: HERE OVFL PLUS0 PLUS1 PLUS2 PLUS3 PLUS4 PLUS5 PLUS6 BOV GOTO $ + OFFSET PROCESS_CODE OV = 0 PC = address OVFL OV = 1 + OFFSET ; If overflow bit is set, ; branch to HERE + OFFSET Instruction Set Example 3 Case 1: Case 2: MIN6 MIN5 MIN4 MIN3 MIN2 MIN1 MIN0 HERE OVFL BOV GOTO $ - OFFSET PROCESS_CODE OV = 0 PC = address OVFL OV = 1 - OFFSET ; If OV bit is set, ; branch to HERE - OFFSET te: Assembler will convert the specified address label into the offset to be used. 2000 Microchip Technology Inc. DS39532A-page 31-41

PIC18C Reference Manual BRA Branch Unconditional Syntax: [ label ] BRA n Operands: -1024 f 1023 Operation: (PC + 2) + 2n PC Status Affected: ne Encoding: 1101 0nnn nnnn nnnn Description: The 2 s complement number 2n (the offset) is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be (PC+2)+2n. This instruction is a two-cycle instruction. Words: 1 Cycles: 2 Q Cycle Activity: If Branch Decode Read literal 'n' Write to PC If Branch Decode Read literal 'n' Example 1 HERE THERE BRA THERE PC = address THERE ; Branch to a program memory ; location (THERE) ; this location must be ; < 1023 locations forward DS39532A-page 31-42 2000 Microchip Technology Inc.

Section 31. Instruction Set 31 Example 2 THERE HERE BRA THERE PC = address THERE ; Branch to a program memory ; location (THERE) ; this location must be ; < 1024 locations backward Instruction Set Example 3 HERE BRA $ ; Branch to program memory ; location (HERE). ; Infinite Loop te: Assembler will convert the specified address label into the offset to be used. 2000 Microchip Technology Inc. DS39532A-page 31-43

PIC18C Reference Manual BSF Bit Set f Syntax: [ label ] BSF f, b, a Operands: 0 f 255 0 b 7 a [0,1] Operation: 1 f<b> Status Affected: ne Encoding: 1000 bbba Description: Bit 'b' in Register 'f' is set. The a bit selects which bank is accessed for the. If a is 1; the bank specified by the BSR Register is used. If a is 0; the access bank is used. Words: 1 Cycles: 1 Q Cycle Activity: Decode Read Register 'f' Write Register 'f' Example 1 BSF FLAG_REG, 7 ; Set bit 7 in Register ; FLAG_REG ; (assembler determines ; that FLAG_REG requires ; access bit to be set) FLAG_REG = 0x0A ; 0000 1010 FLAG_REG = 0x8A ; 1000 1010 Example 2 BSF INDF0, 3, 0 ; Set bit 3 in the register ; pointed to by the FSR0 ; (FSR0H:FSR0L) Register WREG = 0x17 FSR0 = 0x0C2 Contents of Address ; 0010 0000 (FSR0)= 0x20 WREG = 0x17 FSR0 = 0x0C2 Contents of Address ; 0010 1000 (FSR0) = 0x28 DS39532A-page 31-44 2000 Microchip Technology Inc.

Section 31. Instruction Set 31 BTFSC Bit Test File, Skip if Clear Syntax: [ label ]BTFSC f,b,a Operands: 0 f 255 0 b 7 a [0,1] Operation: Skip if (f<b>) = 0 Status Affected: ne Encoding: 1011 bbba Description: If bit 'b' in Register 'f' is '0' then the next instruction is skipped. If bit 'b' is '0' then the next instruction (fetched during the current instruction execution) is discarded, and a NOP is executed instead, making this a 2-cycle instruction. Instruction Set The a bit selects which bank is accessed for the. If a is 1; the bank specified by the BSR Register is used. If a is 0; the access bank is used. Words: 1 Cycles: 1 (2 or 3) Q Cycle Activity: Decode Read Register 'f' If skip (2nd cycle): Ifskipandfollowedbyatwowordinstruction: Example 1 Case 1: Case 2: HERE FALSE TRUE BTFSC GOTO FLAG, 4, 1 PROCESS_CODE FLAG = xxx0 xxxx Since FLAG<4> = 0 PC = address TRUE FLAG = xxx1 xxxx Since FLAG<4> = 1 PC = address FALSE ; Test bit 4 of Register ; FLAG, and skip if ; clear 2000 Microchip Technology Inc. DS39532A-page 31-45

PIC18C Reference Manual BTFSS Bit Test File, Skip if Set Syntax: [ label ]BTFSS f,b,a Operands: 0 f 255 0 b<7 a [0,1] Operation: Skip if (f<b>) = 1 Status Affected: ne Encoding: 1010 bbba Description: If bit 'b' in Register 'f' is '1' then the next instruction is skipped. If bit 'b' is '1', then the next instruction (fetched during the current instruction execution) is discarded and a NOP is executed instead, making this a 2-cycle instruction. The a bit selects which bank is accessed for the. If a is 1; the bank specified by the BSR Register is used. If a is 0; the access bank is used. Words: 1 Cycles: 1 (2 or 3) Q Cycle Activity: Decode Read Register 'f' If skip (2nd cycle): Ifskipandfollowedbyatwowordinstruction: Example 1 Case 1: Case 2: HERE FALSE TRUE BTFSS GOTO FLAG, 4, 0 PROCESS_CODE FLAG = xxx0 xxxx Since FLAG<4> = 0 PC = address FALSE FLAG = xxx1 xxxx Since FLAG<4> = 1 PC = address TRUE ; Test bit 4 of Register ; FLAG, and skip if set DS39532A-page 31-46 2000 Microchip Technology Inc.