CS 61C: Great Ideas in Computer Architecture More RISC-V Instructions and How to Implement Functions

Similar documents
CS 110 Computer Architecture Lecture 6: More MIPS, MIPS Functions

CS 61C: Great Ideas in Computer Architecture More MIPS, MIPS Functions

UCB CS61C : Machine Structures

CS 61C: Great Ideas in Computer Architecture Intro to Assembly Language, MIPS Intro

Lecture 7: Procedures

CS61C : Machine Structures

CS61C : Machine Structures

Inequalities in MIPS (2/4) Inequalities in MIPS (1/4) Inequalities in MIPS (4/4) Inequalities in MIPS (3/4) UCB CS61C : Machine Structures

CS61C : Machine Structures

CS 61C: Great Ideas in Computer Architecture (Machine Structures) More MIPS Machine Language

CS 61c: Great Ideas in Computer Architecture

CS 61C: Great Ideas in Computer Architecture. Lecture 6: More MIPS, MIPS Func.ons. Instructor: Sagar Karandikar

CS 110 Computer Architecture MIPS Instruction Formats

ECE 15B Computer Organization Spring 2010

COMP 303 Computer Architecture Lecture 3. Comp 303 Computer Architecture

MIPS Functions and Instruction Formats

CS 61C: Great Ideas in Computer Architecture Strings and Func.ons. Anything can be represented as a number, i.e., data or instruc\ons

CS 61C: Great Ideas in Computer Architecture Introduction to Assembly Language and RISC-V Instruction Set Architecture

CENG3420 Lecture 03 Review

CS 61C: Great Ideas in Computer Architecture. More MIPS, MIPS Functions

Do-While Example. In C++ In assembly language. do { z--; while (a == b); z = b; loop: addi $s2, $s2, -1 beq $s0, $s1, loop or $s2, $s1, $zero

Control Instructions. Computer Organization Architectures for Embedded Computing. Thursday, 26 September Summary

Control Instructions

Lecture 7: Procedures and Program Execution Preview

CS 61C: Great Ideas in Computer Architecture Func%ons and Numbers

MIPS R-format Instructions. Representing Instructions. Hexadecimal. R-format Example. MIPS I-format Example. MIPS I-format Instructions

Chapter 2A Instructions: Language of the Computer

Chapter 2. Computer Abstractions and Technology. Lesson 4: MIPS (cont )

Branch Addressing. Jump Addressing. Target Addressing Example. The University of Adelaide, School of Computer Science 28 September 2015

Thomas Polzer Institut für Technische Informatik

Machine Language Instructions Introduction. Instructions Words of a language understood by machine. Instruction set Vocabulary of the machine

Instructor: Randy H. Katz hap://inst.eecs.berkeley.edu/~cs61c/fa13. Fall Lecture #7. Warehouse Scale Computer

Course Administration

Lecture 5: Procedure Calls

CS 61C: Great Ideas in Computer Architecture RISC-V Instruction Formats

9/14/17. Levels of Representation/Interpretation. Big Idea: Stored-Program Computer

Chapter 2. Instructions: Language of the Computer. Adapted by Paulo Lopes

Agenda. Strings: C vs. Java. Loading, Storing bytes. Support for Characters and Strings 6/29/2011

Reduced Instruction Set Computer (RISC)

Rui Wang, Assistant professor Dept. of Information and Communication Tongji University.

Reduced Instruction Set Computer (RISC)

Lecture 6: Assembly Programs

CS 61C: Great Ideas in Computer Architecture Intro to Assembly Language, MIPS Intro

ELEC / Computer Architecture and Design Fall 2013 Instruction Set Architecture (Chapter 2)

Computer Organization and Structure. Bing-Yu Chen National Taiwan University

EEM 486: Computer Architecture. Lecture 2. MIPS Instruction Set Architecture

MIPS Functions and the Runtime Stack

Lecture 2. Instructions: Language of the Computer (Chapter 2 of the textbook)

Introduction to the MIPS. Lecture for CPSC 5155 Edward Bosworth, Ph.D. Computer Science Department Columbus State University

CS 61C: Great Ideas in Computer Architecture Introduction to Assembly Language and MIPS Instruction Set Architecture

CSE Lecture In Class Example Handout

CS 61C: Great Ideas in Computer Architecture. MIPS Instruction Formats

Procedure Call Instructions

Computer Organization MIPS ISA

COMPUTER ORGANIZATION AND DESIGN

Prof. Kavita Bala and Prof. Hakim Weatherspoon CS 3410, Spring 2014 Computer Science Cornell University. See P&H 2.8 and 2.12, and A.

CS 61C: Great Ideas in Computer Architecture Intro to Assembly Language, MIPS Intro

Instructions: Assembly Language

CSE Lecture In Class Example Handout

Architecture II. Computer Systems Laboratory Sungkyunkwan University

ECE232: Hardware Organization and Design

CISC 662 Graduate Computer Architecture. Lecture 4 - ISA MIPS ISA. In a CPU. (vonneumann) Processor Organization

MIPS Datapath. MIPS Registers (and the conventions associated with them) MIPS Instruction Types

Course Administration

COE608: Computer Organization and Architecture

Computer Science and Engineering 331. Midterm Examination #1. Fall Name: Solutions S.S.#:

comp 180 Lecture 10 Outline of Lecture Procedure calls Saving and restoring registers Summary of MIPS instructions

ECE331: Hardware Organization and Design

Lecture 4: MIPS Instruction Set

Chapter 2: Instructions:

CS 61c: Great Ideas in Computer Architecture

CSCI 402: Computer Architectures. Instructions: Language of the Computer (3) Fengguang Song Department of Computer & Information Science IUPUI.

We will study the MIPS assembly language as an exemplar of the concept.

Computer Organization and Structure. Bing-Yu Chen National Taiwan University

Stored Program Concept. Instructions: Characteristics of Instruction Set. Architecture Specification. Example of multiple operands

CS 316: Procedure Calls/Pipelining

CISC 662 Graduate Computer Architecture. Lecture 4 - ISA

Compiling Code, Procedures and Stacks

Lecture 5: Procedure Calls

Chapter 2. Instructions: Language of the Computer

CS3350B Computer Architecture

Stored Program Concept. Instructions: Characteristics of Instruction Set. Architecture Specification. Example of multiple operands

Instruction Set Architecture part 1 (Introduction) Mehran Rezaei

CENG3420 L03: Instruction Set Architecture

ECE468 Computer Organization & Architecture. MIPS Instruction Set Architecture

CS 61C: Great Ideas in Computer Architecture MIPS Instruction Formats

Instructions: MIPS arithmetic. MIPS arithmetic. Chapter 3 : MIPS Downloaded from:

Computer Architecture

Computer Architecture. The Language of the Machine

Overview. Introduction to the MIPS ISA. MIPS ISA Overview. Overview (2)

Lecture 7: Examples, MARS, Arithmetic

Computer Architecture. Chapter 2-2. Instructions: Language of the Computer

Chapter 2. Instructions: Language of the Computer. HW#1: 1.3 all, 1.4 all, 1.6.1, , , , , and Due date: one week.

ECE260: Fundamentals of Computer Engineering

101 Assembly. ENGR 3410 Computer Architecture Mark L. Chang Fall 2009

Calling Conventions. Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell University. See P&H 2.8 and 2.12

Instructions: Language of the Computer

Instruction Set Architecture

Procedures and Stacks

Procedure Calling. Procedure Calling. Register Usage. 25 September CSE2021 Computer Organization

Transcription:

CS 61C: Great Ideas in Computer Architecture More RISC-V Instructions and How to Implement Functions Instructors: Krste Asanović and Randy H. Katz http://inst.eecs.berkeley.edu/~cs61c/fa17 9/14/17 Fall 2017 - Lecture #6 1

Outline RISC-V ISA and C-to-RISC-V Review Program Execution Overview Function Call Function Call Example And in Conclusion 9/14/17 2

Outline RISC-V ISA and C-to-RISC-V Review Program Execution Overview Function Call Function Call Example And in Conclusion 9/14/17 3

Levels of Representation/Interpretation High-Level Language Program (e.g., C) Compiler Assembly Language Program (e.g., RISC-V) Assembler Machine Language Program (RISC-V) temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; lw lw sw sw x10, 0(x12) x11, 4(x12) x11, 0(x12) x10, 4(x12) Anything can be represented as a number, i.e., data or instructions 0000 1001 1100 0110 1010 1111 0101 1000 1010 1111 0101 1000 0000 1001 1100 0110 1100 0110 1010 1111 0101 1000 0000 1001 0101 1000 0000 1001 1100 0110 1010 1111 Machine Interpretation Hardware Architecture Description (e.g., block diagrams) Architecture Implementation Logic Circuit Description (Circuit Schematic Diagrams) 9/14/17 4

Review From Last Lecture Computer words and vocabulary are called instructions and instruction set respectively RISC-V is example RISC instruction set used in CS61C Lecture/problems use 32-bit RV32 ISA, book uses 64-bit RV64 ISA Rigid format: one operation, two source operands, one destination add,sub,mul,div,and,or,sll,srl,sra lw,sw,lb,sb to move data to/from registers from/to memory beq, bne, j for decision/flow control Simple mappings from arithmetic expressions, array access, in C to RISC-V instructions 9/14/17 5

Recap: Registers live inside the Processor Processor Control Enable? Read/Write Memory Input Datapath PC Registers Arithmetic & Logic Unit (ALU) Address Write Data Read Data Program Bytes Data Output CS 61c Processor-Memory Interface I/O-Memory Interfaces 6

Example if-else Statement Assuming translations below, compile f x10 g x11 h x12 i x13 j x14 if (i == j) bne x13,x14,else f = g + h; add x10,x11,x12 else j Exit f = g h; Else: sub x10,x11,x12 Exit: 9/14/17 7

Magnitude Compares in RISC-V Until now, we ve only tested equalities (== and!= in C); General programs need to test < and > as well. RISC-V magnitude-compare branches: Branch on Less Than Syntax: Meaning: blt reg1,reg2, label Branch on Less Than Unsigned Syntax: Meaning: if (reg1 < reg2) // treat registers as signed integers goto label; bltu reg1,reg2, label if (reg1 < reg2) // treat registers as unsigned integers goto label; 9/14/17 8

C Loop Mapped to RISC-V Assembly int A[20]; int sum = 0; for (int i=0; i<20; i++) sum += A[i]; addi x9, x8, 0 # x9=&a[0] addi x10, x0, 0 # sum=0 addi x11, x0, 0 # i=0 Loop: lw x12, 0(x9) # x12=a[i] add x10,x10,x12 # sum+= addi x9,x9,4 # &A[i++] addi x11,x11,1 # i++ addi x13,x0,20 # x13=20 blt x11,x13,loop 9

Peer Instruction Which of the following is TRUE? RED: add x10,x11,4(x12)is valid in RV32 GREEN: can byte address 8GB of memory with an RV32 word ORANGE: imm must be multiple of 4 for lw x10,imm(x10) to be valid : None of the above 9/14/17 10

Peer Instruction Which of the following is TRUE? RED: add x10,x11,4(x12)is valid in RV32 GREEN: can byte address 8GB of memory with an RV32 word ORANGE: imm must be multiple of 4 for lw x10,imm(x10) to be valid : None of the above 9/14/17 11

Outline RISC-V ISA and C-to-RISC-V Review Program Execution Overview Function Call Function Call Example And in Conclusion 9/14/17 12

foo.s Assembler foo.o Assembler to Machine Code (more later in course) Linker a.out bar.s Assembler bar.o Assembler source files (text) Assembler converts humanreadable assembly code to instruction bit patterns Machine code object files lib.o Pre-built object file libraries Machine code executable file 9/14/17 13

How Program is Stored Memory Program Bytes One RISC-V Instruction = 32 bits Data 9/14/17 14

Processor Control Datapath Program Execution PC Registers Arithmetic & Logic Unit (ALU) Read Instruction Bits Instruction Address Memory Program Bytes Data PC (program counter) is internal register inside processor holding byte address of next instruction to be executed Instruction is fetched from memory, then control unit executes instruction using datapath and memory system, and updates program counter (default is add +4 bytes to PC, to move to next sequential instruction) 9/14/17 15

In the News: Why fast computers matter European Weather supercomputer ECMWF 50 tonnes ~120,000 compute cores (Intel Broadwell) 10 PetaBytes of storage Runs Linux on each node CS 61c 16

Break! 9/14/17 17

Helpful RISC-V Assembler Features Symbolic register names E.g., a0-a7 for argument registers (x10-x17) E.g., zero for x0 Pseudo-instructions Shorthand syntax for common assembly idioms E.g., mv rd, rs = addi rd, rs, 0 E.g.2, li rd, 13 = addi rd, x0, 13 18

RISC-V Symbolic Register Names Numbers hardware understands Human-friendly symbolic names in assembly code 19

Outline RISC-V ISA and C-to-RISC-V Review Program Execution Overview Function Call Function Call Example And in Conclusion 9/14/17 20

Six Fundamental Steps in Calling a Function 1. Put parameters in a place where function can access them 2. Transfer control to function 3. Acquire (local) storage resources needed for function 4. Perform desired task of the function 5. Put result value in a place where calling code can access it and restore any registers you used 6. Return control to point of origin, since a function can be called from several points in a program 9/14/17 21

RISC-V Function Call Conventions Registers faster than memory, so use them a0 a7 (x10-x17): eight argument registers to pass parameters and two return values (a0-a1) ra: one return address register to return to the point of origin (x1) 9/14/17 22

C RISC-V Instruction Support for Functions (1/4)... sum(a,b);... /* a,b:s0,s1 */ } int sum(int x, int y) { return x+y; } address (shown in decimal) 1000 1004 1008 1012 1016 2000 2004 In RISC-V, all instructions are 4 bytes, and stored in memory just like data. So here we show the addresses of where the programs are stored. 9/14/17 23

C RISC-V Instruction Support for Functions (2/4)... sum(a,b);... /* a,b:s0,s1 */ } int sum(int x, int y) { return x+y; } address (shown in decimal) 1000 mv a0,s0 # x = a 1004 mv a1,s1 # y = b 1008 addi ra,zero,1016 #ra=1016 1012 j sum #jump to sum 1016 # next instruction 2000 sum: add a0,a0,a1 2004 jr ra # new instr. jump register 9/14/17 24

Instruction Support for Functions (3/4) C... sum(a,b);... /* a,b:s0,s1 */ } int sum(int x, int y) { return x+y; } RISC-V Question: Why use jr here? Why not use j? Answer: sum might be called by many places, so we can t return to a fixed place. The calling proc to sum must be able to say return here somehow. 2000 sum: add a0,a0,a1 2004 jr ra # new instr. jump register 9/14/17 25

Instruction Support for Functions (4/4) Single instruction to jump and save return address: jump and link (jal) Before: 1008 addi ra,zero,1016 #ra=1016 1012 j sum #goto sum After: 1008 jal sum # ra=1012,goto sum Why have a jal? Make the common case fast: function calls very common Reduce program size Don t have to know where code is in memory with jal! 9/14/17 26

RISC-V Function Call Instructions Invoke function: jump and link instruction (jal) (really should be laj link and jump ) link means form an address or link that points to calling site to allow function to return to proper address Jumps to address and simultaneously saves the address of the following instruction in register ra jal FunctionLabel Return from function: jump register instruction (jr) Unconditional jump to address specified in register: jr ra Assembler shorthand: ret = jr ra 9/14/17 27

Outline RISC-V ISA and C-to-RISC-V Review Program Execution Overview Function Call Function Call Example And in Conclusion 9/14/17 28

Example int Leaf (int g, int h, int i, int j) { int f; f = (g + h) (i + j); return f; } Parameter variables g, h, i, and j in argument registers a0, a1, a2, and a3, and f in s0 Assume need one temporary register s1 9/14/17 29

Where Are Old Register Values Saved to Restore Them After Function Call? Need a place to save old values before call function, restore them when return, and delete Ideal is stack: last-in-first-out queue (e.g., stack of plates) Push: placing data onto stack Pop: removing data from stack Stack in memory, so need register to point to it sp is the stack pointer in RISC-V (x2) Convention is grow stack down from high to low addresses Push decrements sp, Pop increments sp 9/14/17 30

RISC-V Code for Leaf() Leaf: addi sp,sp,-8 # adjust stack for 2 items sw s1, 4(sp) # save s1 for use afterwards sw s0, 0(sp) # save s0 for use afterwards add s0,a0,a1 # f = g + h add s1,a2,a3 # s1 = i + j sub a0,s0,s1 # return value (g + h) (i + j) lw s0, 0(sp) # restore register s0 for caller lw s1, 4(sp) # restore register s1 for caller addi sp,sp,8 # adjust stack to delete 2 items jr ra # jump back to calling routine 9/14/17 31

Stack Before, During, After Function Need to save old values of s0 and s1 sp sp Saved s1 Saved s0 sp Saved s1 Saved s0 Before call During call After call 9/14/17 32

Administrivia HW1 is out! Get started early. C and Memory Management Guerrilla Session is tonight 7-9pm in 293 Cory Small group tutoring sessions have launched 9/14/17 33

New RISC-V book! The RISC-V Reader, David Patterson, Andrew Waterman Available at https://www.createspace.com/7439283 Early print edition $9.99 Kindle edition to follow at some point Recommended, not required 34

Break! 9/14/17 35

What If a Function Calls a Function? Recursive Function Calls? Would clobber values in a0-a7 and ra What is the solution? 9/14/17 36

Nested Procedures (1/2) int sumsquare(int x, int y) { return mult(x,x)+ y; } Something called sumsquare, now sumsquare is calling mult So there s a value in ra that sumsquare wants to jump back to, but this will be overwritten by the call to mult Need to save sumsquare return address before call to mult 9/14/17 37

Nested Procedures (2/2) In general, may need to save some other info in addition to ra. When a C program is run, there are three important memory areas allocated: Static: Variables declared once per program, cease to exist only after execution completes - e.g., C globals Heap: Variables declared dynamically via malloc Stack: Space to be used by procedure during execution; this is where we can save register values 9/14/17 38

Optimized Function Convention To reduce expensive loads and stores from spilling and restoring registers, RISC-V function-calling convention divides registers into two categories: 1. Preserved across function call Caller can rely on values being unchanged sp, gp, tp, saved registers s0- s11 (s0 is also fp) 2. Not preserved across function call Caller cannot rely on values being unchanged Argument/return registers a0-a7,ra, temporary registers t0-t6 9/14/17 39

Peer Instruction Which statement is FALSE? RED: RISC-V uses jal to invoke a function and jr to return from a function GREEN: jal saves PC+1 in ra ORANGE: The callee can use temporary registers (ti) without saving and restoring them : The caller can rely on save registers (si) without fear of callee changing them 9/14/17 40

Peer Instruction Which statement is FALSE? RED: RISC-V uses jal to invoke a function and jr to return from a function GREEN: jal saves PC+1 in ra ORANGE: The callee can use temporary registers (ti) without saving and restoring them : The caller can rely on save registers (si) without fear of callee changing them 9/14/17 41

Allocating Space on Stack C has two storage classes: automatic and static Automatic variables are local to function and discarded when function exits Static variables exist across exits from and entries to procedures Use stack for automatic (local) variables that don t fit in registers Procedure frame or activation record: segment of stack with saved registers and local variables 9/14/17 42

Stack Before, During, After Function sp sp Saved return address (if needed) Saved argument registers (if any) Saved saved registers (if any) Local variables (if any) sp Before call During call After call 9/14/17 43

Using the Stack (1/2) So we have a register sp which always points to the last used space in the stack To use stack, we decrement this pointer by the amount of space we need and then fill it with info So, how do we compile this? int sumsquare(int x, int y) { return mult(x,x)+ y; } 9/14/17 44

Using the Stack (2/2) sumsquare: addi sp,sp,-8 # space on stack sw ra, 4(sp) # save ret addr sw a1, 0(sp) # save y mv a1,a0 # mult(x,x) jal mult # call mult lw a1, 0(sp) # restore y add a0,a0,a1 # mult()+y lw ra, 4(sp) # get ret addr addi sp,sp,8 # restore stack jr ra mult:... push pop 9/14/17 int sumsquare(int x, int y) { return mult(x,x)+ y; } 45

Where is the Stack in Memory? RV32 convention (RV64 and RV128 have different memory layouts) Stack starts in high memory and grows down Hexadecimal (base 16) : bfff_fff0 hex Stack must be aligned on 16-byte boundary (not true in examples above) RV32 programs (text segment) in low end 0001_0000 hex static data segment (constants and other static variables) above text for static variables RISC-V convention global pointer (gp) points to static RV32 gp = 1000_0000 hex Heap above static for data structures that grow and shrink ; grows up to high addresses 9/14/17 46

RV32 Memory Allocation 9/14/17 47

Outline RISC-V ISA and C-to-RISC-V Review Program Execution Overview Function Call Function Call Example And in Conclusion 9/14/17 48

And in Conclusion Functions called with jal, return with jr ra. The stack is your friend: Use it to save anything you need. Just leave it the way you found it! Instructions we know so far Arithmetic: add, addi, sub Memory: lw, sw, lb, lbu, sb Decision: beq, bne, blt, bge Unconditional Branches (Jumps): j, jal, jr Registers we know so far All of them! a0-a7 for function arguments, a0-a1 for return values sp, stack pointer, ra return address s0-s11 saved registers t0-t6 temporaries zero 9/14/17 49