Project Number 288008 D 8.4 Workshop Report Version 2.0 30 July 2014 Final Public Distribution Denmark Technical University, Eindhoven University of Technology, Technical University of Vienna, The Open Group, University of York Project Partners: AbsInt Angewandte Informatik, Eindhoven University of Technology, GMVIS Skysoft, Intecs, Technical University of Denmark, The Open Group, University of York, Vienna University of Technology Every effort has been made to ensure that all statements and information contained herein are accurate, however the Partners accept no liability for any error or omission in the same. 2014 Copyright in this document remains vested in the T-CREST Project Partners.
DOCUMENT CONTROL Version Status Date 1.0 Collection of materials from first workshop at HiPEAC 22 February 2013 2.0 Inclusion of Madrid ERTS workshop materials 30 July 2014 Page ii Version 2.0 30 July 2014
TABLE OF CONTENTS 1. Introduction... 1 2. Workshop at HiPEAC Conference... 2 2.1 Agenda... 2 2.2 Presentation: Overview of the T-CREST Project... 4 2.3 Presentation: Time-predictable Processor and Network-on-Chip... 7 2.4 Presentation: Time-predictable Memory Hierarchy and SDRAM Controller... 12 2.5 Presentation: Compiler and WCET Analysis Tool Chain... 17 3. Workshop at ECRTS Conference... 20 3.1 Agenda... 20 3.2 Presentation: T-CREST: Time-predictable Multi-Core Architecture for Embedded Systems... 22 3.3 Presentation: Improving the average-case using worst-case aware prefetching... 25 3.4 Presentation: Argo: A Real-Time Network-on-Chip Architecture with an Efficient GALS Implementation... 32 3.5 Presentation: Function Splitting for the Patmos Method Cache... 36 3.6 Presentation: Single-Path Code Generation and Input-Data Dependence... 41 3.7 Presentation: Time-Predictable Caching of Stack Data... 44 3.8 Presentation: Branching in the time-predictable processor Patmos... 49 4. Conclusion... 52 30 July 2014 Version 2.0 Page iii
EXECUTIVE SUMMARY This report provides a summary of two workshops that were carried out by the T- CREST to disseminate information about the technology innovations that have been developed for European software developers and platform providers. The report includes the agendas and presentation materials from each workshop. The workshops were organised in collaboration with other larger events to achieve broader reach and to benefit from the infrastructures provided for organisation of events. Page iv Version 2.0 30 July 2014
1. INTRODUCTION This report provides an overview and documents the materials that were presented at two separate workshops that have been organised by the T-CREST project to create greater awareness of the project results. A first workshop was conducted in the second year of the project at the HiPEAC Conference 1 (European Network of Excellence on High Performance and Embedded Architecture and Compilation) in Berlin on 22 January 2013, where initial development results in the project being presented. A second workshop was conducted at the ECRTS Conference 2 (Euromicro Conference on Real-Time Systems) in Madrid on 10 July 2014, where final technology results were presented and information concerning access to the open source results from the project was provided. The T-CREST partners carried out both workshops in collaboration with other European Commission funded projects. The HiPEAC workshop in 2013 was conducted jointly with the following projects: parmerasa 3 : Multi-core execution of parallelised hard real-time applications supporting analysability; and PROARTIS 4 : Probabilistically analysable real-time systems Each project is addressing related technology challenges for embedded systems development. By collaborating in conducting a joint workshop, the projects were able to establish closer links while providing a broader view of the technology advances being addressed with the support of the European Commission thereby attracting a larger audience. The ECRTS workshop was carried out in collaboration with the following projects: parmerasa: Multi-core execution of parallelised hard real-time applications supporting analysability; and CERTAINTY 5 : Certification of real-time applications designed for mixed criticality The joint workshop with these projects created an opportunity for closer collaboration with the CERTAINTY project while further strengthening ties with parmerasa. The following sections summarises the materials that were presented at each of the workshops. 1 Conference information is available at: www.hipeac.net/conference/berlin 2 Conference information is available at: ecrts.eit.uni-kl.de/ecrts14 3 See www.parmerasa.eu for more information about the parmerasa project. 4 See www.proartis-project.eu for more information about the PROARTIS project. 5 See www.certainty-project.eu for more information about the CERTAINTY project. 30 July 2014 Version 2.0 Page 1
2. WORKSHOP AT HIPEAC CONFERENCE The following sections provide the Agenda and presentations that were utilised for the T-CREST workshop held at the HiPEAC Conference in Berlin on 22 January 2013. 2.1 AGENDA The following agenda was utilised for the workshop conducted as part of the HiPEAC Conference on 22 January 2012, at Berlin, Germany. Agenda Session 1: Introduction of the EU FP7 projects (10:00-11:00) Session chairs: Sascha Uhrig, Technical University of Dortmund Francisco J. Cazorla, Barcelona Supercomputing Center parmerasa Overview Theo Ungerer, University of Augsburg Overview of the T-CREST Project Jens Sparsø, Technical University of Denmark Introduction to PROARTIS Francisco J. Cazorla, Barcelona Supercomputing Center Session 2: Hardware Architectures (11:30-13:00) Session chair: Christian El-Salloum, Technical University of Vienna parmerasa Hardware Architecture Eduardo Quiñones, Barcelona Supercomputing Center T-CREST Time-predictable Processor and Network-on-Chip Jens Sparsø, Technical University of Denmark T-CREST Time-predictable Memory Hierarchy and SDRAM Controller Kees Goosens, Technical University of Eindhoven PROARTIS Hardware Architectural Solutions Francisco J. Cazorla, Barcelona Supercomputing Center Lunch (13:00 14:00) Session 3: Timing Analysis Support (14:00-16:00) Session chair: Jan Reineke, Saarland University PROARTIS WCET Analysis Techniques and Tools Adriana Gogonel, INRIA and Ian Broster, Rapita Systems parmerasa WCET Analysis Tools Haluk Ozaktas, University Paul Sabatier Toulouse and Ian Broster, Rapita Systems T-CREST Compiler and WCET Analysis Tool Chain Peter Puschner, Technical University of Vienna and Gernot Gebhard, AbsInt Session 4: System and Application Software (16:30-17:30) Page 2 Version 2.0 30 July 2014
Session chair: Luis Miguel Pinho, CISTER Research Centre PROARTIS System Software Tullio Vardanega, University of Padua parmerasa Parallelized Avionics and Automotive Software João Fernandes, Honeywell and Sebastian Kehr, Denso Close (17:30) 30 July 2014 Version 2.0 Page 3
2.2 PRESENTATION: OVERVIEW OF THE T-CREST PROJECT Page 4 Version 2.0 30 July 2014
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2.3 PRESENTATION: TIME-PREDICTABLE PROCESSOR AND NETWORK-ON-CHIP 30 July 2014 Version 2.0 Page 7
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2.4 PRESENTATION: TIME-PREDICTABLE MEMORY HIERARCHY AND SDRAM CONTROLLER Note: Some slides numbers are omitted since they were not presented due to time constraints. Page 12 Version 2.0 30 July 2014
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2.5 PRESENTATION: COMPILER AND WCET ANALYSIS TOOL CHAIN 30 July 2014 Version 2.0 Page 17
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3. WORKSHOP AT ECRTS CONFERENCE The following sections provide the Agenda and presentations that were utilised for the T-CREST workshop held at the ECRTS Conference in Madrid on 10 July 2014. 3.1 AGENDA The workshop conducted as part of the ECRTS Conference at Madrid on 10 July 2014, utilised the following agenda. Agenda Introduction to T-CREST, parmerasa and CERTAINTY projects (9:00 10:20) T-CREST: Time-predictable Multi-Core Architecture for Embedded Systems Martin Schoeberl, Technical University of Denmark parmerasa Overview - Objectives and Achievements Theo Ungerer, University of Augsburg CERTAINTY: Certification of Real time applications designed for mixed criticality M. Faugère, THALES Research and Technology Dynamic Budgeting for Settling DRAM Contention of Co-running Mixed- Criticality Applications on Multicores Martin Stigge, Uppsala University Break (10:20 10:40) T-CREST Technologies (10:40 12:40) Improving the average-case using worst-case aware prefetching Jamie Garside, University of York Argo: A Real-Time Network-on-Chip Architecture with an Efficient GALS Implementation Evangelia Kasapaki, Technical University of Denmark Function Splitting for the Patmos Method Cache Stefan Hepp, Vienna University of Technology Single-Path Code Generation and Input-Data Dependence Analysis Daniel Prokesch, Vienna University of Technology Time-Predictable Caching of Stack Data Sahar Abbaspourseyedi, Technical University of Denmark Branching in the time-predictable processor Patmos Wolfgang Puffitsch, Technical University of Denmark Lunch (12:40 13:40) parmerasa Technologies (13:40 15:00) Systematic and Timing-analyzable Parallelization of Industrial Applications Martin Frieb, University of Augsburg Page 20 Version 2.0 30 July 2014
Towards Parallelization of Automotive Legacy Software Sebastian Kehr, Denso Static timing analysis of parallel applications Christine Rochange, University of Toulouse Multi-core architectures for hard real-time systems Milos Panic, Barcelona Supercomputing Center, Spain Break (15:00 15:20) CERTAINTY Technologies (15:20 17:00) Scheduling, mapping and interference analysis for mixed-critical applications on multi-core platforms Nikolay Stoimenov, Eidgenössische Technical University Zürich Composability and scheduling Petro Poplavko, Verimag NoC modeling and computation of worst-case traversal bounds on MPPA B. Dinechin, Kalray Fault modeling at NoC level A. Tschiene, Technical University Braunschweig Static Code-Level Timing and Stack Usage Analysis C. Ferdinand, Absint Close (17:00) 30 July 2014 Version 2.0 Page 21
3.2 PRESENTATION: T-CREST: TIME-PREDICTABLE MULTI-CORE ARCHITECTURE FOR EMBEDDED SYSTEMS Page 22 Version 2.0 30 July 2014
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3.3 PRESENTATION: IMPROVING THE AVERAGE-CASE USING WORST-CASE AWARE PREFETCHING 30 July 2014 Version 2.0 Page 25
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3.4 PRESENTATION: ARGO: A REAL-TIME NETWORK-ON-CHIP ARCHITECTURE WITH AN EFFICIENT GALS IMPLEMENTATION Page 32 Version 2.0 30 July 2014
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3.5 PRESENTATION: FUNCTION SPLITTING FOR THE PATMOS METHOD CACHE Page 36 Version 2.0 30 July 2014
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3.6 PRESENTATION: SINGLE-PATH CODE GENERATION AND INPUT-DATA DEPENDENCE 30 July 2014 Version 2.0 Page 41
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3.7 PRESENTATION: TIME-PREDICTABLE CACHING OF STACK DATA Page 44 Version 2.0 30 July 2014
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3.8 PRESENTATION: BRANCHING IN THE TIME-PREDICTABLE PROCESSOR PATMOS 30 July 2014 Version 2.0 Page 49
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4. CONCLUSION Organising the two workshops were important actions in support of the dissemination objectives of the T-CREST project. The major conference that were selected for the workshop venues included research and industrial representatives from across Europe with many having specific interests in technology advances in platform architectures, as well as technologies that support critical systems and dependability. The audiences also had sufficient technical results concerning the technological innovations from the T- CREST project could be presented in depth. The workshops also provided further opportunities for collaboration with three other European Commission funded projects addressing related technology challenges. Page 52 Version 2.0 30 July 2014