Embedded Processing Portfolio for Ultrasound

Embedded Processing Portfolio for Ultrasound

High performance, programmable platform Processor performance speeds image analysis faster, clearer results Power/size efficient processors enable portability point of care imaging Programmable s enable software upgrades extend product life Complete line of Code compatible devices provides scalable platform to address portable through high-end cart-based systems

TI s Medical Imaging Processors Mission: to enable performance imaging every doctor demands TI Enables TI Solutions Advances in medical processing Latest algorithms Improved image quality More accurate diagnosis Emerging Features Innovative applications safer, non-invasive Real-time diagnosis Product differentiation Portable medical applications Longer battery life Smaller form factor Complete product line of high performance s Software programmable Flexible Adaptable Upgradeable Real-time performance 1.25GHz single core 320GMACs/160GFlops multi-core Medical driven roadmap Low power processors and SOCs Highly integrated Power efficient C64x+ & core OS, GUI, MMI, display High connectivity C64x Sitara C6-Integra Integra Davinci TI Confidential NDA Restrictions 3

Ultrasound system Where fits RF Demodulation B-Mode Color Flow Spectral Doppler Scan Control SOC (+MPU) Scan Conversion Speckle Reduction System Control O/S Display Storage

Multi-core Console Ultrasound Solution SRIOx4 DDR3 Decimation RF Demod. B-Mode Color Doppler Detection Wall Filter FFT Compression Velocity Est Peak/Mean Est Scan Conv Power Est Speckle Red Scan Conv. System Ctrl MMI PACs i/f Mode Switch Cineloop Mgmt Probe C6657 (~3.5w) McBSP DAC AFE 66x (x2) 1GHz P: 32 KB D: 32KB : 512KB MSMC Shared : 4MB PC Beam-former 1 to 4 lanes Multicore Navigator SPI HL 50 PCIe DDR3 64-bit 1.33GHz control data FPGA beam forms and routes data to via SRIO C6657 (2-core) for scan control & back end image processing algorithms. PC performs system control, MMI, interface to PACs Lower power & system cost solution 5

Multi-core Portable Ultrasound Solution SRIOx4 DDR3 DDR SATA DSS USB GEmac Decimation RF Demod. B-Mode Color Doppler Detection Wall Filter FFT Compression Velocity Est Peak/Mean Est Scan Conv Power Est Speckle Red Scan Conv. System Ctrl O/S MMI Linux PACs /f i. Android Mode Switch QT Cineloop Mgmt Probe AFE Beam-former 1 to 4 lanes C6657 (~3.5w) SPI 66x (x2) 1GHz P: 32 KB D: 32KB : 512KB Multicore Navigator HL 50 PCIe McBSP MSMC Shared : 4MB DAC DDR3 64-bit 1.33GHz 32-bit 333/666 MHz DDR 2/3 DM814x AM 3874 (~1w) ARM Cortex -A8 800 MHz P: 32KB D: 32KB : 256KB PCIe Graphics Engine Image Engine Switch Fabric GPMC 16-bit 200 MHz Flash DISPLAY LCD Storage Printer PACs control data FPGA beam forms and routes data to via SRIO C6657 (2-core) implements mid-back end image processing algorithms AM3874 performs system control, MMI, interface to PACs C6657 + AM3874 = ~4w total 6

SOC Based Ultra-Portable Ultrasound Solution DDR McASP SATA DSS USB GEmac Front End Beamforming Detection Compounding B-Mode Color Doppler Speckle Red Scan Conv Wall Filter Velocity Est Power Est. Scan Conv FFT Peak/Mean Est. System Ctrl O/S MMI PACs i/f Mode Switch Cineloop Mgmt Probe AFE FPGA Beam-former RF Demod 32-bit 333/666 MHz DDR 2/3 AM387x DM8148 674x+ 750MHz P: 32KB D: 32KB : 256KB PCIe Graphics Engine ARM Cortex -A8 1GHz P: 32KB D: 32KB : 256KB Switch Fabric Image Engine GPMC 16-bit 200 MHz Flash DAC DISPLAY LCD Storage Printer PACs control data FPGA beam-former + RF demod and routes data to SOC via PCIe ARM Cortex A8 performs system control, MMI, interface to PACs performs back end image processing Video & Graphics h/w accelerator TI Confidential NDA Restrictions 7

GEmac SRIOx4 DDR3 USB DDR SATA DSS Multi-core Based Performance Ultrasound Solution RF Demod. 3D/4D Elastography Speckle Red B-Mode Color Doppler Detection Wall Filter FFT Compression Velocity Est Peak/Mean Est Scan Conv Power Est Scan Conv System Ctrl O/S MMI Linux. PACs i/f. Android Mode Switch QT Cineloop Mgmt Probe AFE Beam-former 1 to 4 lanes SPI 66x (x8) 1GHz P: 32 KB D: 32KB : 512KB Multicore Navigator HL 50 MSMC Shared : 4MB PCIe x2 McBSP DAC DDR3 64-bit 1.33GHz 32-bit 333/666 MHz DDR 2/3 DM814x AM 3874 PCIe ARM Cortex -A8 800 MHz P: 32KB D: 32KB : 256KB Graphics Engine Image Engine Switch Fabric GPMC 16-bit 200 MHz Flash DISPLAY LCD Storage Printer PACs control data FPGA beam forms and routes data to via SRIO C6678 standard mid processing + 3D/4D, Elastography, & Speckle Reduction AM3874 performs system control, MMI, interface to PACs TI Confidential NDA Restrictions 8

HyperLink TeraNet C6655/ C6657 (Sample Now!) New Core 2 Cores @ 1.0GHz nominal (1.4GHz max) C6657 (2 Core), C6655 (1 core) High Performance Fixed & Floating Point Cores Power Optimized Design Target 3.5W for 2 Core, 2.5W for 1 Core implementation (85c case @ 1Ghz) Keystone Multi-Core Architecture Multicore Navigator, TeraNet, Hyperlink Memory Architecture 1MB Local per Core 1MB Multicore Shared Memory (MSM) Boot ROM,DDR3-1600MHz (32-bit) Address Translation & ECC Interfaces 4x RapidIO rev 2.1 (1x4, 2x2, 1x2+2x1) 2 lanes PCIe Gen II 10/100/1000 Mbps Ethernet SGMII ports Universal Parallel Port (16-bit) Muxed with EMIF -16 I2C, SPI, 2x McBSP (Mux), 32 GPIO, 2 x UART, 4x Timers64, Semaphore Other 2x VCP2, 1x TCP3d Multicore debugging (embedded trace per core / chip) 0.8 mm pitch flip chip package 21x21 package Ext Temp Range: -55C to 105C 40nm High Performance Node Smart reflex DDR3-32b C66X Power Management Debug Multicore Navigator C66X Memory Subsystem Multicore Shared Memory Controller (MSMC) Shared Memory 1MB System Elements SysMon EDMA Communications CoProcessors Peripherals & IO SGMII SRIO x4 upp 2x VCP2 TCP3d PCIe x2 I 2 C SPI McBSP EMIF 16 UART TI Confidential NDA Restrictions TI Confidential NDA Restrictions 9 9

TeraNet Shannon (TMS320C6678) Block Diagram Multi-Core KeyStone SoC Fixed/Floating CorePac 8 CorePac @ 1.25 GHz 4.0 MB Shared 320G MAC, 160GFLOP, 60G DFLOPS ~10W Navigator Queue Manager, Packet DMA Multicore Shared Memory Controller Low latency, high bandwidth memory access 3-port GigE Switch (Layer 2) PCIe gen-2, 2-lanes SRIO gen-2, 4-lanes HyperLink 50G Baud Expansion Port Transparent to Software DDR3-64b Multicore Navigator 8 x CorePac Memory Subsystem Power Management Debug Multicore Shared Memory Controller (MSMC) Shared Memory 4MB System Elements SysMon EDMA Hyper Link 50 Network CoProcessors IP Interfaces SGMII Peripherals & IO SRIO x4 TSIP 2x Crypto Packet Accelerator GbE Switch PCIe x2 I 2 C SPI SGMII EMIF 16 UART 10

DM8148 Processor Cores ARM Cortex A8 (MPU) up to 1 GHz C674x Floating Point Core up to 750 MHz Memory ARM: 32KB I-Cache, 32KB D-Cache, 256K : 32KB I-Cache, 32KB D-Cache, 256K Two DDR-800 Controllers Coprocessors/Subsystem HD VICP 2.0 Accelerator at 320 MHz Real-Time HD Encode /Decode 3D Graphics engine Display Subsystem Peripherals Gigabit EMAC Switch USB 2.0 Ctlr/PHY x 2 PCIe 2.0 SATA 3.0Gbps DDR3 800 x2 SD/SDIO x3 McASP x6, McBSP SPI, GPIO, I2C, UART, DCAN Power Total Power Typical <4 W Package 23x23, 0.8mm pitch, 684 ball BGA Via Channels enable low cost design rules -- 4 mil traces and 10/20 mil escape vias DM8148 Fixed/ Floating point C674x Core Peripherals PCIe McASP x6 SPDIF McBSP Memory Interfaces DDR3 x2 SDIO /SD x3 Switched Central Resource (SCR) I2C/ SPI x4 Async EMIF/ NAND ARM microprocessor ARM Cortex A8 TM UART x6 SATA2 DCAN x2 HD Video Coprocessor (x1) USB 2.0 x2 3D Graphics Engine GPIO GMAC Switch Display On-Screen Display Resizer Video I/O SD DAC (x2) HDMI PHY HD Video I/O (x2) Back to: DM roadmap product positioning

Using s & SOCs in Ultrasound Systems TI s C6678 with new floating point core provides high performance signal processing capabilities at low power C6657 dual core can perform processing for mid-range system Upgrade to 4 or 8 core C6674/C6678 for more advanced algorithms s are well suited for processing such as: B-Mode (Detection, Compression) Color (Wall Filter, Velocity & Power estimation) Doppler (FFT, Peak Mean estimation) Scan Conversion 3D/4D, Elasto-graphy, Speckle Reduction Combining an FPGA for beam formation/routing and Sitara ARM SOC s can provide a flexible, low-power solution for digital ultrasound systems. High Level Language Eclipse development environment On-Chip DMA & Multicore Navigator for data movement. McBSP ports address I/O needs for CW Doppler & audio

Using s & SOCs in Portable Ultrasound Systems TI s low-power Davinci SoCs allow flexibility on the back-end SoC for various display options, image filtering and target identification on a single chip: C674x (fixed-/floating-point s) Cortex-A8 for peripheral and communications control 3D graphics engine for rich UIs Rich display sub-system for multiple HD displays HD video encode/decode accelerators (Davinci devices only) High system connectivity with peripherals such as: Gigabit ethernet PCIe USB SATA SPI/GPIOs/more

Complete & ARM MPU Software Solutions by TI Scalable BSP/SDK Releases LINUX Periph Libraries and Stacks SITARA ARM MPU C6-INTEGRA ARM MPU + Middleware/ Frameworks Multimedia Codecs Common IDE/ Tools DAVINCI ARM MPU + + Video Accelerator Engine Example SW & Demos Instant Expert SW Development Kits FREE Development license to use our Linux, Android, or WinCE Board FREE Support Packages (BSP) / Software Development Kits (SDK) * For use on our ARM, ARM+, and ARM++Multimedia Processors * Each release seamlessly and scalable works across all products

Medical Software Toolkit 2.0 Optimized implementations of commonly used C64x+/ processing blocks Source Code: Ultrasound: B-mode (Envelop Detection & Compression) DAS Receive Beam-forming Doppler Processing RF Demodulation and Decimation Scan Conversion Optical Coherence Tomography Cubic Spline Interpolation Optimized FFT 3D Rendering Affine Warp Request download at: http://focus.ti.com/docs/toolsw/folders/print/s2meddus.html

Medical Ultrasound Demo (MIDAS) Rev. 2 All B-Mode, Color Flow, and Scan Conversion Processing on OMAP3530! ARM Cortex A-8 600MHz C64x+ 430MHz DDR Ensemble Aggregation Runs Linux O/S User Interface, Control, Display Runs Ultrasound Algorithms Envelope Detection B-mode Estimation Wall Filter Color Flow Compression Flow Estimation Scan Conversion Scan Conversion Tissue Flow & Blending TI OMAP3530 Mistral EVM Display 640x480 @20fps Input Data Size (Post RF Demod) Scan Lines Samples/ Scan Line Bytes/ Sample Ensemble kb/ frame B-mode + Scan Conversion 128 416 4-208 Loading ARM ms/fm B-Mode 19% 6% 15 Color Flow + Scan Conversion 64 256 4 8 512 B-Mode+ Color Flow 46% 21% 28 https://gstreamer.ti.com/gf/project/med_ultrasound/

Medical Imaging Value Proposition New & innovative algorithms in software Improved image quality & emerging features Field upgrades, Flexibility, Adaptive coding Deterministic signal processing architecture Supports latest real-time O/S for predictable & reliable performance Portable imaging applications Low power SOC s replace PC. (+ARM, Graphics, Video accl ) Longer battery life. Smaller form factor. Scalable platforms: Portable Value Premium Code compatible family of products R&D Savings Reuse (code, hardware, development environment) No hardware spins, eco s, & timing closure bottlenecks Time to Market State of the art development tools: (Compilers, trace, emulation) Develop & debug in high level language Imaglib & Medical Software toolkit, 3d parties Roadmap & Product continuity Long term supplier, Full product line: Analog,, Power, etc 10GHz-320GMACs/160GFlop s today, Application support (Field, Factory, domain white papers & app notes) C64x+ Sitara C6-Integra Davinci TI Confidential NDA Restrictions 17