Architecture and Specification Trends Michael Abraham (mabraham@micron.com) Applications Engineering Manager Micron Technology, Inc. August 2009 1
Abstract As continues to shrink, page sizes, block sizes, and ECC requirements are increasing while data retention, endurance, and performance are decreasing. These changes impact systems including random write performance and more. Learn how to prepare for these changes and counteract some of them through improved block management techniques and system design. This presentation also discusses some of the tradeoff myths for example, the myth that you can directly trade ECC for endurance August 2009 2
: Shrinking Faster Than Moore s Law 200 ion (nm) 100 80 Logic DRAM Resoluti 60 40 Micron 32Gb (34nm) 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 Semiconductor International, 1/1/2007 August 2009 3
Memory Organization Trends Over time, block size is increasing. Larger page sizes increase sequential throughput. More pages per block reduce die size. 4,194,304 1,048,576 262,144 65,536 16,384 4,096 1,024 256 64 16 Block size (B) Data Bytes per Page Pages per Block August 2009 4
Consumer-grade : Endurance and ECC Trends Process shrinks lead to less electrons per floating gate. ECC used to improve data retention and endurance. To adjust for increasing RBERs, ECC is increasing exponentially to achieve equivalent UBERs. For consumer applications, endurance becomes less important as density increases. 30 100,000 En ndurance (C Cycles) 10,000 25 20 15 10 5 ECC (bits s) 1,000 2005 Future 0 SLC Endurance MLC-2 Endurance MLC-2 ECC SLC ECC August 2009 5
Myth: More ECC Extends Block Endurance Block endurance is how long a block is usable before program or erase status failures occur. Applying more ECC than required does not automatically extend the block endurance. devices are configured to trigger program and erase status failures for a specific, fixed ECC value predetermined at the factory to meet qualification requirements. Applying extra ECC does not change these predetermined d thresholds, h which h means that t program and erase status failures begin to occur at the same cycling intervals regardless of the amount of ECC applied. August 2009 6
Larger Page Sizes Improve Sequential Write Performance For a fixed page size, write throughput decreases as process shrinks vendors increase the page size to compensate for slowing array performance Write throughput decreases with more bits per cell 80 60 SLC 40 20 MLC-2 MLC-3 0 512 2048 4096 8192 2048 4096 8192 4096 8192 Data Bytes per Page Sequential Programming Throughput (MB/s) August 2009 7
More Pages Per Block Affect Random Write Performance The block copy time is the largest limiting factor for random write performance. As block copy time increases, random performance decreases. Number of pages per block is the dominant factor. Increase of tprog is the next largest factor. Increase in I/O transfer time due to increasing page size (effect not shown below) is also a factor. Some card interfaces have write timeout specs at 250ms, which means that block management algorithms manage partial blocks. 500 SLC 400 300 200 100 0 MLC-2 32 / 30064 / 25064 / 300128 / 250 128 / 600128 / 900256 / 900 256 / 1200 Pages per Block & tprog (typ) MLC-3 192 / 2000+ Block Copy Time (ms) August 2009 8
Interface The interface is increasing in throughput Allows better utilization of I/O channels higher h bandwidth Immediately useful for single die read performance Modest improvement for write performance with multiple die Important for SSDs, enterprise applications Reduces I/O channels August 2009 9
Interface Trends Max Throughput Interface Standard (x8) (MB/s) No standard 40 ONFI 1.0 Async (12/06) 50 ONFI 2.0 Sync (2/08) 133 ONFI 2.1-2.2 Sync (1/09, 9/09) 200 Toggle Mode (not published) 133 ONFI 3.0 Sync 400
The ONFI Advantage Single Channel Package Dual Channel Package MB B/s 900 800 700 600 500 400 300 200 100 0 40 80 167 333 200 400 Target 800 Target 400 ONFi 1.0 ONFi 2.0 ONFi 2.1 ONFi 3.0 3.0 Async Synchronous Supports simultaneous read, program, and erase operations on multiple die on the same chip enable since ONFI 1.0 Only industry-standard interface capable of 200MB/sec data rate from a single die Two independent channels in a single package (doubles the bandwidth) In volume production today Headroom for 400MB/sec and beyond Work has already begun on ONFI 30 August 2009 11
A-Data Afa Technologies Alcor Micro Aleph One Anobit Tech. Apacer Arasan Chip Systems ASMedia Technology ATI Avid Electronics BitMicro Biwin Technology Chipsbank Cypress DataFab Systems Data I/O Datalight Denali Software ENE Technology Entorian FCI FormFactor Foxconn Fresco Logic Fusion Media Tech Genesys Logic Hagiwara Sys-Com HiperSem Hitachi GST Hyperstone InCOMM Indilinx Inphi Intelliprop ITE Tech Jinvani Systech Kingston Technology Lauron Technologies Lotes LSI Macronix Marvell Mentor Graphics Metaram Moai Electronics Molex NVidia Orient Semiconductor P.A. Semi Powerchip Semi. Power Quotient International Prolific Technology Qimonda Sandforce Seagate Shenzhen Netcom Sigmatel Silicon Integrated Systems Silicon Motion Silicon Storage Tech Silicon Systems STEC Skymedi Smart Modular Tech. Solid State System Super Talent Electronics Synopsys y Tandon Tanisys Telechips Teradyne, Inc. Testmetrix Transcend Information Tyco UCA Technology University of York Virident Systems WinBond August 2009 12 Members
Improving System Performance System performance is increased by adding more channels or more die per channel. Ignoring effects of ECC and block management algorithms, total throughput is either array or I/O throughput limited. Controller August 2009 13
800 700 SLC 4KB 2-plane Throughput Example: Async vs. Sync Interface 800800 800 800 600 /s) Perf formance (MB/ 500 400 300 200 100 0 480 400 400 400 448 400 136 160 240 160160 200 200 200 224 68 80 152 160160 224 80 80 120 34 40 76 112 200 40 40 38 76 80 80 112 1 2 56 4 8 19 38 112 40 40 28 56 1 2 4 8 # of Die per Channel 1 2 4 8 1 1 2 4 8 4 # of Channels August 2009 14
800 700 MLC 4KB 2-plane Throughput Example: Async vs. Sync Interface 800 800 704 600 /s) Perf formance (MB/ 500 400 300 352 352 400 400 200 100 0 120 160 160160 176 176 200 200 60 80 80 80 30 40 40 40 88 1 2 4 8 1 2 4 8 # of Die per Channel 256 160 112 28 56 128 14 28 56 80 32 64 128 7 14 28 40 16 32 64 8 16 32 64 1 2 4 8 1 2 4 8 1 4 # of Channels August 2009 15
Conclusions Larger block sizes to become more difficult to manage Page size doubles increasing sequential performance while reducing random performance to compensate for overall slower array throughput ECC increases to compensate for data retention and endurance; even still endurance is decreasing for consumer memory 2bpc MLC has a lower manufacturing cost per bit as long as it is on a smaller process node than 3bpc MLC memory and it fits more customer applications! Pages per block increasing to reduce die size Interface performance increasing to open up a whole new market enterprise solutions while helping improve SSD performance ONFI provides a proactive, scalable interface for the future with broad industry support August 2009 16
Questions? August 2009 17
About Michael Abraham Manager of Micron s Applications Engineering group BS B.S. in Computer Engineering i from Brigham Young University Technical representative for Micron in ONFI and JEDEC for Key role in defining and standardizing the highspeed, synchronous DDR interface within Micron and at ONFI 2007-2009 2009 Micron Technology, Inc. All rights reserved. Products are warranted only to meet Micron s production data sheet specifications. Information, products and/or specifications are subject to change without notice. All information is provided on an AS IS basis without warranties of any kind. Dates are estimates only. Drawings not to scale. Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. August 2009 18