Lab 0: Tutorial on Xilinx Project Navigator & ALDEC s Active-HDL Simulator CSE 591: Advanced Hardware Design and Verification Assigned: 01/05/2011 Due: 01/19/2011 Table of Contents 1 Overview... 2 1.1 Grading... 2 1.2 Supplementary Material... 3 1.3 General Online Reading... 3 2 Tutorial on Working with Xilinx Project Navigator... 4 2.1 Running Xilinx Project Navigator... 4 2.2 Creating a new project... 4 2.3 Entering the target device properties... 5 2.4 Creating a new Verilog file for the project... 5 2.5 Copy and Paste the following code:... 9 2.6 Checking the Syntax... 10 2.7 Analysis of the generated logic... 11 2.8 Running Synthesis... 12 3 Creating a Test Bench for our Design... 13 4 Simulating our design using Xilinx s isim... 16 5 Analyzing the results from our Simulation... 17 6 Using the Xilinx Spartan-3 FPGA... 19 7 Now you its your turn!... 25
1 Overview The following lab is inted to act as a primer for the Xilinx ISE toolset. We will be going through the process of creating a very simple logic design, testing it, and implementing it in an actual FPGA Platform. 1.1 Grading Question 0: Create Positive Edge Detect and Negative Edge Detect Logic -1 Point Incorrect Design for Positive Edge Detect -1 Point Incorrect Test Bench for Positive Edge Detect 4-1 Point Incorrect Design for Negative Edge Detect -1 Point Incorrect Test Bench for Negative Edge Detect -4 Point if not attempted Question 1: Design a Toggle Flip-Flop -2 Points for incorrect implementation 4-4 Points if not attempted Question 2: Create a Test-Bench and validate your Toggle Flip-Flop -1 Points for failing to test each condition shown in the waveform 2-2 Points if not attempted Question 3.a: Create a 1-Bit Comparator -1 Points if direction of assignment was incorrect. -1 Points for incorrect reg or wire usage. 4-4 Points if not attempted Question 3.b: Create a Test-Bench for the 1-Bit Comparator and validate the comparator -1 Points for failing to test all 4 possible cases. -1 Points for not using # delays 4-4 Points if not attempted Question 3.c: Create a 4-Bit Comparator -1 Points for not instantiating 4 separate 1-bit comparators. 4-1 Points for incorrect bit width declarations -4 Points if not attempted Question 3.d: Create a Test-Bench for the 4-Bit Comparator and validate the comparator -2 Points for not testing all 256 possible conditions. 4-4 Points if not attempted Question 4: Simulate code and record results observed -1 Points per incorrect entry into table of expected results. -1 Points per incorrect # delay usage 4-2 Points if not attempted Question 5: Completed LED Blink FPGA Implementation 1-1 Point if not attempted 2 P age
1.2 Supplementary Material ISE Quick Tour: o https://xilinx.webex.com/xilinx/lsr.php?at=pb&sp=ec&rid=31975327&rkey=b2cb97cbbb0026e3 ISE In-Depth Tutorial o http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_2/ise_tutorial_ug695.pdf Aldec Active-HDL 8.3 o http://www.aldec.com/products/trainings.aspx?productid=f8ee0c96-cd00-4b24-812cc2935fe143ae Kyle s You-Tube stuff (for those of you who love my melodic velvety tones!) o http://www.youtube.com/watch?v=_4cezm5cxbo (Active HDL Tutorial - Part 1) o http://www.youtube.com/watch?v=9fxytv67ls8 (Active HDL Tutorial - Part 2) 1.3 General Online Reading http://www.asic-world.com/verilog/ http://www.verilog.com/ http://www.sutherland-hdl.com/online_verilog_ref_guide/vlog_ref_top.html http://www.doulos.com/knowhow/verilog_designers_guide/ http://electrosofts.com/verilog/ 3 P age
2 Tutorial on Working with Xilinx Project Navigator Please follow the below steps to setup the Xilinx Project. 2.1 Running Xilinx Project Navigator Go to shortcut to the ISE project Navigator on the desktop or All Programs > Xilinx > ISE > Project Navigator. 2.2 Creating a new project Go to File > New Project > Enter the name of the project and the location as shown below and click next: 4 P age
2.3 Entering the target device properties We need to mention the FPGA device for which the code is being used. Since we would be working on Spartan 3 boards put the parameters as shown below. 2.4 Creating a new Verilog file for the project Click on the new source button and select Verilog module from the list and give a <name> (we are making a Positive Edge Detection circuit) for your Verilog file which will be saved in the format PED.v. Click next to proceed. 5 P age
In the New Source Wizard Define Module screen you can name the signal and assign those directions and vector width. This information is used by the tool to automatically write the module for you. It is recommed that you learn to write the module yourself rather than taking the help of tool. After you have entered the above information click next and the New Source Wizard Summary window will appear. Click Finish. 6 P age
The project will be created now and click yes on the screen as shown below: The file created by you will be shown by the tool, click next to proceed to summary of project window. 7 P age
Click finish in the Project Summary window. You can see the project being created with some default code created by the tool. 8 P age
2.5 Copy and Paste the following code: `timescale 1ns / 1ns //indicates that he simulation unit is 1 ns and the resolution is 1 ns. //----------------------------------------------------- // Design Name : ped // File Name : ped.v // Function : Positive Edge Detection // Coder : HEMANSHU ABBEY //----------------------------------------------------- module ped (//Port Declarations SIG, // Signal input to be monitored CLK, // Synchronous Clock Input RESET_B, // An active low input which resets the logic to a default state. PULSE // A single clock wide pulse to indicate that a Positive edge has been detected. ); //Port Directions //-----------Input Ports--------------- input SIG, CLK, RESET_B; //-----------Output Ports--------------- output PULSE; //------------Signal Declarations/Internal Variables-------- wire inv; wire PULSE; reg q; //-------------Code Starts Here--------- always @ (posedge CLK or negedge RESET_B) if (~RESET_B) q <= 1'b0; else q <= SIG; assign inv =!q; assign PULSE = SIG & inv; module Note: Please try to understand the code by drawing waveforms for it. Also try to write the code for negative edge detection on your own. 9 P age
2.6 Checking the Syntax Double click it to run the process and it will show a green correct sign if the process is completed successfully. NOTE: It is very important that you learn to debug your own code. If you have some errors/warnings please try to think what is going wrong and rectify it. 10 P age
2.7 Analysis of the generated logic Under Synthesize tab click on View RTL schematic as shown below: Double click on the green box which is your block level diagram for the code to get the actual circuit level implementation by the tool. 11 P age
2.8 Running Synthesis Once we are sure that we do not have any errors in the code we can run the complete synthesize to make sure our code is practically implementable. Right click on the synthesize tab and select Rerun all and make sure that you see the process being completed successfully. Once the synthesize process finishes it creates a *.bit file by default in the project directory. This file is used to program the FPGA on the board. How we will program a FPGA will be introduced in a later stage of the course. The next section will focus on writing a test bench for the code and observing the waveforms. 12 P age
3 Creating a Test Bench for our Design A test bench is a virtual environment used to verify the correctness or soundness of a design or model. For writing test benches it is important to have the design specification of "design under test" or the DUT. First step of any testbench creation is building a dummy template. This template will contain your DUT and the necessary stimulus. Most of your stimulus will come from procedural blocks, e.g. initial and always. So, we can delay the declare and inputs to DUT as reg and outputs from DUT as wire for now. Note that there is no port list for the test bench. 1. Right click on the PED.V file and select new source as shown below 13 P age
2. Select Verilog Text Fixture and name the file as shown below and click on Next > and Finish on the subsequent screens. 3. A default code is created by the Xilinx tool. It is recomm learning to write the code without the help of tool. 14 P age
Select and Delete the default code and replace it with the code shown below and save the file. (It is saved in the project directory created by you) tb/tb_ped.v `timescale 1ns / 1ns //----------------------------------------------------- // Design Name : ped_tb // File Name : ped_tb.v // Function : Testbench for positive edge detection logic // Coder : HEMANSHU ABBEY //----------------------------------------------------- module TB; //------------Signal Declarations/Internal Variables-------- reg sig, clk, reset_b; wire pulse; // Instatiation of ped module and passing of test vectors ped ped0 (.SIG(sig),.CLK(clk),.RESET_B(reset_b),.PULSE(pulse)); //-------------Code Start----------------- initial clk <= 1'b1; reset_b <= 1'b0; sig <= 1'b0; forever #50 clk <= ~clk; initial @(posedge clk) reset_b <= 1'b0; sig <= 1'b0; @(posedge clk) reset_b <= 1'b0; sig <= 1'b0; module @(posedge clk) # 75 reset_b <= 1'b1; sig <= 1'b0; @(posedge clk) reset_b <= 1'b1; sig <= 1'b0; @(posedge clk) reset_b <= 1'b1; sig <= 1'b1; @(posedge clk) reset_b <= 1'b1; sig <= 1'b0; @(posedge clk) reset_b <= 1'b1; sig <= 1'b1; @(posedge clk) reset_b <= 1'b1; sig <= 1'b1; #100; $stop; NOTE: Try understanding the testbench and its functioning. It s giving a sequence of events. Try making waveforms as per testbench to boost your understanding. 15 P age
4 Simulating our design using Xilinx s isim We will not be using Xilinx as a simulator beyond this lab. But, it is good to get familiar with the different types of simulators. Click the Simulation radio button in the Design window of the ISE Project Navigator. Expand the ISim Simulator tree to reveal Behavioral Check Syntax and Simulate Behavioral Model. Right Click on Simulate Behavioral Model select Run. 16 P age
5 Analyzing the results from our Simulation We have implemented a positive edge detection circuit which has a output PULSE which goes high whenever a positive edge is detected in the input sig. We can see from the simulated waveforms that whenever sig goes high the pulse signal also goes high for a clock period. Going ahead if sig stays high then pulse will not respond. This confirms that we have indeed made a positive edge detection and not a level detection circuit. Also we should note that till reset_b is active low the circuitry does not respond to variations in input (Asynchronous reset approach) Similarly try making negative edge detection logic. This concludes the tutorial on workflow with tools and basic coding and testbench approach. Question 1: Using correct Verilog Syntax (Module Declaration, I/O Declaration, Register Declaration, proper use of always blocks, etc ), design a Toggle Flip-Flop. Port Name Port Direction Port Width Description TOGGLE Input 1-bit A single clock-wide pulse to indicate that the current state of the toggle flop should be inverted. CLK Input 1-bit Synchronous Clock Input RESET_B Input 1-bit An active low input which resets the logic to a default state. T_OUT Output 1-bit The current state of the toggle flop. Question 2: Design a Test-Bench to implement the following waveforms 17 P age
You need to generate a working test-bench and Xilinx isim waveforms for this question. tb/tb_tff.v Initial CLOCK = 1'b1; RESET = 1'b0; DATA = 1'b0; forever #50 CLOCK <= ~CLOCK; initial @(posedge CLOCK) RESET = 1'b0; DATA = 1'b0; @(posedge CLOCK) RESET = 1'b0; DATA = 1'b0; module @(posedge CLOCK) # 75 RESET = 1'b1; DATA = 1'b0; <FILL YOUR CODE HERE> @(posedge CLOCK) RESET = 1'b1; DATA = 1'b0; #200; $stop; 18 P age
6 Using the Xilinx Spartan-3 FPGA This is a general tutorial aimed at getting you familiarized with working on Xilinx Spartan-3 FPGA board. The tutorial is a walkthrough the process of burning the code on FPGA. It is recommed that you go through the tutorial pasted earlier. 1. Open the Xilinx Project Navigator and create a new project for the Xilinx Spartan-3 FPGA. 2. Create a new Verilog file with the following code or you can create a dummy Verilog file and then copy paste the below code. `timescale 1ns / 1ns module blink_led ( CLK, // System Clock RESET, // Active low, asyn reset LED_OUT // LED outputs to indicate locked and unlocked state ); //-----------Input Ports---------------------------- input CLK, RESET; //-------------Output Ports---------------------------- output LED_OUT; //-------------Input ports Data Type------------------- wire CLK, RESET; //-------------Output Ports Data Type------------------ reg LED_OUT; integer counter = 0; always @(posedge CLK or posedge RESET) if(reset) counter <= 1'b0; LED_OUT <= 1'b0; else if(counter > 250000000) if (counter == 500000000) counter <= 1'b0; LED_OUT <= 1'b0; else counter <= counter + 1'b1; LED_OUT <= 1'b1; else counter <= counter + 1'b1; LED_OUT <= 1'b0; module 3. Run synthesize to verify there is no syntax errors. 4. Now go to User Constraints > Create Timing Constraints as shown below. Click yes 19 P age
5. On the next screen give the clock frequency of 20ns. ( The clock on board is 50 MHz) Save the changes. 6. Click ok to proceed as shown below 20 P age
7. Close the window for Device Architecture 21 P age
8. Now you would be able to see the following screen. Drag and drop your signals on the spreadsheet as shown below. You need to map only 3 signals here as CLK at T9, LED_OUT at P11 and RESET at L14 You need to map your signals to the actual pins on FPGA board. This process is known as creating the UCF (User Constraint File) for the project. The file is saved by the name blink_led.ucf in your project location. If for some reasons you are not able to create the file using the tool then copy paste the below code in notepad and save it as blink_led.ucf (Not as a txt). NET "CLK" TNM_NET = CLK; TIMESPEC TS_CLK = PERIOD "CLK" 20 ns HIGH 50%; #PACE: Start of Constraints generated by PACE #PACE: Start of PACE I/O Pin Assignments NET "CLK" LOC = "T9"; NET "LED_OUT" LOC = "P11"; NET "RESET" LOC = "L14"; #PACE: Start of PACE Area Constraints 22 P age
9. Once the UCF is created you need to run Implement Design and then run the Generate Programming File. This created the bit-stream for your code that the FPGA understands. It is created by the extension *.bit. Now click on the Configure Target Device, keep the default settings and click finish as shown. 10. Now you need to assign the bit file to your FPGA (1 st device) as shown below: 23 P age
Select the file and click open. You need not assign file for the 2 nd device, so click cancel in the next screen and then click ok on the below screen: 11. Now right click on the 1 st Device and program the FPGA 12. If for some reason you are not able to see the below screen. Try programming again or check your bit stream generation process. 24 P age
13. Your code is functional now. You will see LED P11 blinking with around 5 sec gaps. Press the RESET and the LED should turn off till the duration RESET has been pressed. Now try reducing the counter limits as 25000000 and 50000000 and re-run the complete process. What do you observe? Can you explain what is happening here? 7 Now you its your turn! Question 3: a) Using Verilog, implement a 1-bit comparator using only inverters and 2-input NAND gates. This comparator has 2 1-bit inputs. The output is 1 if and only if both inputs are the same. The input data lines of the comparator should be labeled starting with A, B and the output with SAME. This file should be called rtl/cmp_1bit.v. b) Use Xilinx s isim to exercise the 1-bit version of your comparator over all possible combinations of inputs. This will require you creating a test-bench that instantiates the comparator and using a procedural block to provide stimulus. This file should be called tb/tb_cmp_1bit.v. c) Using Verilog, create a 4-bit comparator using the 1-bit comparator you created above. The input data lines of the comparator should be labeled starting with A[3:0] and B[3:0] and the output with SAME. This file should be called rtl/cmp_4bit.v. d) Use Xilinx s isim to exercise the 4-bit version of your comparator over all possible combinations of inputs. This will require you creating a test-bench that instantiates the comparator and using a procedural block to provide stimulus. This file should be called tb/tb_cmp_4bit.v. Question 4: Referring to the Chapter 1 Section 7 of the Chu. Text, develop a Verilog test bench that uses the following test vectors to verify our 4-bit comparator and indicate what the expected values for Y should be: Vector @ Simulation Time A B SAME 0 0 ns 0 0? 1 100 ns 7 15? 2 200 ns 12 3? 3 300 ns 3 3? 4 301 ns 12 12? 5 302 ns 4 bx 4 bz? This file should be called tb/tb_cmp.v. Note: I would use a timescale of 1 ns / 1 ns. Simulate this test bench and tell me what the values are for the SAME. 25 P age
8 Submission Process Submit the TA the RTL, TESTBENCH and SIMULATION output from Xilinx isim. o It must be contained in a zip file. Rename the zip file to filename.piz. o The contents of the file are as follows: rtl/ped.v. rtl/ned.v. rtl/tff.v rtl/cmp_1bit.v. rtl/cmp_4bit.v. tb/tb_tff.v tb/tb_ped.v tb/tb_ned.v tb/tb_cmp_1bit.v. tb/tb_cmp_4bit.v. tb/tb_cmp.v. doc/q4.txt syn/blink_led_tut.bit syn/blink_led_tut.ucf o The zip file must be named exactly as follows: CSE591_S12_LAB_0.<student_id>.<First_Name>_<Last_Name>.piz o It must be e-mailed to the following e-mail accounts: Kyle.Gilsdorf@asu.edu (Kyle Gilsdorf) Due to the number of students in this class, failure to submit the lab in the correct format will result in it being marked as late (5% off final grade, per day late) until the lab is submitted in the correct format. 26 P age