To study Chapter 2: CSCI 402: Computer Architectures Instructions: Language of the Computer (1) Fengguang Song Department of Computer & Information Science IUPUI Contents 2.1-2.3 Introduction to what is instruction operation operand1 operand2 What operations provided by computer hardware How to store the operands in computer hardware 2 1
First look at an example of what is instruction 3 High Level Language à Machine Language 32 bits per instruction Compiler 2
Definition of Instruction Are commands sent by a program to hardware A computer speaks its own language Words of the computer language are called instructions Instruction Set: The vocabulary of all commands understood by a given computer architecture Different computers have different instruction sets but most of their aspects are common (just like dialect) Reason: built from same technology and provide same ops E.g., MIPS, ARMv7, ARMv8 (2013, 64bits), Intel X86 In history, computers used simple instruction sets. Why? Reason: It is simple to build the hardware and the compiler All are designed to support a few very basic operations Many modern computers still use simple instruction sets add c, a, b 000000 10001 10010 01000 00000 100000 5 Operations Provided by Computers Data Movement Load (from memory) Store (to memory) memory-to-memory move register-to-register move input (from I/O device) output (to I/O device) push, pop (to/from stack) Arithmetic Shift Logical Control (Jump/Branch) Subroutine Linkage Interrupt Synchronization String Graphics (MMX) Integer or FP Add, Subtract, Multiply, Divide shift left/right, rotate left/right not, and, or, set, clear unconditional, conditional call, return trap, return test & set (atomic r-m-w) search, translate parallel subword ops (4 16bit add) 6 3
Top 10 80x86 Instructions Rank instruction Integer Average Percent total executed 1 load 22% 2 conditional branch 20% 3 compare 16% 4 store 12% 5 add 8% 6 and 6% 7 sub 5% 8 move register-register 4% 9 call 1% 10 return 1% Only 10 instructions! Total 96% Simple instructions dominate instruction frequency 7 What Conclusion Can We Get? 96%? Probably we just need hardware to support those simple instructions Since they dominate the number of instructions executed Eventually, the following 12 instructions need to be supported: load store add subtract move register-register and shift compare equal, compare not equal branch jump call return 8 4
Characteristics of Instructions Much more primitive than higher level languages e.g., there is no sophisticated control flow like, for, while, switch, etc. Very restrictive Only has few basic arithmetic operations (see previous slide) Design goals: Maximize performance, minimize cost, and reduce design time This course will focus on the MIPS instruction set A common format Similar to many architectures developed since the 1980's E.g., NEC, Nintendo, Silicon Graphics, Sony PS, and the popular ARM 9 The MIPS Instruction Set? https://en.wikipedia.org/wiki/mips_instruction_set Used as examples throughout the textbook Developed by MIPS Technologies (www.mips.com) In 2013, MIPS Technologies was acquired by Imagination Technologies Occupies a large share of embedded system market E.g., consumer electronics, network/storage equipment, cameras, printers Such as Windows CE devices, Sony PlayStation A typical design of many modern ISAs See MIPS Reference Green Card Its PDF file is on CS402 course website too 10 5
Instruction Set Architecture (ISA) ISA serves as the interface between software and hardware. software instruction set hardware It provides the mechanism by which software tells hardware what should be done. Based on ISA High level language code : C, C++, Java, Fortan, compiler Assembly language code: architecture specific statements assembler Machine language code: architecture specific bit patterns 11 Classifying ISAs (4 Categories) Using implicit Operands 1. Accumulator (before 1960) //The earliest machines 2. Stack (1960s to 1970s) //HP calculator Using explicit Operands??. Memory-Memory (1970s to 1980s) [no longer exists] 3. Register-Memory (1970s to present) //Intel 80x86 4. Register-Register (or Load/Store) (1960s to present) add Ra Rb Rc: Ra Rb + Rc add A: acc acc + mem[a] add: tos tos + next add A B: mem(a) mem(a) + mem(b) add R A: R R + mem[a] Dominant since 1980 s: RISC arch and ARM Some registers may be general purpose, or some may be restricted to special purposes 12 6
Why We Need General-Purpose Registers? Since 1975, all machines use general purpose registers Advantages of using registers: Registers are faster than memory (1 cycle vs 100 s cycles) Registers are easier and more flexible than stack or accumulator for a compiler to use e.g., (A*B) (C*D) (E*F) can do multiplies in any order vs. stack Registers can store variables So that memory traffic is reduced, program is sped up (since registers are faster than memory) Code Density improves (since register name has fewer bits than memory location) only 5 bits vs 32- or 64-bits memory address, on MIPS 14 First, Look at Arithmetic Operations Every computer must perform arithmetic E.g., on MIPS, add and subtract have 3 operands 2 sources and 1 destination add a, b, c //a ß b + c All arithmetic operations have this format Exactly 1 operation and 3 varaibles Q: how to compute b+c+d+e? a = b+c a = a +d a = a + e Why always 3 operands? Computer Architects Design Principle #1: Simplicity favors regularity Regularity makes implementation simpler à simpler hardware Then, simplicity enables higher performance at lower cost 15 7
An Example of MIPS Operations E.g., A line of C code with 5 variables. f = (g + h) - (i + j); Compiled MIPS code need 3 instructions! add t0, g, h # temp t0 = g + h add t1, i, j # temp t1 = i + j sub f, t0, t1 # f = t0 - t1 16 Operands in Registers Restriction: However, arithmetic instructions must use registers as operands MIPS has a number of 32 32-bit registers Numbered from 0 to 31 Also, 32-bit data is called a word Assembler gives names to these 32 registers Registers $t0, $t1,, $t9 for temporary values Registers $s0, $s1,, $s7 for variables that correspond to C variables in source code Design Principle #2: Smaller is faster The reason for having only 32 registers Too many registers, access time will be longer versus main memory: millions of locations 17 8
Operands in MIPS 18 C code: Register Example f = (g + h) - (i + j); Now, suppose g, h, i, j are stored in $s1, $s2, $s3, $s4, f is stored in $s0 Compiled MIPS code become: add $t0, $s1, $s2 add $t1, $s3, $s4 sub $s0, $t0, $t1 19 9
Memory Operands 32 registers are not enough to store user data Must use memory for composite data Such as arrays, structures, dynamically allocated data How to apply arithmetic operations to memory? Must load values from memory into registers firstly Must store result from register to memory 20 Recall: Hexadecimal Numbers Base 16 Is a compact representation of bit strings 4 bits <--> a hex digit 0 0000 4 0100 8 1000 c 1100 1 0001 5 0101 9 1001 d 1101 2 0010 6 0110 a 1010 e 1110 3 0011 7 0111 b 1011 f 1111 Just replace one hexadecimal digit by the corresponding four binary digits, and vice versa. If the length of the binary number is not a multiple of 4, go from right to left. n Example: eca8 6420 n 1110 1100 1010 1000 0110 0100 0010 0000 21 10
Memory Operands (Cont.) Memory is byte addressed That is, each address can identify a byte But a word (=4 bytes) can be stored in 2 different layouts! Big Endian (e.g., our MIPS) Including ARM versions 3 and above, PowerPC, Alpha, SPARC V9, MIPS, PA-RISC, SuperH SH-4 and IA-64 Definition: Most-significant byte stored at least-address of memory 0x AA BB CC DD Little Endian (e.g., Intel and AMD) Definition: Least-significant byte stored at least-address of memory e.g., Intel and AMD systems 22 Example of Endianness Suppose a 32-bit hexadecimal value of 0x12 34 56 78 is stored in a 32-bit word in the byte location 184. How is it stored? Big Endian Little Endian Memory Address Value Memory Address Value 184 184 185 185 186 186 187 187 Definition: Most-significant byte stored at least-address of memory Definition: Least-significant byte stored at least-address of memory 23 11