CSCI 2121 Computer Organization and Assembly Language PRACTICE QUESTION BANK

CSCI 2121 Computer Organization and Assembly Language PRACTICE QUESTION BANK Question 1: Choose the most appropriate answer 1. In which of the following gates the output is 1 if and only if all the inputs are 0? a. AND b. OR c. NAND d. NOR 2. A truth table has 512 rows when complete. The number of input variables that determine the Boolean function of this truth table is a. 512/2 b. 512 2 c. 8 d. 9 3. How many different numbers can a 6-bit binary word represent? a. 63 b. 64 c. 124 d. 128 4. Which of the following gates are added to the two inputs of an AND gate to convert it to a NOR gate? a. NOT b. AND c. OR d. XOR 5. Which gate connected to a NOT gate produces a NOR gate? a. NOT b. AND c. OR d. XOR 6. The following possible equivalencies have been derived for the Boolean expression X+YZ: I. (X+Y)(X+Z) II. X + Y(X+Z) III. X + (Y +Z ) Which is the correct set of equivalent Boolean expressions? a. I only b. I and II c. I and III d. II and III e. None of I, II or III is equivalent to X +YZ 7. The expression for sum of A, B in the half adder is given by a. AB b. A+B c. A B d. None of the above 8. Which of the following is the binary representation of the hexadecimal number 3B7F? a. 0100 1001 1110 1101 b. 0011 1011 0111 1111 c. 1111 1011 0111 1001 d. 0010 0100 0000 1010 9. What is the equivalent of binary (10110011100011110000) in base 32? 1

a. 11 9 23 31 b. 22 14 7 16 c. 11 9 7 16 d. 11 14 23 16 10. The 2's complement of the binary number 010111 is a. 101001 b. 101000 c. 010111 d. 101011 11. In 2's complement representation, a certain negative number -N is 1011. The representation of +N is a. 0100 b. 0101 c. 0110 d. 1111 12. The 1's complement of the binary number 1101101 is a. 0000010 b. 0010010 c. 0010011 d. 1100011 13. The octal equivalent of 111 010 is a. 81 b. 72 c. 71 d. all of these 14. In an x86 32-bit architecture stack frame, suppose ebp contains 00f8 and esp contains 00f0, then the size of the stack frame is a. 2 bytes b. 4 bytes c. 8 bytes d. 16 bytes 15. In the above example, what is stored in the memory location 00f8? a. The return address of the stack frame s function b. The starting address of the stack frame s function c. The current value of ebp d. The previous value of ebp 16. In the above example, if the function of the stack frame calls another function, a. The return address of the calling function is saved in the memory location 00f0 b. The return address of the calling function is saved in the memory location 00ec c. The return address of the calling function is saved in the memory location 00e8 d. The return address of the calling function is saved in the memory location 00f8 2

Question 2: Minimize the following Boolean functions using the K-map method. (Note: In the truth table specification, for example, 8-11 means minterms 8, 9, 10 and 11; φ represents don t care. a. f1(a, b, c) = Σ ( 0, 3, 4, 6) b. f2(a, b, c, d) = Σ ( 1, 8-11, 13, 15) c. f3(a, B, C, D) = Σ ( 2, 4, 6, 8, 11, 12, 13, 15) +φ (0, 1, 3, 5, 7) d. f4(a, B, C, D) = Σ ( 0, 2, 7, 8, 10, 13, 15) +φ (11, 12, 14) Question 3: Using DeMorgan s theorems, find the complement of the following Boolean function. a. f1 = (a + b )(c + d e )(a + b) (c +de) Question 4: Using the identities in Boolean Algebra, prove the following: a) ABC + ABC + AB C + A BC = AB + AC + BC b) A + A B = A + B Question 5: A combinational circuit has three input lines and two output lines. It takes a 3-bit number and counts the number of 1 s in binary. For example, if the input is 000, the output is 00; if the input is 011, the output is 10, etc. a) Write the truth table b) Minimize the Boolean functions for each output, wherever possible. c) Design the circuit using a two-level AND-OR logic. Question 6: Design a 8-1 multiplexer circuit from the specification and truth table. Redesign the 8-1 multiplexer using 4-1 and/or 2-1 multiplexers as building blocks. Question 7: Draw the state transition diagram for a 3-bit count-down counter with a RESET input. When RESET=0, the counter goes from 111 to 110 to 101, etc. When RESET=1, the counter resets to 111 from any state. Draw the block diagram indicating the number of D flip flops required. Question 8: A computer with 512K memory locations has an instruction format with five fields: an opcode field specifying one of 128 instructions, two register fields specifying one of 40 registers, one memory address field and a constant operand field that can hold 2 HEX digits. What is the total length of the instruction in bits? Show the number of bits in each field in the instruction format. Question 9: Write codes using 3-address, 2-address, 1-address and 0-address instructions for the following arithmetic statement: X = A * (B/C + D) Assume the availability of ADD, SUB, MUL and DIV instructions in addition to LOAD, STORE, PUSH and POP as appropriate. Assume that the memory locations for A, B, etc. are MA, MB, etc. If opcodes are 5 bits long and each memory address is 32 bits, compare the sizes of each code set. Question 10: A computer with 256K memory locations has an instruction format with four fields: an opcode field specifying one of 32 instructions, two register fields specifying one of 24 registers, and one memory address field. What is the total length of the instruction in bits? Show the number of bits in each field in the instruction format. Question 11: The Reference Sheet supplied to you shows the instruction formats of the SRC. Study the formats and write SRC codes to perform each of the following high-level language codes: (a) SUM = 0 SUM = SUM + A + B DIF = DIF - C SUM = SUM + DIF 3

(b) IF (A-B) 10,20,30 (that is, the program branches to statement 10 if A-B <0; to statement 20 if A-B=0; and to statement 30 if A-B >0) Question 12: You are given a reference sheet showing the relevant portion of the data path logic of the SRC architecture. The necessary control signals activating various points in the data path logic are also shown. Study the logic and write the concrete RTN and the control signals necessary to enable each of the following operations. Use a neat tabular format showing the time steps, the operations and the control signals in each step. NOTE: You can skip the Instruction Fetch steps. (a) sub ra,rb,rc (b) ori ra,rb,c2 (c) Load into register rb the content of the memory location whose address is in ra (assume that this instruction is already fetched and is in IR) Question 13: Suppose we add another SRC instruction swap ra, rb that exchanges the contents of registers ra and rb. Develop a concrete RTN and a control sequence for this instruction. Note that you cannot use any other register from the register set for temporary data storage because it will destroy the register contents. NOTE: You can skip the Instruction Fetch steps. Question 14: 1. Convert decimal 0.6875 to binary. 2. Convert decimal 153 to binary. 3. Convert decimal 153 to octal. 4. Convert decimal 117.23 to octal. 5. Convert binary 10110.0101 to decimal. 6. Convert Hex 16.5 to decimal. 7. Convert decimal 431 to binary in two ways: (a) convert directly to binary and (b) convert to Hex and then from Hex to binary. Which method is faster? 8. Perform + 6 + (+13), + 6 + (-13), - 6 + (+13), and 6 + (-13) using 2 complement arithmetic. What is the minimum number of bits you need in the representation to fit all the answers? 9. Decode the following two s complement numbers: 1111 1001, 1111 0001, 1110 1101 Question No. 15: Write the meanings of each of the following x86 instructions: Instruction movl $0, %eax movb $0x05, al movl (%ecx), %edx movl -4(%ebp), %eax movl -4(%ebp, %edx, 4), %eax leal 8(,%eax,4), %eax leal (%edx,%eax,2), %eax Meaning Question 16: The following C code was assembled in x86 Gnu Assembler. The partial output of the assembly is shown. Complete the missing code. Draw the stack showing its contents. 4

int main() { int a = 5; int b = 3; int c = a*2 + b; } _main: pushl %ebp movl %esp, %ebp subl $12, %esp #Add missing code here addl popl retl $12, %esp %ebp Question 17: Write the core part of the assembly code for the C function shown below. Assume that -4(%ebp) has the value of x, -8(%ebp) has the value of y, and -12(%ebp) will hold the value of result. int larger(int x, int y) { int result; if (x > y) result= x; else result= y; return result; } 5

Question 18: Assume eax holds 0x100, ecx holds 0x1 and edx holds 0x3. The four memory locations 0x100 to 0x10C hold 0xFF, 0xAB, 0x11 and 0x13, respectively. Show the result of each of the following x86 operations (note: these operations are separate and not in sequence): (Note: a quick reference guide to x86 assembly instructions will be made available). a) add %ecx, (%eax) b) sub %edx, 4 (%eax) c) imul 16, (%eax, %edx, 4) Question 19: A computer system has 256K words of main memory and 16K words of direct-mapped cache memory. The block size is 256 words. The access time for the main memory is 15 times that of the cache memory. a) What is the size of the tag field? b) If a fully associative mapping scheme were used instead, what would be size of the tag field? c) Determine the efficiency of the system assuming a cache hit ratio of 0.9. d) If the cache access time is 200 nanoseconds, what hit ratio would be required to achieve an average access time equal to 500 nanoseconds? Question 20: A set associative cache has a total of 128 blocks divided into sets of 8 blocks each. Main memory has 2048 blocks with 16 words per block. How many bits are needed for the tag field? Question 21: A computer system has 64K words of main memory and a set associative cache. The block size is 16 words and the tag field of the memory address is 5 bits. If the same cache were direct mapped, the main memory address will have a 3-bit tag field. How many words are there in the cache? How many blocks are there in each cache set? Question 22: A computer system has 64K words of main memory and 4K words of fully associative cache. The block size is 16 words. The access time for the Main Memory is 10 times that of the cache memory. (a) Determine the efficiency of the system assuming a cache hit ratio of 0.8. (b) If the cache access time is 100 nanoseconds, what hit ratio would be required to achieve an average access time of 250 nanoseconds? (c) What is the size of the tag field? (d)if a direct mapping scheme were used instead, what would be the size of the tag field? (e)suppose that it has to be converted into a set associative cache with a tag field size equal to 8 bits, how many sets are there? How many blocks are there in each set? 6

Some Reference Sheets that you will be given during the exam. Additional reference sheet with the SRC data path logic (simplified) may also be given. REFERENCE SHEET NO. 1 n-bit Binary Numbers n = 1 n = 2 n = 3 n = 4 0 1 00 01 10 11 000 001 010 011 100 101 110 111 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Boolean Algebra Identities No. Identity 1 a + 0 = a 2 a. 0 = 0 3 a + 1 = 1 4 a.1 = a 5 a + a = a 6 a.a = a 7 a + a = 1 8 a.a = 0 9 a + b = b + a 10 ab = ba 11 a + (b + c) = (a + b) + c 12 a(bc) = (ab)c 13 a(b+c) = ab + ac 14 a + bc = (a+b)(a+c) 15 a =a 16 a + ab = a 17 a + a b = a+b 18 (a+b) = a.b (ab) = a + b 7

REFERENCE SHEET NO. 2 SRC Instruction Set Symbolic Meaning representation ld ra, c2 Load register ra with M[c2] (content of memory with address c2) ld ra, c2 (rb) Load register ra with M[c2 + R[rb]] st ra, c2 Store content of ra into M[c2] st ra, c2 (rb) Store content of ra into M[c2 + R[rb]] la ra, c2 Load ra with c2 la ra, c2 (rb) Load ra with c2 + R[rb] addi ra, rb, c2 R[rb] + c2 and store result in ra andi ra, rb, c2 R[rb] AND c2 and store result in ra ori ra, rb, c2 R[rb] OR c2 and store result in ra ldr ra, c1 Load ra with M[[PC] + c1] str ra, c1 Store content of ra in M[[PC] + c1] lar ra, c1 Load ra with [PC] + c1 neg ra, rc not ra, rc add ra, rb, rc sub ra, rb, rc and ra, rb, rc or ra, rb, rc Negate the rc and put it in ra Put the complement of rc in ra Add the contents of rb and rc and put it in ra R[rb] R[rc] into register ra R[rb] AND R[rc] into register ra R[rb] OR R[rc] into regiser ra brzr rb, rc 010 Branch to address in rb if content in rc is zero brnz rb, rc 011 Branch to address in rb if content in rc is not zero brpl rb, rc 100 Branch to address in rb if content in rc is positive brmi rb, rc 101 Branch to address in rb if content in rc is negative br rb 001 Branch always brnv rb 000 Branch never Branch and Link Example: brzrl ra, rb, rc Meaning: Save PC value in ra. Then branch to address in rb if content in rc is zero. brnzl,brpll, brmil, brl and brnvl have similar meanings. shr ra, rb, c2 shl ra, rb, c2 shc ra, rb, c2 shra ra, rb, c2 Shift right the content of rb into ra by c2 bits Shift left the content of rb into ra by c2 bits Circular shift left the content of rb into ra by c2 bits Arithmetic shift right the content of rb into ra by c2 bits shr ra, rb, rc Shift right the content of rb into ra by count in rc Similar meanings for shl ra, rb, rc; shc ra, rb, rc; and shra ra, rb, rc nop stop No operation End

REFERENCE SHEET NO. 3 Quick Reference Guide to x86 instructions Instruction Format mov src, dst mov imm, dst push src pop dst add src, dst sub src, dst and src, dst xor src, dst mul src imul src cmp a, b jl label lea src, dst call func ret shr src, dst Purpose Move data between registers, and between registers and memory Move immediate data imm into registers Push the value in src onto the stack Pop the value in the stack onto dst dst = [src] + [dst] dst = [dst]-[src] dst = [src] AND [dst] dst = [src] XOR [dst] Multiply eax and src as unsigned integers, put the product in eax. Same as mul, but sign of the numbers will be maintained. Compare two values. Sets flags used by the conditional jumps given below. NOTE: Compare is relative to the second argument, so jl jumps if b<a. Jump to label if the previous comparison came out true for less than. Other conditions are jle (<=), jge (>=), jeq(==), jge(>=), jg (>), jne (!=) Computes the effective address given by src and stores it in dst Push the address of the next instruction and start executing func Pop the return program counter and jump there. Ends a subroutine. Logical Shift Right dst by src bits Also shl (logical shift left), sar (arithmetic shift right), etc. All registers are prefixed by % All immediate operands are prefixed by $ Operands are suffixed by l for 32 bit instructions: example movl %eax, %ecx moves the content of register eax to register ecx # is the comment marker. Memory address format in an instruction: displacement(base reg, offset reg, scale) where displacement is a constant (positive, negative or zero) Address = content of base reg + displacement + content of offset reg*scale For example, movl -4(%ebp), %eax moves the content of the memory location given the content of ebp register minus 4 to register eax.