Slide Set 1 (corrected)

Slide Set 1 (corrected) for ENCM 369 Winter 2018 Section 01 Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary January 2018

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 2/83 Contents About these slides Organization of a Simple Computer Introduction to the MIPS-32 Computer Architecture Introduction to MIPS registers, machine language and assembly language MIPS Assembly Language Programming: Getting Started

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 3/83 Outline of Slide Set 1 (corrected) About these slides Organization of a Simple Computer Introduction to the MIPS-32 Computer Architecture Introduction to MIPS registers, machine language and assembly language MIPS Assembly Language Programming: Getting Started

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 4/83 About these slides This is the first of around 10 12 large sets of slides that will be used for Section 01 lectures in ENCM 369 in Winter 2018. It will usually take several lectures to get through a single set of slides. For example, I expect that it will take about 5 1 lectures to get through this first set. 2 Reading these slides online is not a good substitute for attending lectures in most lectures I will do some important hand-written work using the document camera. Please come to lectures prepared to take some notes.

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 5/83 Typographical conventions Either bold text or bright red text will be used for emphasis. The typewriter font will usually be used for code in assembly language, C, or C++. (I might not use the typewriter font for code if it makes the code too wide to fit in a slide.) Text in a box is a general description of what could appear within a piece of code. Example: A C do statement has this syntax... do statement while ( expression ); (Usually statement is a compound statement that starts with { and ends with }.)

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 6/83 Typographical conventions: Italics Italics will be used two different ways. One word or a few words in italics will be used to formally or informally define a term. Example: A bit is the basic unit of information in a digital system; the value of a bit is either 0 or 1. An entire sentence in italics indicates a pause to elaborate a concept or solve a problem under the document camera. Example: Let s translate the C statement into a sequence of assembly language instructions.

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 7/83 Outline of Slide Set 1 (corrected) About these slides Organization of a Simple Computer Introduction to the MIPS-32 Computer Architecture Introduction to MIPS registers, machine language and assembly language MIPS Assembly Language Programming: Getting Started

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 8/83 Organization of a Simple Computer Processor Bus Main Memory What is a bus? What is the role of the processor? I/O Device.. I/O Device

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 9/83 Organization of a Simple Computer: I/O Bus Main Memory What does I/O stand for? Processor. I/O Device. I/O Device What are examples of I/O devices in laptop or desktop computers? What are examples of I/O devices in embedded computers?

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 10/83 Main memory Main memory is a collection of electronic circuits that hold instructions and data of running programs. (Hey, what s an instruction?) Main memory in a desktop or laptop is RAM ( random access memory ), not the hard drive. (Typically, the hard drive contains mostly files not currently in use by any running program.) RAM is volatile storage information in RAM is lost when a computer is powered down.

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 11/83 Bytes A bit is the smallest possible item of digital data. A bit has a value of 0 or 1. A byte is a collection of eight bits. Example byte values, written in base two: 01101001 and 10001000. Unfortunately, bit and byte are very similar words be careful not to mix up their meanings! How many different bit patterns are possible for the value of a byte?

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 12/83 Models of Engineering Systems Definition: A model is a simplified description of a system that allows people to understand and predict the behaviour of the system. Often, models are collections of equations (especially differential equations). For computer systems, models are likely to be informal but detailed pictures and stories explaining how systems work.

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 13/83 Models: Deeper Understanding and Better Prediction Sometimes, an existing model can be enhanced made more accurate by adding details, such as extra terms in equations, or more complex stories about components. Other times, an existing model is inaccurate about something important, so the model must be replaced with a new, better model.

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 14/83 Simple model of main memory: A giant array of bytes There may be thousands or millions or billions of bytes in the array. Each byte in the array has a unique address, which is just a number. To advance from one byte to the next byte in memory, add 1 to the address. A variable of type char* (pointer-to-char) in a C or C++ program is a container for the address of a byte.

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 15/83 Registers: Storage of bytes inside the processor A register is a storage location for one or more bytes (typically a group of two, four, or eight bytes) inside the processor. So registers are NOT part of main memory, because main memory is external to the processor. processor registers bus. main memory I/O device. I/O device

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 16/83 Avoid using the word memory when describing a register! This can be confusing. A register is definitely a kind of memory system, in the sense that a pattern of 1 s and 0 s can be written into a register and later read back from that register. However, in discussion of computer organization, memory usually means main memory, which is outside the processor, and does not include the registers inside the processor.

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 17/83 Processors have relatively SMALL numbers of registers Example: In the x86-64 architecture, used by processors in current Macs, and PCs running 64-bit Windows or Linux, there are 16 eight-byte general-purpose registers (GPRs). (So, how many bits are there in an x86-64 GPR?) Another example: In the MIPS32 architecture there are 32 four-byte GPRs. The total capacity of all the registers is TINY compared to the total capacity of main memory!

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 18/83 Replacing a model from ENCM 339 Model used a lot in ENCM 339: All variables and function arguments in a running C (or C++) programs are in main memory, in regions called the stack, static storage, and the free store (or heap). This model is very helpful in understanding C and C++ code, but in ENCM 369 you must stop believing it! Why won t this model work in ENCM 369?

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 19/83 Key terms: Memory Read and Memory Write Memory read operation: The processor puts a memory address on the bus. A group of bytes (usually one, two, four or eight) in memory gets copied from memory to a register, via the bus. Memory write operation: The processor puts a memory address on the bus. A group of bytes (usually one, two, four or eight) in memory gets copied from a register to memory, via the bus.

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 20/83 Memory Reads and Memory Writes, continued The answers to these questions are simple but also very important to be clear about! What component is choosing the address in a read operation? What component is choosing the address in a write operation? Why is only one address needed when there is a read or write of two or more bytes?

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 21/83 The Simplest Useful Model for How a Computer Works There are two steps. Let s write descriptions for these steps. The processor performs Step 1, Step 2, Step 1, Step 2, Step 1, Step 2,... forever (or until the computer is turned off).

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 22/83 The Simplest Useful Model for How a Computer Works: Key Questions In Step 1, how does the processor decide what address to use to get an instruction? In Step 2, what kinds of action can be performed by the processor in executing an instruction?

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 23/83 Flow of instructions (What memory address is used in Step 1?) The picture shows 9 bytes within the giant array of bytes that is main memory. Suppose that the processor is about to read Instruction A. What happens next? lower addresses higher addresses. 01011110 11001001 10101100 00001110 10010000 00010001 00000000 00000000 00000100. Instruction A (3 bytes) Instruction B (2 bytes) Instruction C (4 bytes)

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 24/83 Flow of instructions: if statements, loops, and function calls It would be impossible to create useful programs if processors always read and executed instructions in the order in which the instructions appeared in main memory. What kinds of special instructions allow program pieces like if statements, loops, and function calls to work?

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 25/83 Registers (Review) A register is a storage location for one or more bytes (typically a group of two, four, or eight bytes) inside the processor. So registers are NOT part of main memory, because main memory is external to the processor. processor registers bus. main memory I/O device. I/O device

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 26/83 Uses for GPRs and memory Reminder: GPR stands for general-purpose register. A GPR can hold either an integer or a memory address (a C pointer). GPRs hold a small amount of a running program s data. (Here data means variables and function arguments.) Memory holds the rest of the program s data usually much more than what is in the GPRs and all of the program s instructions.

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 27/83 For a typical processor design, a complete description of all integer types you can use GPRs for can be messy and complicated! (For example, on x86-64, uses of GPRs for 8-bit, 16-bit, 32-bit and 64-bit signed and unsigned integers are all supported to varying degrees, and the C names for the types may differ from one OS to another.) To get started in this course, we ll simplify things we ll think only about 32-bit C int (signed two s-complement) and 32-bit C unsigned int types.

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 28/83 Examples of tasks performed in executing an instruction (or What happens in Step 2? ) Suppose we have the C statement foo = x + y + z; where all the variables are ints. What sequence of instructions could be used to make this statement work?

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 29/83 Outline of Slide Set 1 (corrected) About these slides Organization of a Simple Computer Introduction to the MIPS-32 Computer Architecture Introduction to MIPS registers, machine language and assembly language MIPS Assembly Language Programming: Getting Started

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 30/83 MIPS processors Designed by a company called MIPS, which in 2013 was acquired by another company called Imagination Technologies (http://imgtec.com). Manufactured under license by many different companies. Today, used mostly in embedded systems, such as digital cameras, network hardware, automotive applications, GPS receivers,... In 1980 s and 1990 s, used for desktop workstations produced by Digital Equipment Corporation and Silicon Graphics, Inc. It was also used for some famous game console designs such as the Sony Playstation 2 and the Nintendo 64.

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 31/83 Why study the MIPS architecture in ENCM 369? The MIPS architecture is easier to learn and understand than the x86 and x86-64 architectures (used in PCs and Macs) or ARM architectures (used in smartphones, tablets, and lots of other products). It has many properties in common with x86, x86-64, ARM, and other major architectures, so almost all of the knowlege gained learning MIPS will help you understand other architectures as well. Our textbook is MIPS-based!

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 32/83 Variations of MIPS In this course, we ll study the MIPS-32 version. We ll just say MIPS in this course, but we really mean MIPS-32. In MIPS-32... GPRs are 32 bits wide. Memory addresses are 32 bits wide. Instructions are 32 bits wide. Memory words are 32 bits wide. There are related MIPS-16 and MIPS-64 architectures, but we won t study those in detail.

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 33/83 Memory is really organized in words, not bytes A simple model presented about 19 slides back says: main memory is a giant array of bytes. A more complex and accurate model that we ll start using now says: Bytes in main memory are grouped together in multi-byte pieces called words, and memory should be thought of as a giant array of words. Much later in the course, we will study more complex models of main memory, involving concepts of caches and virtual memory.

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 34/83 Different architectures have different word sizes Word size Word size Example (bytes) (bits) systems 2 16 PCs and Macs of 1980 s low-power embedded systems 4 32 MIPS-32 PCs, Macs, until several years ago many embedded systems 8 64 servers current game consoles current PCs and Macs current high end smartphones

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 35/83 MIPS-32 memory organization: An array of 32-bit words Each word is four bytes the address of a word is the lowest of the addresses of its bytes. What are the addresses of word X, byte Y, and byte Z? word address 2 32 4 2 32 8 2 32 12. 8 4 0 byte offset +3 +2 +1 00 11 00 11. +0 00000000 11111111 00000000 11111111 byte Z byte Y word X

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 36/83 Address spaces and regions within address spaces The address space of a computer system is the set of all possible memory addresses. The previous slide showed the MIPS-32 address space. Why is 2 32 4 the largest word address in the MIPS-32 address space? A typical program ignores most of the address space. The program uses only a few regions within the address space typically one region for instructions, and a small number of regions for data.

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 37/83 A model for MIPS memory access MIPS processor registers logical address 32 address translation Bus control signals? physical address 32 data or instruction 32 Main Memory (big array of words)

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 38/83 A model for MIPS memory access (continued) What are some examples of control signals, and how might they be used? What does address translation mean? Example 1: How is the bus used to bring an instruction into the processor? Example 2: How is the bus used when the processor updates a byte in a character string in memory?

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 39/83 Alignment restrictions in MIPS: word addresses must be multiples of 4 byte offset word address +3 +2 +1 +0.. 00 11 00 11 000000 111111 00000000 11111111 00000000 11111111 4,194,320 4 consecutive 4,194,316 bytes, but NOT 4,194,312 a word 4,194,308 4,194,304 a word..

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 40/83 More about alignment Addresses of 16-bit MIPS halfwords must be multiples of 2. Most processor families have alignment rules, such as: 16-bit chunks must have addresses that are multiples of 2. 32-bit chunks must have addresses that are multiples of 4. 64-bit chunks (such as C doubles) must have addresses that are multiples of 8. Alignment rules simplify the design of memory hardware, helping memory handle reads and writes as fast as possible.

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 41/83 Outline of Slide Set 1 (corrected) About these slides Organization of a Simple Computer Introduction to the MIPS-32 Computer Architecture Introduction to MIPS registers, machine language and assembly language MIPS Assembly Language Programming: Getting Started

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 42/83 Introduction to MIPS registers, machine language and assembly language Let s start with the GPRs (general-purpose registers). (Remember, registers are inside the processor, not part of main memory!) MIPS has 32 general-purpose registers (GPRs). Each GPR is 32 bits wide, and can hold either a C int or a memory address (C pointer). The GPRs are numbered from 0 to 31. They also have names we ll learn the names soon.

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 43/83 MIPS registers that are NOT GPRs There are 16 floating-point point registers (FPRs), each 64 bits wide. Each can hold a C double. (We ll learn more about floating-point numbers and FPRs near the end of the course.) There are also several special-purpose registers, including a very important one called the PC (program counter).

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 44/83 MIPS instruction size Each instruction is exactly one word in size. (How many bits is that? How many bytes?) (In ARM instruction sets, instructions are, as in MIPS, all 4 bytes in size. In contrast, instructions in the x86 instruction set vary in size from one byte to 17 bytes.) A fixed instruction size simplifies hardware design, but allowing varying sizes sometimes results in smaller program size.

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 45/83 The Program Counter (PC) In this course you will have to determine from context whether PC means personal computer or program counter! The MIPS PC is a 32-bit special-purpose register that holds the address of the next instruction to be read from memory. Instruction pointer would be a better name than program counter! But program counter is the standard name in MIPS and many other architectures.

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 46/83 The PC and the Simplest Useful Model for How a Computer Works Step 1: Processor reads instruction from memory. Step 2: Processor executes the instruction. (The instruction is a very simple command.) The processor performs Step 1, Step 2, Step 1, Step 2, Step 1, Step 2,... forever (or until the computer is turned off). What are Steps 1 and 2 in terms of the PC and the MIPS memory model?

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 47/83 Review of hexadecimal numbers, notation for hexadecimal numbers As you learned in ENEL 353, hexadecimal means base sixteen. Using the notation of ENEL 353, here s an example: 50CD 16 = 5 16 3 + 0 16 2 + 12 16 1 + 13 16 0 = 5 4096 + 0 256 + 12 16 + 13 = 20685 10 In ENCM 369 we ll use 0x (digit 0, not letter O) to indicate hexadecimal constants, because that notation is used in C, C++, many assembly languages, and many other programming languages. Example: In C, this expression is true... 0x50cd == 20685

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 48/83 Notation in ENCM 369 for numbers with lots of digits Underscores separate groups of digits. Groups of digits are whatever size is convenient. Examples... one billion: 1 000 000 000 2 31 1, in hexadecimal: 0x7fff_ffff Using underscores to separate groups of digits is allowed in recent versions of Java and Python. That is quite a cool feature. Unfortunately underscores in numbers won t work in C or MIPS assembly language, which are the main languages we will use in ENCM 369 this term.

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 49/83 A typical MIPS instruction Let s call this example (1): Add values of GPR 8 and GPR 9, copy result into GPR 17. The bit pattern for this example instruction... 000000_01000_01001_10001_00000_100000 What do the groups of bits within the instruction mean?

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 50/83 More example instructions Example (2): Add constant 1025 and value of GPR 18, copy result into GPR 10. Example (3): Copy word of memory pointed to by GPR 4 into GPR 8. (This is called a load word instruction.) Example (4): Copy byte of memory pointed to by GPR 4 into GPR 8. (This is called a load byte instruction.)

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 51/83 Processor-memory interaction for 3 kinds of MIPS instructions MIPS processor logical address 32 registers address translation main memory control signals? data/instruction 32 32 physical address Let s use 6 copies of this diagram to trace Steps 1 and 2 for three instructions...

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 52/83 Processor-memory interaction for 3 kinds of MIPS instructions, continued The instructions will be example (1), an add instruction; example (3), an lw instruction; an sw (store word) instruction, which copies a word from a GPR to memory, using another GPR value as an address. Very important! Know this as soon as possible: lw (load word) copies data from memory to a GPR. sw (store word) copies data from a GPR to memory.

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 53/83 Programming in Machine Language A program is a sequence of instructions, and each instruction is a bit pattern. With a manual describing the bit patterns for all of the instructions available on a computer, you could write a program by composing bit patterns, one instruction at a time. This method of building a program is called programming in machine language. The earliest computers had to be programmed in machine language there was no software available for any other method of programming!

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 54/83 Assembly Language Composing machine language is tedious and slow. It s easier for humans to write instructions with a text editor and let a translator program determine the bit patterns. This kind of translator program is called an assembler the input to the assembler is called assembly language.

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 55/83 Things you will see in an A. L. (assembly language) file Descriptions of instructions, one instruction per line. Directives for allocation and initialization of static data. Other important kinds of information.

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 56/83 Syntax for instructions in A. L., examples of MIPS A. L. instructions What is the general form of an A. L. instruction? What would the MIPS A. L. be for the machine language examples we saw previously? (1) add GPRs 8 and 9, put result in GPR 17 (2) add GPR 18 and constant 1025, put result in GPR 10 (3) copy memory word pointed to by GPR 4 into GPR 8 (4) copy memory byte pointed to by GPR 4 into GPR 8

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 57/83 Historic uses of Assembly Language For decades, entire programs were written in A.L. Examples: Operating systems for industry-dominating IBM mainframes (1960 s). Microsoft MS-DOS and many important applications for MS-DOS. Many, many pieces of embedded system software.

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 58/83 Why write an entire program in A.L.? It used to be true that skilled humans could write A. L. programs that were smaller and faster than equivalent high-level language (HLL) programs that did the same work. This reason is now obsolete good modern compilers can almost always generate smaller, more efficient instruction sequences than most humans even highly educated and skilled humans can write in A.L.

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 59/83 Modern reasons to know A.L. 1. Certain small pieces of programs are better written in A.L. than in a HLL. 2. Old A.L. programs may need to be debugged or enhanced. 3. Students programming in A.L. develop precise models for what a processor does and what a compiler does. Reason 3 is why you will read and write a lot of A.L. in ENCM 369.

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 60/83 Reasons to avoid programming in A.L. Cost: Compared to C and other HLLs, A.L. takes more time to write and is much harder to read and debug. Lack of portability: Good C code is portable: It can be compiled to run on many different processor families. A.L. code is processor-specific for example, a program written in MIPS A.L. can not be made to run efficiently on an x86-64 computer.

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 61/83 Outline of Slide Set 1 (corrected) About these slides Organization of a Simple Computer Introduction to the MIPS-32 Computer Architecture Introduction to MIPS registers, machine language and assembly language MIPS Assembly Language Programming: Getting Started

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 62/83 MIPS Assembly Language Programming: Getting Started Let s start with some names and uses for MIPS GPRs. $0 is also known as $zero. It has unique, possibly surprising behaviour: It always contains the number 0, regardless of what is done with it. Suppose $16 and $17 contain values 20 and 30. What happens as a result of these instructions? add $18, $16, $17 add $0, $16, $17

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 63/83 Names and uses for some MIPS GPRs, continued $16 $23 are known as $s0 $s7 and are often (but not always) used for local variables of procedures. (Procedure is a general name for things like C functions.) (Remember, contrary to the model presented in ENCM 339, some variables and function arguments are in GPRs, not main memory.) $8 $15, $24, and $25 are known as $t0 $t9 and are often (but not always) used as temporaries storage for intermediate results. More complete rules for use of $s0 $s7 and $t0 $t9 will be presented later in the course.

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 64/83 Example uses of s-registers and t-registers variable register a $s0 b $s1 c $s2 d $s3 e $s4 f $s5 Suppose GPRS are allocated for six int variables as shown in the table. What are A.L. translations for the statements below? // statement one a = 0; // statement two b = (c - d) + (e - f);

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 65/83 MIPS A.L. syntax for lw (load word) and sw (store word) Review: load means copy data from memory to a register, store means copy data from a register to memory. Syntaxes for the instructions are... lw destination, address sw source, address destination in lw must be a GPR. source in sw must be a GPR. Let s make some notes about the syntax for address.

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 66/83 Array elements, registers, and memory Memory words all have addresses. Registers DO NOT HAVE ADDRESSES! (Registers can contain addresses, but that s not the same thing!) How does array element access work? What does that imply about whether arrays can be in registers or in memory?

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 67/83 Example A.L. code for array element access Suppose $s0 is used for p, of type int* (pointer-to-int). Suppose $s1 is used for k, of type int. What would be a correct A.L. translation for the C code below? p[10] = p[20] + k; (This requires that p points to the start of an array of at least 21 int elements. You re expected to know, from ENCM 339, about using pointers to access array elements!)

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 68/83 Decision-making and branch instructions To write A.L. that works like a C if statement, we need an instruction that causes a skip forward if some condition is true. Example C code, where x, y, z are all ints: if (x == y) z = 0; z = z + x; Suppose x is in $s0, y is in $s1, and z is in $s2. What would be a correct MIPS A.L. translation?

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 69/83 Labels in A.L. L1 in the previous A.L. code is an example of a label. A label is used to give a name to an instruction or an item of static data. (See Lab 2 for examples of labels for static data.) A label names the next instruction or data item listed in the A.L. code, regardless of comments or blank lines...

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 70/83 In each example below, L1 is a label for the add instruction Example 1 Example 2 Example 3 L1: add $s2, $s2, $s0 L1: L1: # Here are add $s2, $s2, $s0 # some comments # and blank lines. add $s2, $s2, $s0 The style of Example 1 uses the least vertical space. The style of Example 2 may be more readable because the label is easier to spot. The style of Example 3 is silly but allowed by the assembler.

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 71/83 Branch and jump instructions You were made to write lots of goto statements in C in Lab 1 because that should help you quickly understand branches and jumps! Branch (general concept): goto an instruction, but only if some condition is true. Jump (general concept): goto an instruction, without checking any condition.

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 72/83 beq, bne, and j: three of the many branch and jump instructions available in MIPS beq GPR 1, GPR 2, label meaning: if ( GPR 1 == GPR 2 ) goto label bne GPR 1, GPR 2, label meaning: if ( GPR 1!= GPR 2 ) goto label j label meaning: goto label

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 73/83 A few terms: jump target, taken, branch target The target of a jump instruction is defined as the instruction to be executed after the jump instruction. (So the A.L. label in a MIPS j instruction is the label of the jump target.) A branch instruction is said to be taken if the condition tested by the branch is true. The target of a branch is the instruction that will be executed next if the branch is taken.

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 74/83 How do jumps and branches fit into The Simplest Useful Model? The model, for MIPS... Step 1: Using PC contents as an address, read instruction word from memory, add 4 to PC. Step 2: Execute the instruction. Repeat Step 1, Step 2, Step 1, Step 2, and so on, forever. Using the terms target and taken, what are more precise descriptions of Step 2 for MIPS j, beq, and bne instructions?

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 75/83 One way to code a C while loop in A.L.: branch at the top, jump at the bottom Let s translate this example into MIPS A.L. sum = 0; i = 0; while (i!= n) { sum += a[i]; i++; } //... more code... variable type GPR a int * $s0 n int $s1 sum int $s2 i int $s3

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 76/83 Branches and comparisons: the MIPS slt instruction What if we want to branch to some label, say, L42, if $s0 < $s1? Neither bne nor beq will work! A two-instruction sequence is needed: slt $t0, $s0, $s1 # $t0 = ($s0 < $s1) bne $t0, $zero, L42 # if ($t0) goto L42 slt means set on less than. In the example, if $s0 < $s1, $t0 gets a value of 1, otherwise $t0 gets 0. slt is a kind of comparison instruction.

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 77/83 Using the sll (shift left logical) instruction to multiply by a power of 2 From the while loop example: sll $t0, $s3, 2 # $t0 = 4 * $s3 Why does this work? To start, let s find out what sll does. The syntax is sll dest. GPR, source GPR, constant The instruction takes the bit pattern from the source, shifts it left by constant bit positions, and puts the result in the destination.

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 78/83 Why does left shift do multiplication? In base ten, think about computing 9753 987, then computing 9753 1000. How is this related to multiplication in base two? Let s write some MIPS examples of multiplication using the sll instruction. Later in the course we ll find that MIPS has multiply instructions. However, sll is more convenient for the special case of multiplying by a power of two.

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 79/83 Pseudoinstructions in MIPS A.L. These are convenient for A.L. programmers, but a little confusing for beginners. A pseudoinstruction is a line of A.L. that looks like a MIPS instruction but does not correspond exactly to a MIPS machine instruction. The assembler handles a pseudoinstruction by generating one or more real instructions that have the appropriate effect.

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 80/83 Example pseudoinstruction... blt $s0, $s1, L1 MIPS does not have a single instruction that can do both a less than comparison and a branch decision. What does the assembler do with this blt pseudoinstruction? In ENCM 369 we want to learn real instructions, so we ll avoid pseudoinstructions whenever possible. However, certain pseudoinstructions for example, la, used in Lab 2 are impossible to avoid.

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 81/83 Another example pseudoinstruction: move $t1, $t0 # copy $t0 value into $t1 The assembler will read that and generate a real machine instruction, something like this: add $t1, $zero, $t0

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 82/83 Pseudoinstructions that have real-instruction mnemonics This is one of the more confusing aspects of the MIPS assembly language. Here are a few examples... A.L. code add $t0,$t0,1 addi $s1,$s0,0x12345 lw $t9, label Remarks A true add has 3 GPR operands. Assembler generates an addi instruction. Constant too big to fit in 16 bits. Assembler generates a 3-instruction sequence. Assembler generates a 2-instruction sequence; 2nd instruction is lw with address built from GPR and offset.

ENCM 369 Winter 2018 Section 01 Slide Set 1 (corrected) slide 83/83 Avoid using pseudoinstructions in ENCM 369 labs Every now and then using a pseudoinstruction can save you a small amount of typing, but doing so slows down learning of the real MIPS instruction set. Exception: Use la GPR, label whenever you like. There is no convenient way to get the same effect with real instructions. Pseudoinstructions are briefly described in Section 6.7.2 of the textbook. The Help facility built into MARS provides separate lists of all the real instructions and pseudoinstructions supported by MARS.