Programmable Logic Devices Programmable Logic Devices (PLDs) are the integrated circuits. They contain an array of AND gates & another array of OR gates. There are three kinds of PLDs based on the type of array(s), which has programmable feature. Programmable Read Only Memory Programmable Array Logic Programmable Logic Array The process of entering the information into these devices is known as programming. Basically, users can program these devices or ICs electrically in order to implement the Boolean functions based on the requirement. Here, the term programming refers to hardware programming but not software programming. Programmable Read Only Memory (PROM) Read Only Memory (ROM) is a memory device, which stores the binary information permanently. That means, we can t change that stored information by any means later. If the ROM has programmable feature, then it is called as Programmable ROM (PROM). The user has the flexibility to program the binary information electrically once by using PROM programmer. PROM is a programmable logic device that has fixed AND array & Programmable OR array. The block diagram of PROM is shown in the following figure. Here, the inputs of AND gates are not of programmable type. So, we have to generate 2 n product terms by using 2 n AND gates having n inputs each. We can implement these product terms by using nx2 n decoder. So, this decoder generates n min terms. Here, the inputs of OR gates are programmable. That means, we can program any number of required product terms, since all the outputs of AND gates are applied as inputs to each OR gate. Therefore, the outputs of PROM will be in the form of sum of min terms. Example Let us implement the following Boolean functions using PROM.
A(X,Y,Z)= m(5,6,7)a(x,y,z)= m(5,6,7) B(X,Y,Z)= m(3,5,6,7)b(x,y,z)= m(3,5,6,7) The given two functions are in sum of min terms form and each function is having three variables X, Y & Z. So, we require a 3 to 8 decoder and two programmable OR gates for producing these two functions. The corresponding PROM is shown in the following figure. Figure 1 Here, 3 to 8 decoder generates eight min terms. The two programmable OR gates have the access of all these min terms. But, only the required min terms are programmed in order to produce the respective Boolean functions by each OR gate. The symbol X is used for programmable connections. Programmable Array Logic (PAL)
PAL is a programmable logic device that has Programmable AND array & fixed OR array. The advantage of PAL is that we can generate only the required product terms of Boolean function instead of generating all the min terms by using programmable AND gates. The block diagram of PAL is shown in the following figure. Figure 2 Here, the inputs of AND gates are programmable. That means each AND gate has both normal and complemented inputs of variables. So, based on the requirement, we can program any of those inputs. So, we can generate only the required product terms by using these AND gates. Here, the inputs of OR gates are not of programmable type. So, the number of inputs to each OR gate will be of fixed type. Hence, apply those required product terms to each OR gate as inputs. Therefore, the outputs of PAL will be in the form of sum of products form. Example Let us implement the following Boolean functions using PAL. A=XY+XZ A=XY+XZ A=XY +YZ A=XY +YZ The given two functions are in sum of products form. There are two product terms present in each Boolean function. So, we require four programmable AND gates & two fixed OR gates for producing those two functions. The corresponding PAL is shown in the following figure.
Figure 3 The programmable AND gates have the access of both normal and complemented inputs of variables. In the above figure, the inputs X, X X, Y, Y Y, Z & Z Z, are available at the inputs of each AND gate. So, program only the required literals in order to generate one product term by each AND gate. The symbol X is used for programmable connections. Here, the inputs of OR gates are of fixed type. So, the necessary product terms are connected to inputs of each OR gate. So that the OR gates produce the respective Boolean functions. The symbol. is used for fixed connections. Programmable Logic Array (PLA) PLA is a programmable logic device that has both Programmable AND array & Programmable OR array. Hence, it is the most flexible PLD. The block diagram of PLA is shown in the following figure.
Figure 4 Here, the inputs of AND gates are programmable. That means each AND gate has both normal and complemented inputs of variables. So, based on the requirement, we can program any of those inputs. So, we can generate only the required product terms by using these AND gates. Here, the inputs of OR gates are also programmable. So, we can program any number of required product terms, since all the outputs of AND gates are applied as inputs to each OR gate. Therefore, the outputs of PAL will be in the form of sum of products form. Example Let us implement the following Boolean functions using PLA. A=XY+XZ A=XY+XZ B=XY +YZ+XZ B=XY +YZ+XZ The given two functions are in sum of products form. The number of product terms present in the given Boolean functions A & B are two and three respectively. One product term, Z XZ X is common in each function. So, we require four programmable AND gates & two programmable OR gates for producing those two functions. The corresponding PLA is shown in the following figure.
Figure 5 The programmable AND gates have the access of both normal and complemented inputs of variables. In the above figure, the inputs X, X X, Y, Y Y, Z & Z Z, are available at the inputs of each AND gate. So, program only the required literals in order to generate one product term by each AND gate. All these product terms are available at the inputs of each programmable OR gate. But, only program the required product terms in order to produce the respective Boolean functions by each OR gate. The symbol X is used for programmable connections. ADVANTAGE OF PAL AND PLA:- Fewer printed circuit board
software d sequential circuits can be done with the help of PAL. functions a PAL can have larger inputs and implement a number of be complemented adding pos functions do not require long lead times for prototypes or production parts - the PALs a real ready on a distributor's shelf and ready for shipment. No multilevel circuit implementations in ROM without external connections from output to input PAL has outputs from OR terms as internal inputs to all AND terms making implementation of multi-level circuits easier.
Implement following combinational logic circuits, using PLA F1 ( A, B, C) = (0, 1, 3, 4) and F2 ( A, B, C) = (1, 2, 3, 4, 5). Figure 6(a) Map for function F1. - Figure 6(b) Map for function F2. Assume that a 3 4 2 PLA is available for the realization of the above functions. It should be noted that according to the number of inputs and output, the specified PLA is sufficient to realize the functions. However, total distinct minterms in the functions are six, whereas available product terms or the number of AND gates in the specified PLA is four. So some simplification or minimization is required for the functions. Karnaugh maps are drawn in Figures (a) and (b) for this purpose. The simplified Boolean expressions for the functions are F1 = B'C' + A'C and F2 = A'B + A'C + AB'. In these expressions, there are four distinct product terms-b'c', A'C, A'B, and AB'. So these function can be realized by the specified 3 4 2 PLA. The internal connection diagram for the functions using PLA after fuse-links programming is demonstrated in Figure Figure 7 Programming the PLA means to specify the paths in its AND-OR-INVERT pattern. A PLA program table is a useful tool to specify the input-output relationship indicating the number of product terms and their expressions. It also specifies whether the output is complemented or not. The program table for the above example is shown in Figure 6.18.
Product Terms Inputs Outputs A B C F1 F2 A'B 1 0 1 - - 1 A'C 2 0-1 1 1 AB' 3 1 0 - - 1 B'C' 4-0 0 1 - Figure 8 T T T/C The first column lists the product terms numerically. The second column specifies the required paths between inputs and AND gates. The third column indicates the paths between the AND gates and OR gates. Under each output variable, T is written if output INVERTER is bypassed i.e., the output at true form, and C is written if output is complemented with INVERTER. The Boolean terms listed at the leftmost are for reference only, they are not part of the table. For each product term, the inputs are marked with 1, 0, or - (dash). If the input variable is present in the product term at its complemented form, the corresponding input variable is marked with a 1. If the input variable appears in the product term at its complemented form, it is marked with a 0. If the variable does not at all appear in the product term, it is marked with a - (dash). Thus the paths between the inputs and the AND gates are specified under the column heading inputs and accordingly the links at the inputs of AND gates are to be retained or blown off. The AND gates produce the required product term. The open terminals of AND gates behave like logic 1. The paths between the AND gates and OR gates are specified under the column heading outputs. Similar to the above, the output variables are also marked with 1, 0, or - (dash) depending upon the presence of product terms in the output expressions. Finally, a T (true) output dictates that links across the INVERTER are retained and for C (complemented) at output indicates that the link across the INVERTER is to be broken. The open terminals of OR gates are assumed to be logic 0. While designing a digital system with PLA, there is no need to show the internal connections of the unit. The PLA program table is sufficient to specify the appropriate paths. For a custom made PLA chip this program table is needed to provide to the manufacturer. Since for a given PLA, the number of AND gates is limited, careful investigation must be carried out, while implementing a combinational circuit with PLA, in order to reduce the total number of distinct product terms. This can be done by simplifying each function to a minimum number of terms. Note that the number of literals in a term is not important as all the inputs are available. It is required to obtain the simplified expressions both of true form and its complement form for each of the functions to observe which one can be expressed with fewer product terms and which one provides product terms that are common to other functions. The following example will clarify this.
Implement the following Boolean functions using a 3 4 2 PLA. F1 ( A, B, C) = (3, 5, 6, 7) and F2 ( A, B, C) = (0, 2, 4, 7). Solution. A total of seven minterms are present in the two functions above, whereas the number of AND gates is four in the specified PLA. So simplification of the above functions is necessary. Simplification is carried out for both the true form as well as the complement form for each of the functions. Karnaugh maps are drawn in Figure 6.19(a)-(d). Figure 9(a) Map for function F1. - Figure 9(b) Map for function F2. Figure 9(c) Map for function F1'. - Figure 9(d) Map for function F2'. The Boolean expressions are F1 = AC + AB + BC and F2 = B'C' + A'C' + ABC F1' = B'C' + A'B' + A'C' and F2' = A'C + B'C + ABC'. From the Boolean expressions it can be observed that if both the true forms of F1 and F2 are selected for implementation, the total number of distinct product terms needed to be realized is six, which is not possible by the specified 3 4 2 PLA. However, if F1' and F2 are selected, then the total number of distinct product terms reduces to four, which is now possible to be implemented by the specified PLA. F1 can be complemented by the output INVERTER to obtain its true form of F1. The PLA program table for these expressions is prepared in Figure 6.20. Note that the C (complement) is marked under the output F1 indicating that output INVERTER exists at the output path of F1. The logic diagram for the above combinational circuit is shown in Figure 6.21. Product Terms Inputs Outputs A B C F1 F2 B'C' 1-0 0 1 1 A'B' 2 0 0-1 -
A'C' 3 0-0 1 1 ABC 4 1 1 1-1 Figure 10 C T T/C Figure 11 It should be noted that the combinational circuits for the examples presented here are too small and simple for practical implementation with PLA. But they do serve the purpose of demonstration and show the concept of PLA combinational logic design. A typical commercial PLA would have over 10 inputs and about 50 product terms. The simplification of so many variables are carried out by means of tabular method or other computer-based simplification methods. Thus, the computer program assists in designing the complex digital systems. The computer program simplifies each of the functions of the combinational circuit and its complements to a minimum number of terms. Then it optimizes and selects a minimum number of distinct product terms that cover all the functions in their true form or complement form.