DSI Receiver Protocol Conformance Test Report UNH-IOL 121 Technology Drive, Suite 2 Durham, NH 03824 +1-603-862-0090 mipilab@iol.unh.edu +1-603-862-0701 Engineer Name engineer@company.com Panel Company 1010 Glass Way San Jose, CA USA 09/27/10 Enclosed are the results from the MIPI DSI Receiver Protocol Conformance testing performed on: Panel Company 3 Lane MIPI DSI Receiver This testing was performed by UNH-IOL from September 20, 2010 September 25, 2010. The test suite referenced in this report is available on the MIPI Alliance website: http://www.iol.unh.edu/services/testing/mipi/testsuites.php Issues Observed While Testing The DSI Receiver under test was observed to meet all requirements tests for DSI Receivers. For specific details regarding issues please see the corresponding test result. Test Report Completed 9/27/2010 iol Digitally signed by UNH-IOL Date: 2010.09.14 16:24:38 04'00' Kevin Maffei kmaffei@iol.unh.edu
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Section 1: DUT and Test Setup Information Test Setup Details Manufacturer Model Firmware Revision Hardware Revision UNH-IOL ID: DSI/DCS Traffic Generator DSI/DCS Montior Additional Comments/Notes Panel Company 3 Lane MIPI DSI Receiver Not Available Not Available 99989 Moving Pixel Company P331 Agilent GHz Infiniium DSO with UNH-IOL DPHYGUI Software The below diagram shows the test setup used in performing this testing. The following table contains possible results and their meanings: with Comments FAIL Warning Informative Refer to Comments Not Applicable Borderline Not Tested Interpretation The Device Under Test (DUT) was observed to exhibit conformant behavior. The DUT was observed to exhibit conformant behavior however an additional explanation of the situation is included, such as due to time limitations only a portion of the testing was performed. The DUT was observed to exhibit non-conformant behavior. The DUT was observed to exhibit behavior that is not recommended. s are for informative purposes only and are not judged on a pass or fail basis. From the observations, a valid pass or fail could not be determined. An additional explanation of the situation is included. The DUT does not support the technology required to perform these tests. The observed values of the specified parameters are valid at one extreme, and invalid at the other. Not tested due to the time constraints of the test period. 3
Section 2: Protocol Conformance Test s Chapter 5: DSI Physical Layer, Group 1: Data Flow Control Test 5.1.1 Packets Sent in Entirety To determine that the DSI device transmits Packets in their entirety. Test 5.1.2 Packets Received in Entirety To determine that the DSI device receives Packets in their entirety. The peripheral properly transmitted all packets in entirety. Refer to figure 1. The peripheral received packets in entirety because the image was displayed properly on the LCD panel. Refer to Figure 5. Chapter 5: DSI Physical Layer, Group 2: Bidirectionality and Low Power Signaling Policy Test 5.2.1 Proper Lane Use in Command Mode To determine that the DSI device properly implements bidirectionality on Lane 0 and unidirectionality on Lane 1,2,3 if operating in Command Mode. Test 5.2.2 Proper Lane Use in Video Mode To determine that the DSI device properly implements bidirectionality or unidirectionality on Lane 0 and unidirectionality on Lane 1,2,3 if operating in Video Mode. Test 5.2.3 Clock Lane Only Driven by Host To determine that the DSI host always drives the Clock lane and that a peripheral device never drives the Clock Lane. Test 5.2.4 Low Power Transmission To determine that the DSI host sends LP transmissions on data lane 0 only and that the DSI Peripheral sends transmissions on data lane 0 only use LP. Test 5.2.5 Bidirectional Transmission To determine that the DSI host sends LP transmissions on data lane 0 only and that the DSI Peripheral sends transmissions on data lane 0 only use LP. Test 5.2.6 Peripheral Receives Bus Turnaround Request To determine that Hosts and Peripherals properly accept and issue Bus Turn-Around commands. Not Applicable The peripheral properly receivied HS data on all data lanes (4). This was verified by an image being displayed properly on the LCD panel. See Figure 2 to see the bi-directionality on lane 0 after sending HS packet. The clock lane is never driven by the peripheral. The peripheral responds to both HS and LP transmissions. The response only occurs on data lane 0. Refer to Figure 3. The peripheral responds to both HS and LP transmissions. The response only occurs on data lane 0. Refer to Figure 3. The peripheral properly issues and receives bus turnaround commands whether the data is sent in HS or LP. Refer to figure 3. Chapter 5: DSI Physical Layer, Group 3: Command Mode Interfaces 4
Test 5.3.1 Peripheral Command Mode Data Lane Module Requirements To determine that a Peripheral Data Lane Module operating in Command Mode supports CIL-SFAA (HS-RX, LP-RX, LP-TX, LP-CD). Test 5.3.2 Peripheral Command Mode Clock Lane Module Requirements To determine that a Peripheral Clock Lane Module operating in Command Mode supports CIL-SCNN (HS-RX, LP-RX). Test 5.3.3 Command Mode Bidirectional Link Reverse Direction Escape Mode Support To determine that a peripheral supporting bidirectionality on Lane 0 while operating in Command Mode supports Escape mode. Test 5.3.4 Command Mode Bi-directional Link Forward Direction Escape Mode Support To determine that a host supporting bidirectionality on Lane 0 while operating in Command Mode supports Escape mode. Test 5.3.5 ULPS Support Offered To determine that a host or peripheral supporting bidirectionality on Lane 0 while operating in Command Mode supports offering Escape mode entry to ULPS. Test 5.3.6 ULPS Support Received To determine that a host or peripheral supporting bidirectionality on Lane 0 while operating in Command Mode supports receiving Escape mode entry to ULPS. Not Applicable Not a command mode panel. Not Applicable Not a command mode panel. Not Applicable Not a command mode panel. Not Applicable Not a command mode panel. Not Applicable Not a command mode panel. Not Applicable Not a command mode panel. Chapter 5: DSI Physical Layer, Group 4: Video Mode Interfaces Test 5.4.1 Peripheral Video Mode Data Lane Module Requirements To determine that a DSI receiver data lane module operating in Video Mode supports CIL-SFAN (HS-RX, LP-RX). Test 5.4.2 Peripheral Video Mode Clock Lane Module Requirements To determine that a DSI receiver clock lane module operating in Video Mode supports CIL-SCNN (HS-RX, LP-RX). Test 5.4.3 Video Mode RESET Trigger Message Support To determine that a device operating in Video Mode supports Escape Mode properly. Test 5.4.4 Video Mode ULPS Support To determine that a device operating in Video Mode supports Escape Mode properly. 5 The peripheral properly receives HS video data. Refer to Figure 5. Refer to Figure 3 to see the panel respond to both HS and LP Transmissions. The peripheral properly receives HS video data. Refer to Figure 5. Refer to Figure 3 to see the panel respond to both HS and LP Transmissions. Not Applicable Can not implement with current software running on the test station. Not Applicable Can not implement with current software
running on the test station. Chapter 5: DSI Physical Layer, Group 5: Bidirectional Control Mechanism Test 5.5.1 Peripheral Transmits Bus Turn-Around Request To determine that a peripheral performs a Bus Turn-Around properly when it is finished transmitting a response to a host processor. The peripheral properly turns the bus back to the testing station. Refer to Figure 3. Chapter 5: DSI Physical Layer, Group 6: Clock Management Test 5.6.1 Continuous Clock Behavior To determine that a host claiming continuous clock behavior keeps the DSI Clock Lane active between HS data transmissions. Test 5.6.2 Non-Continuous Clock Behavior To determine that a host claiming non-continuous clock behavior drives the Clock Lane to LP-11 between HS data transmissions. Test 5.6.3 Escape Mode Non-Continuous Clock Frequency Matching To determine that a host claiming non-continuous clock behavior drives the Clock Lane to LP-11 during Escape Mode between HS data transmissions. The peripheral properly enters and exits HS while the clock lane is continuously active. Refer to Figure 6. The peripheral properly enters and exits HS while the clock lane is non-continuous. Refer to Figure 19. Not Applicable Not a peripheral test. Chapter 5: DSI Physical Layer, Group 7: System Power-Up and Initialization Test 5.7.1 TX-Stop Detection by Peripheral To determine that the Peripheral s D-PHY detects a TX-Stop state after power on. Informative The peripheral did not accept bus transaction after any of the cases were sent. This is verified because the testing station was waiting on a BTA that occurs at the end of the INIT. Chapter 6: Multi-Lane Distribution and Merging, Group 1: Multi-Lane Interoperability and Lane-number Mismatch Test 6.1.1 Proper Byte Distribution and Merging Over Multiple Lanes To determine that the Host Processor properly distributes and a Peripheral properly merges a transmitted or received stream of bytes. 6 The peripheral properly merges all of the bytes regardless of how many lanes are operating. This was verified by viewing an image on the screen for 1 lane, 2 lane, 3 lane, and 4 lane setups.
Test 6.1.2 Proper Byte Distribution and Merging for Odd Byte Counts To determine that the Host Processor properly distributes and a Peripheral properly merges a transmitted or received stream of bytes when the length of that stream of bytes is not an integer multiple of the number of lanes. Test 6.1.3 Proper Merging when Byte Stream Ends Early Verify proper behavior by a device when a received stream of bytes ends 2 cycles earlier on one lane than on all other lanes. The peripheral properly merges all of the bytes regardless of how many lanes are operating. This was verified by viewing an image on the screen for 1 lane, 2 lane, 3 lane, and 4 lane setups. This is a four lane device and it can be configured to run as either 1, 2, 3, or 4 lane system. All configurations function correctly. The same number of lanes are used by both the testing station and the peripheral. Refer to figure 1 to see the data be returned from the peripheral. The data did come back on lane 0 only. Test 6.1.4 Number of Lanes To verify that a host or peripheral in a system does not dynamically change the number of Lanes used. Test 6.1.5 Matching Number of Lanes To verify that a host and peripheral in a system support the same number of lanes. Test 6.1.6 LP Mode To determine that a peripheral operating in LP mode only uses Lane 0 to send data back to the host. The peripheral properly merges all of the bytes regardless of how many lanes are operating. This was verified by viewing an image on the screen for 1 lane, 2 lane, 3 lane, and 4 lane setups. Chapter 7: Low Level Protocol Errors and Contention, Group 1: Low-Level Protocol Errors Test 7.1.1 SoT Error Received by Peripheral To determine that the Peripheral properly handles a received SoT Error. Test 7.1.2 SoT Sync Error Received by Peripheral To determine that the Peripheral properly handles a received SoT Sync Error. Test 7.1.3 EoT Sync Error Received by Peripheral To determine that the Peripheral properly handles a received EoT Sync Error. Test 7.1.4 Escape Mode Entry Command Error Detected by Host or Peripheral 7 The peripheral properly received the SoT error. Refer to Figure 7 to see the SoT error flag set. The peripheral properly received the SoT sync error flag due to a multibit SoT error sent by the testing station. Refer to Figure 8. The peripheral properly detected the EoT error.
To determine that the Peripheral or Host properly handles a received Escape Mode Entry Command Error. Test 7.1.5 LP Transmission Sync Error Detected by Host or Peripheral To determine that the Peripheral or Host properly handles a received Escape Mode Entry Command Error. Test 7.1.6 No Valid Escape False Control Error Detected by Host or Peripheral To determine that the Peripheral or Host properly handles a received False Control Error. Test 7.1.7 No Turnaround Sequence False Control Error Detected by Host or Peripheral To determine that the Peripheral or Host properly handles a received False Control Error. The peripheral properly detects the escape mode entry command error. Refer to Figure 10. The peripheral properly detects the invalid LP transmission and sets the LP Transmission sync error flag. Refer the Figure 11. The peripheral properly detects the LP request followed by no command. This did set the False control error flag, refer to Figure 12. The peripheral properly detects the HS request followed by no command. Chapter 7: Low Level Protocol Errors and Contention, Group 2: Contention Detection and Recovery Test 7.2.1 LP High Fault Detected by Both Sides To verify that a device properly detects and responds to an LP high fault. Test 7.2.2 LP Low Fault Detected by Both Sides To verify that a device properly detects and responds to an LP low fault. Test 7.2.3 False LP Low Fault Not Detected To verify that a device does not incorrectly detect an LP low fault. Test 7.2.4 LP High Fault Detected by Host To verify that a host correctly detects an LP High fault. Test 7.2.5 LP Low Fault Detected by Host To verify that a host correctly detects an LP Low fault. Test 7.2.6 LP High Fault Detected by Peripheral To verify that a peripheral correctly detects an LP High fault. Test 7.2.7 LP Low Fault Detected by Peripheral To verify that a peripheral correctly detects an LP Low fault. 8 Refer to Figure 14. Refer to Figure 15. The peripheral does not transition to LP-RX upon reception of the false LP low fault. Refer to figure 15. Not Applicable Not a peripheral test. Not Applicable Not a peripheral test. Not Applicable Testing station is not properly driving contention as defined in spec. Not Applicable Testing station is not properly driving
Test 7.2.8 HS RX Timer To verify that a DSI peripheral properly implements the HS RX Timer. Test 7.2.9 LP TX Timer - Peripheral To verify that a bi-directional peripheral properly implements the LP TX Timer. contention as defined in spec. Not Applicable Timer value is unknown. Not Applicable Timer value is unknown. Chapter 7: Low Level Protocol Errors and Contention, Group 3: Additional Timers Test 7.3.1 Turnaround Acknowledge Timeout To verify that a Peripheral properly implements the TA_TO Timer. Test 7.3.2 Peripheral Reset Timeout To verify that a Peripheral properly implements the PR_TO Timer. Not Applicable Timer value is unknown. Not Applicable Timer value is unknown. Chapter 7: Low Level Protocol Errors and Contention, Group 4: Acknowledge and Error Reporting Mechanism Test 7.4.1 Acknowledge To verify that a Peripheral properly acknowledges packets received error-free. Test 7.4.2 Error Reported To verify that a Peripheral properly acknowledges packets received with errors. Test 7.4.3 Acknowledge READ Request To verify that a Peripheral properly acknowledges READ packets received error-free. Test 7.4.4 Error Reported on READ Request To verify that a Peripheral properly acknowledges READ packets received with errors. Test 7.4.5 Single Bit Error on READ Request To verify that a Peripheral properly acknowledges READ packets received with a correctable single bit error. Test 7.4.6 Error Register Cleared To verify that a Peripheral properly clears its error register after 9 The peripheral returned an ACK-TRIG response after the LP packet shown in Figure 1 was sent. The peripheral received an error after an HS packet shown in Figure 2. The peripheral properly received and returned the data which was sent to it. Refer to Figure 16. The peripheral detected errors and it did not transmit any read data only an error report packet. Refer to Figure 17. The peripheral properly transmitted the read data followed by an error report, reporting a one bit correctable ECC error. Refer to Figure 18.
reporting errors via an Acknowledge and Error Report packet. The error register is cleared properly refer to Figure 3. Section 3: Plots and Decode Data. Figure 1 Packets sent in entirety: Decode: Esc Entry : LP-10/00/01/00 Esc Command: 11100001 (LPDT) ******* BURST 1 CONTENTS (10 bytes extracted from burst, after Sync) ********** DSI PACKET DECODE (Long, 10 bytes, Host->Display) -------------------------VC : 00 DT : 0x29 (101001): Generic Long Write WC : 0x0004 (0000000000000100) (4 8-bit words) ECC: 0x3F (00111111) CRC: 0xF26E 29 04 00 3F 00 34 20 56 6E F2 BTA Request: LP-10/00/10/00 10
BTA Accept : LP-10/11 Esc Entry : LP-10/00/01/00 Esc Command: 00100001 (Unknown-4/Ack Trigger) BTA Request: LP-10/00/10/00 BTA Accept : LP-10/11 Esc Entry : LP-10/00/01/00 Esc Command: 11100001 (LPDT) ******* BURST 2 CONTENTS (4 bytes extracted from burst, after Sync) *********** DSI PACKET DECODE (Short, 4 bytes, Host->Display) -------------------------VC : 00 DT : 0x37 (110111): Set Maximum Return Packet Size WC : 0x0001 (0000000000000001) (0d1) ECC: 0x1D (00011101) 37 01 00 1D BTA Request: LP-10/00/10/00 BTA Accept : LP-10/11 Esc Entry : LP-10/00/01/00 Esc Command: 00100001 (Unknown-4/Ack Trigger) BTA Request: LP-10/00/10/00 BTA Accept : LP-10/11 Esc Entry : LP-10/00/01/00 Esc Command: 11100001 (LPDT) ******* BURST 3 CONTENTS (4 bytes extracted from burst, after Sync) *********** DSI PACKET DECODE (Short, 4 bytes, Host->Display) -------------------------VC : 00 DT : 0x24 (100100): Generic READ, 2 parameters WC : 0x3400 (0011010000000000) (0d13312) ECC: 0x1C (00011100) 24 00 34 1C BTA Request: LP-10/00/10/00 BTA Accept : LP-10/11 Esc Entry : LP-10/00/01/00 Esc Command: 11100001 (LPDT) ******* BURST 4 CONTENTS (4 bytes extracted from burst, after Sync) *********** DSI PACKET DECODE (Short, 4 bytes, Display->Host) -------------------------VC : 00 11
DT : 0x12 (010010): Generic Short READ Response, 2 bytes returned WC : 0x0000 (0000000000000000) (0d0) ECC: 0x18 (00011000) 12 00 00 18 BTA Request: LP-10/00/10/00 LP Decode Complete. (No states left) (dphygui.m): ================================================================== (dphygui.m): ===== LP DECODER Complete (29-Jul-2010 09:27:06) ================= (dphygui.m): ================================================================== Figure 2 Proper lane use in command mode: Decode: HS decode ******* BURST 1 CONTENTS (10 bytes extracted from burst, after Sync) ********** DSI PACKET DECODE (Long, 10 bytes, Host->Display) -------------------------VC : 00 DT : 0x29 (101001): Generic Long Write WC : 0x0004 (0000000000000100) (4 8-bit words) ECC: 0x3F (00111111) CRC: 0xF26E 29 04 00 3F 00 34 20 56 6E F2 LP DECODE: 12
13
Figure 3 Low Power Transmission: Decode: LP DECODE: Recovered State Sequence: (216 states total) (H=LP-11, L=LP-00, 1=LP-10, 0=LP-01) 1L0L1L1L1L0L0L0L0L1L1L0L0L1L0L1L0L0L0L0L1L0L0L0L0L 0L0L0L0L0L0L0L0L0L1L1L1L1L1L1L0L0L0L0L0L0L0L0L0L0L 0L0L1L0L1L1L0L0L0L0L0L0L0L1L0L0L0L1L1L0L1L0L1L0L0L 1L1L1L0L1L1L0L0L1L0L0L1L1L1L1L1H1L1L1H1L0L0L0L1L0L 0L0L0L1L1H1L1L1H Esc Entry : LP-10/00/01/00 Esc Command: 11100001 (LPDT) ******* BURST 1 CONTENTS (10 bytes extracted from burst, after Sync) ********** DSI PACKET DECODE (Long, 10 bytes, Host->Display) -------------------------VC : 00 DT : 0x29 (101001): Generic Long Write WC : 0x0004 (0000000000000100) (4 8-bit words) ECC: 0x3F (00111111) CRC: 0xF26E 29 04 00 3F 00 34 20 56 6E F2 BTA Request: LP-10/00/10/00 BTA Accept : LP-10/11 14
Esc Entry : LP-10/00/01/00 Esc Command: 00100001 (Unknown-4/Ack Trigger) BTA Request: LP-10/00/10/00 LP Decode Complete. (No states left) (dphygui.m): ================================================================== (dphygui.m): ===== LP DECODER Complete (29-Jul-2010 14:19:00) ================= (dphygui.m): ================================================================== HS decode: ******* BURST 1 CONTENTS (4 bytes extracted from burst, after Sync) *********** DSI PACKET DECODE (Short, 4 bytes, Host->Display) -------------------------VC : 00 DT : 0x37 (110111): Set Maximum Return Packet Size WC : 0x0001 (0000000000000001) (0d1) ECC: 0x1D (00011101) 37 01 00 1D ******************* No more bursts left. Decode complete. ******************** (dphygui.m): ================================================================== (dphygui.m): ===== HS DECODER Complete (29-Jul-2010 14:20:00) ================= (dphygui.m): ================================================================== LP DECODE: Recovered State Sequence: (98 states total) (H=LP-11, L=LP-00, 1=LP-10, 0=LP-01) 1L1L1H1L0L1L1L1L0L0L0L0L1L0L1L0L0L0L0L0L0L1L0L0L0L 0L0L0L0L0L1L0L0L0L0L0L1L0L0L0L1L1L0L0L0L1H1L1L1H BTA Request: LP-10/00/10/00 BTA Accept : LP-10/11 Esc Entry : LP-10/00/01/00 Esc Command: 11100001 (LPDT) ******* BURST 1 CONTENTS (4 bytes extracted from burst, after Sync) *********** DSI PACKET DECODE (Short, 4 bytes, Display->Host) -------------------------VC : 00 DT : 0x02 (000010): Acknowledge and Error Report WC : 0x8201 (1000001000000001) (0d33281) ECC: 0x18 (00011000) 02 01 82 18 ERROR REPORT DECODE: 1 = SoT Error 0 = SoT Sync Error 0 = EoT Sync Error 15
0 = Escape Mode Entry Command Error 0 = Low-Power Transmit Sync Error 0 = Peripheral Timeout Error 0 = False Control Error 0 = Contention Detected 0 = ECC Error, single-bit (detected and corrected) 1 = ECC Error, multi-bit (detected, not corrected) 0 = Checksum Error (Long packet only) 0 = DSI Data Type Not Recognized 0 = DSI VC ID Invalid 0 = Invalid Transmission Length 0 = Reserved 1 = DSI Protocol Violation BTA Request: LP-10/00/10/00 LP Decode Complete. (No states left) (dphygui.m): ================================================================== (dphygui.m): ===== LP DECODER Complete (29-Jul-2010 14:20:57) ================= (dphygui.m): ================================================================== LP DECODE: Recovered State Sequence: (314 states total) (H=LP-11, L=LP-00, 1=LP-10, 0=LP-01) 1L1L1H1L0L0L0L1L0L0L0L0L1L1H1L1L1H1L0L1L1L1L0L0L0L 0L1L0L0L1L0L0L1L0L0L0L0L0L0L0L0L0L0L0L0L1L0L1L1L0L 0L0L0L1L1L1L0L0L0L1H1L1L1H1L0L1L1L1L0L0L0L0L1L0L1L 0L1L1L0L0L0L0L0L1L0L0L0L0L0L0L0L0L0L0L0L0L0L1L0L1L 0L1L1L0L0L0L0L0L0L0L0L0L0L0L0L0L0L0L0L0L0L0L0L0L0L 0L0L0L0L0L0L0L0L0L0L0L0L1L0L0L0L0L1L0L0L1L1L0L0L0L 0L0L0L1H1L1L1H BTA Request: LP-10/00/10/00 BTA Accept : LP-10/11 Esc Entry : LP-10/00/01/00 Esc Command: 00100001 (Unknown-4/Ack Trigger) BTA Request: LP-10/00/10/00 BTA Accept : LP-10/11 Esc Entry : LP-10/00/01/00 Esc Command: 11100001 (LPDT) ******* BURST 1 CONTENTS (4 bytes extracted from burst, after Sync) *********** DSI PACKET DECODE (Short, 4 bytes, Host->Display) -------------------------VC : 00 DT : 0x24 (100100): Generic READ, 2 parameters WC : 0x3400 (0011010000000000) (0d13312) ECC: 0x1C (00011100) 16
24 00 34 1C BTA Request: LP-10/00/10/00 BTA Accept : LP-10/11 Esc Entry : LP-10/00/01/00 Esc Command: 11100001 (LPDT) ******* BURST 2 CONTENTS (10 bytes extracted from burst, after Sync) ********** DSI PACKET DECODE (Long, 10 bytes, Display->Host) -------------------------VC : 00 DT : 0x1A (011010): Generic Long READ Response WC : 0x0004 (0000000000000100) (4 8-bit words) ECC: 0x35 (00110101) CRC: 0x0321 1A 04 00 35 00 00 00 00 21 03 BTA Request: LP-10/00/10/00 LP Decode Complete. (No states left) (dphygui.m): ================================================================== (dphygui.m): ===== LP DECODER Complete (29-Jul-2010 14:21:48) ================= (dphygui.m): ================================================================== Figure 4 Command Mode Bidirectional Link Reverse Direction Escape Mode Support: Decode: 17
******* BURST 1 CONTENTS (10 bytes extracted from burst, after Sync) ********** DSI PACKET DECODE (Long, 10 bytes, Host->Display) -------------------------VC : 00 DT : 0x29 (101001): Generic Long Write WC : 0x0004 (0000000000000100) (4 8-bit words) ECC: 0x3F (00111111) CRC: 0xF26E 29 04 00 3F 00 34 20 56 6E F2 ******************* No more bursts left. Decode complete. ******************** LP DECODE: Recovered State Sequence: (98 states total) (H=LP-11, L=LP-00, 1=LP-10, 0=LP-01) 1L1L1H1L0L1L1L1L0L0L0L0L1L0L1L0L0L0L0L0L0L1L0L0L0L 0L0L1L0L0L1L0L0L0L0L0L0L1L0L0L1L0L0L0L0L1H1L1L1H BTA Request: LP-10/00/10/00 BTA Accept : LP-10/11 Esc Entry : LP-10/00/01/00 Esc Command: 11100001 (LPDT) ******* BURST 1 CONTENTS (4 bytes extracted from burst, after Sync) *********** DSI PACKET DECODE (Short, 4 bytes, Display->Host) -------------------------VC : 00 DT : 0x02 (000010): Acknowledge and Error Report WC : 0x0241 (0000001001000001) (0d577) ECC: 0x09 (00001001) 02 41 02 09 ERROR REPORT DECODE: 1 = SoT Error 0 = SoT Sync Error 0 = EoT Sync Error 0 = Escape Mode Entry Command Error 0 = Low-Power Transmit Sync Error 0 = Peripheral Timeout Error 1 = False Control Error 0 = Contention Detected 0 = ECC Error, single-bit (detected and corrected) 1 = ECC Error, multi-bit (detected, not corrected) 0 = Checksum Error (Long packet only) 0 = DSI Data Type Not Recognized 0 = DSI VC ID Invalid 18
0 = Invalid Transmission Length 0 = Reserved 0 = DSI Protocol Violation BTA Request: LP-10/00/10/00 LP Decode Complete. (No states left) Figure 5 Peripheral Video Mode Data Lane Module Requirements: Decode: ******* BURST 98 CONTENTS (4 bytes extracted from burst, after Sync) ********** DSI PACKET DECODE (Short, 4 bytes, Host->Display) -------------------------VC : 00 DT : 0x21 (100001): Sync Event, H Sync Start WC : 0x0000 (0000000000000000) (0d0) ECC: 0x12 (00010010) 21 00 00 12 ******* BURST 99 CONTENTS (2406 bytes extracted from burst, after Sync) ******* DSI PACKET DECODE (Long, 2406 bytes, Host->Display) -----------------------VC : 00 DT : 0x3E (111110): Packed Pixel Stream, 24-bit RGB, 8-8-8 Format WC : 0x0960 (0000100101100000) (2400 8-bit words) ECC: 0x04 (00000100) CRC: 0x6485 3E 60 09 04 A5 84 4F 9E 7A 48 B8 91 66 AB 84 5D 62 3A 17 45 1D 00 50 29 02 19
5E 39 0C 75 51 1D C4 A1 69 DB B7 7B D4 B0 76 D8 B3 7E D6 B0 7F AE 8A 5A 93 6E 41 63 3E 11 96 75 42 EA C9 94 E7 C8 8F E8 CA 8C F4 D6 96 E7 CB 8A A0 85 42 94 78 37 A4 88 49 BF 9F 66 94 70 3C 83 5D 30 79 52 2B 65 3C 1E 6C 47 2D 37 14 00 43 24 10 38 1D 0A 45 2C 16 62 48 2F 8B 70 53 A5 84 63 9E 78 53 59 2D 08 45 19 00 5E 37 10 B4 8E 69 C1 99 75 97 70 49 7B 51 2B A6 7C 56 B0 86 60 8E 64 3C BA 90 6A D4 AA 84 DB B1 8B D9 AE 8B B9 91 6E CB A2 82 BD 96 75 65 3E 1F 2F 0A 00 5A 36 1E 85 61 49 A3 80 6A 93 73 5E 92 73 5E 88 6B 59 89 6C 5C 57 3A 2C 47 2B 20 60 42 3A 49 2A 27 BA 9B 99 DB BB BC A2 82 85 30 11 16 29 0E 15 1B 04 0C 20 0B 14 1E 0A 13 18 07 0F 1B 0C 13 16 0A 0C 16 0A 0A 1B 10 0A 32 28 1E 5F 53 47 3B 2F 23 CA B9 B1 FF F1 EB FF F1 ED 97 83 84 1E 0E 11 2D 21 25 1B 0F 13 0A 01 04 0F 09 0B 06 04 05 07 05 06 00 00 00 01 03 02 00 01 00 00 00 00 01 01 01 06 02 03 08 04 05 0C 06 08 0E 08 0A 0B 07 06 03 00 00 15 11 10 3C 38 37 3C 38 37 19 15 14 0A 06 05 19 15 14 07 03 02 07 03 02 03 00 00 05 01 00 0D 09 08 07 03 02 03 00 00 04 03 01 05 05 07 0A 0C 0B 01 00 00 03 00 00 08 03 00 08 00 00 77 6C 70 B4 A9 B1 71 65 71 49 3C 4D 7E 71 85 74 68 7C 44 3B 4E 41 3A 4A 34 2E 3C 0D 0A 13 03 00 02 03 00 00 06 00 02 14 0E 10 20 17 1C 22 19 1E 24 1E 22 2A 24 26 4E 49 46 79 71 6E D6 CD C6 FF FA F1 FF EE E3 C9 AD A2 A1 7F 75 EE CF BD E4 CF B4 D9 C9 A8 FF F2 D1 FF F5 D3 F2 DF BE DF CC AB E0 CE AA CD BB 97 CC B8 95 EA D6 B3 D6 BF 9D E2 CB AB F6 DD BE EF D6 B7 FF E7 C9 FF EA C9 FE E1 B9 FF E0 B7 F8 DC B5 E8 CE AB FC E1 C3 FF E6 C9 93 75 59 90 71 55 CD A9 8F DF B7 9E BD 93 7B 78 4E 38 5E 34 24 36 0E 02 3D 17 0C 4E 2D 1C EB CC B0 CD B0 90 9E 83 65 FA E3 C4 DC C7 AC ED D7 BF F3 DD C6 EB D2 BE 8C 6F 5D 3E 21 0F 56 37 25 34 14 05 49 2B 20 3D 22 17 4D 35 2B 4D 39 30 5D 4A 46 3D 2B 29 2D 1B 19 1C 0D 0A 0C 00 00 08 00 00 06 00 00 04 00 00 04 00 01 01 00 00 00 00 00 00 01 00 00 01 00 00 01 00 00 02 01 02 02 00 03 00 00 06 00 00 36 28 25 58 46 44 41 29 27 38 1E 1D 4B 2F 2E 43 29 28 4E 36 36 63 4F 50 4A 37 39 31 21 22 40 31 34 4E 3F 42 4B 3C 41 3C 2D 32 46 37 3E 5B 4C 53 64 54 5E 5E 4E 58 48 38 42 3E 2E 38 42 35 3F 36 29 33 2A 1C 29 16 08 15 29 1B 28 25 17 26 14 08 16 11 05 13 26 1A 28 25 19 27 2A 1C 2B 12 04 13 6F 61 70 9A 8C 9B 63 52 62 35 24 34 5D 4B 5B BA A8 B6 9D 89 95 95 7F 8B 80 69 73 9F 88 90 DA C3 C9 D0 BA BD C8 AF B2 A7 8D 8E AB 8F 8E BE A2 A1 E2 C4 C2 FF E6 E4 CF B1 AF D0 B2 B0 FF E3 DF FF E6 E2 F8 DD D6 F9 E0 D9 E9 D3 C8 C3 AF A4 E2 D0 C4 EC DC CF F3 E6 D6 EB DE CD F5 E6 CF FE EE D5 F0 DF C5 FB E7 CC FF F6 D7 EB D4 B2 D6 BD 95 EB CF A7 F8 DB AF EF CF A6 FF E6 C1 E1 BE A0 9F 7A 67 6F 49 3E 73 4A 48 67 40 41 60 41 3F 7D 61 60 83 66 68 89 6C 6E AB 8E 92 A5 88 8C 9E 80 88 8B 70 79 8D 73 7E 8B 73 80 7E 68 75 7D 68 77 8E 7C 8C 98 87 97 9E 90 A1 B2 A4 B5 CB BD CE E4 D3 E3 FB EB F6 FE F1 F8 F2 E6 EA E7 DE E1 E8 E2 E4 ED EB EE F3 F4 F8 ED EE F3 F5 F4 FA FA F5 FC FC F1 F7 EB DA E0 FF F1 F3 D9 C2 C8 E9 D3 E0 F6 DF F1 F0 DA F1 CB B4 D0 BD A5 C5 A0 86 AB 92 78 9D 88 6E 91 6E 57 73 5F 49 60 60 4B 5E 51 3C 4B 33 1F 2B 22 0E 1A 26 12 1E 1C 08 14 0F 00 08 3B 2A 34 80 6E 7A AF 9D AB BC AA BA C7 B5 C3 BC AA B6 92 81 8B 33 22 28 2C 1C 1F 8D 7D 80 E2 D2 D5 F8 E7 EF D3 C2 CC C0 AE BC C5 B3 BF EC D9 DD F9 E5 E6 EB D5 D7 DC C3 C6 D7 BA BC CF B2 B4 FF E4 E6 FF F6 F6 DC BE BE BF A3 A0 B6 9A 97 B2 96 92 D3 BA B3 F4 DB D4 F7 DE D7 FF F8 ED FF F7 E4 FF E6 CC A7 80 61 5E 3D 1E E2 C9 B3 FF FB ED F9 EB E8 F4 EA E9 FF FE F8 F6 F7 F1 F2 FF F8 E9 FC F6 F6 FF FF FF FF FB FF EC E4 85 54 45 51 13 00 9F 63 49 CF A5 8D FF F8 E4 FF F3 E5 C6 AB A2 87 60 5B A1 70 6B A8 6F 66 A1 65 5A 7D 48 38 44 15 05 3F 1A 0A 20
50 33 25 5E 43 3A 3B 26 21 1D 10 0A 16 0B 05 1D 0E 07 17 03 00 33 17 09 66 43 30 9C 72 5C A5 76 5C 82 4F 34 81 49 2E 78 3F 24 77 3E 23 7F 45 2D 8E 54 3E 94 5C 45 98 63 51 99 69 5B 76 4B 42 5E 38 2F 5C 3A 31 5F 41 39 4E 35 2E 3E 2A 23 35 23 1F 2D 1E 1B 31 23 22 29 1B 1B 1B 0D 0D 31 23 23 40 30 31 26 16 19 1F 11 11 18 0E 0C 1C 13 0E 20 12 0F 25 13 11 39 20 23 78 5B 60 A5 84 8D 8C 66 71 71 47 51 86 57 5F 8B 57 59 89 4E 48 8C 48 3B 8B 40 29 9B 4A 2D BF 6C 40 D9 88 49 DD 8F 44 EB A4 56 DB 9C 4C E6 AF 5F EE C0 73 F3 CE 87 F1 D3 93 F1 DA A4 F2 E0 B2 F3 E3 BF F2 E3 C6 F2 E3 CC F5 E6 D1 F7 E8 D5 F7 E7 D8 F0 E3 DA F3 E8 E2 F4 E9 E5 EE E4 E2 EB E1 E2 EC E3 E6 EB E2 E7 E7 DD E5 EA E0 E9 E9 DF E8 E9 DD E7 E8 DC E6 E8 DB E4 E9 D9 E3 E8 D9 E0 E9 D8 E0 EB D8 DE EB D6 DD EE D4 DD EE D4 DD ED D3 DC E8 D1 D7 E5 D2 D8 E2 D3 D6 E3 D8 DC DC D6 D6 E3 DF E0 DC D8 D7 DC D3 D4 EB E1 E2 E7 D8 DB F6 E0 E3 F3 CF D3 FF EC EE F7 D0 D1 79 56 54 27 06 00 23 02 00 2D 0B 01 31 0B 00 3F 13 0A 43 0E 06 59 19 17 73 27 29 67 0D 16 62 00 0D 89 1E 2E F0 86 90 FF C2 BF D3 73 67 A2 3D 33 7F 18 0F 8B 23 1A 7B 15 09 6A 09 00 8B 2E 1D 9C 47 33 8C 3A 25 88 37 22 8F 3A 26 93 33 25 93 2B 20 94 21 1A 8F 15 10 96 16 13 91 0D 0B 94 10 0C 93 0F 0B 90 0C 08 B2 31 2C A3 23 20 93 16 14 96 18 19 89 0F 0E 88 11 0D 8D 1B 11 99 2B 1A AD 43 2B EA 82 65 FF A5 83 E5 93 6B FF B5 8B FF C5 9D FF AB 88 E2 81 60 8C 23 06 B6 49 2C CA 58 3D C7 54 39 F0 7F 61 D5 6A 4A ED 86 63 FD 9D 75 E9 90 64 FF AC 7D FF B4 82 F7 A8 70 FF BB 83 FF BB 87 E3 96 68 9C 4D 26 9E 4E 2D 83 2D 14 66 0B 00 70 10 04 85 24 1B 6F 0E 07 7C 1E 16 7F 25 1C 8B 34 2A B4 65 58 84 38 2A 50 08 00 8C 49 39 EE AF 9D DC A4 8D DA A8 8D EB BE 9D FF D7 B6 FF E0 BF FF E9 C9 D7 94 77 C6 7A 62 BA 6A 53 C7 76 63 C0 73 5F CF 88 74 B5 71 5E 8C 40 32 BE 72 64 D3 8E 7F 65 28 16 BF 8A 78 E1 B2 9E FF E8 D1 FF DE C6 FA D8 BD FF DF C3 F0 C7 A9 FF DA BC FF CC AE 93 56 37 FF C4 A4 F6 B1 92 79 32 14 92 49 28 C3 79 52 F2 A9 7E FF BB 8A F0 AE 7C EC B2 82 FF D3 A4 E4 B9 8F E8 C1 9A F0 C4 A1 CD 9B 78 FF C3 9E D5 90 67 FB AA 7F F4 A5 7C C9 82 62 F3 B4 93 FF D0 AC F9 BB 94 DA 9F 73 9B 65 37 D5 A2 77 DC AF 86 C5 9D 7A FF F7 DA FF EF D5 FA D6 C0 FF EB D8 50 27 15 44 19 08 4D 23 13 3B 13 0B 5E 37 30 3C 13 0D 4E 23 1D 6B 3E 39 57 26 21 5A 25 1F 55 1A 14 60 21 1A 6A 25 1E 74 2B 24 7D 30 28 84 35 2E 8A 3A 33 8E 3B 35 90 39 30 8C 30 23 98 3B 2C 96 36 26 93 33 23 A0 40 30 A3 44 32 9C 3B 2A 9B 3A 29 9E 3B 28 A1 3E 2B AE 49 35 AB 46 32 B2 4D 39 A2 3D 29 AD 47 31 BA 56 3F AF 4B 33 B0 4C 32 B4 50 36 B2 4E 34 BD 59 41 C1 5D 45 B7 53 3B BE 5A 42 CD 69 4F DB 77 5D D9 76 59 E3 80 61 DC 79 59 CB 68 48 D6 74 51 D4 72 4D D3 71 4A D0 6F 45 C4 63 39 CE 6D 42 CB 6A 3F C9 68 3D CF 6F 45 BC 5C 34 E2 84 5E DF 85 62 D8 7F 5F E5 8E 72 BF 69 50 B4 5F 4A DE 8C 77 DA 84 6D BD 5F 43 D4 75 55 DA 7B 5B CC 6F 4D CA 6D 4B BC 62 3F C6 6C 49 FF B0 8E E0 82 5E CE 6D 4A B8 56 33 D8 71 50 D7 6E 4E D2 67 47 D2 63 45 DF 71 50 D8 6A 49 CD 62 40 D0 6C 4A E0 81 61 C4 6B 4D 92 3E 22 6E 1E 07 71 24 12 7B 2F 21 72 2C 22 6B 28 20 62 26 1E 5B 24 1F 54 23 1C 4D 22 1B 49 21 19 49 1D 1A 4A 1E 1B 4C 20 1D 49 20 1A 46 1F 18 45 1E 17 46 1D 19 48 1F 1B 36 0A 0B 5D 2C 2F AE 77 7A C8 8D 8F AA 6A 68 AB 6A 64 B2 6E 63 B4 70 63 C0 7E 6E C0 81 6F C6 85 71 CF 8D 77 CD 89 74 BA 76 5F B2 6B 55 BC 75 5F CA 83 71 C3 7E 6E C8 82 76 DB 98 8F D4 93 8D C0 80 7E BD 7F 80 B9 7D 7F B6 79 80 AC 6E 79 AB 6D 7A A4 64 74 B3 73 83 C1 7F 8B B4 6F 74 CF 88 82 C7 7E 6D C4 76 5F C0 6D 4F C0 69 4B C5 65 4C A9 45 2E AC 45 36 AB 40 30 AB 3C 28 A4 3A 22 AC 4A 31 BC 66 4D C6 7E 66 D8 9B 86 85 64 21
******* BURST 100 CONTENTS (4 bytes extracted from burst, after Sync) ********* DSI PACKET DECODE (Short, 4 bytes, Host->Display) -------------------------VC : 00 DT : 0x21 (100001): Sync Event, H Sync Start WC : 0x0000 (0000000000000000) (0d0) ECC: 0x12 (00010010) 21 00 00 12 Figure 6 Continuous Clock behavior: Decode: N/A 22
Figure 7 SoT Error received by peripheral: ******* BURST 1 CONTENTS (4 bytes extracted from burst, after Sync) *********** DSI PACKET DECODE (Short, 4 bytes, Display->Host) -------------------------VC : 00 DT : 0x02 (000010): Acknowledge and Error Report WC : 0x0201 (0000001000000001) (0d513) ECC: 0x23 (00100011) 02 01 02 23 ERROR REPORT DECODE: 1 = SoT Error 0 = SoT Sync Error 0 = EoT Sync Error 0 = Escape Mode Entry Command Error 0 = Low-Power Transmit Sync Error 0 = Peripheral Timeout Error 0 = False Control Error 0 = Contention Detected 0 = ECC Error, single-bit (detected and corrected) 1 = ECC Error, multi-bit (detected, not corrected) 0 = Checksum Error (Long packet only) 0 = DSI Data Type Not Recognized 0 = DSI VC ID Invalid 0 = Invalid Transmission Length 0 = Reserved 0 = DSI Protocol Violation 23
Figure 8 SoT Sync error: ******* BURST 1 CONTENTS (4 bytes extracted from burst, after Sync) *********** DSI PACKET DECODE (Short, 4 bytes, Display->Host) -------------------------VC : 00 DT : 0x02 (000010): Acknowledge and Error Report WC : 0x0002 (0000000000000010) (0d2) ECC: 0x17 (00010111) 02 02 00 17 ERROR REPORT DECODE: 0 = SoT Error 1 = SoT Sync Error 0 = EoT Sync Error 0 = Escape Mode Entry Command Error 0 = Low-Power Transmit Sync Error 0 = Peripheral Timeout Error 0 = False Control Error 0 = Contention Detected 0 = ECC Error, single-bit (detected and corrected) 0 = ECC Error, multi-bit (detected, not corrected) 0 = Checksum Error (Long packet only) 0 = DSI Data Type Not Recognized 0 = DSI VC ID Invalid 0 = Invalid Transmission Length 0 = Reserved 24
Figure 9 Eot Sync Error: ******* BURST 1 CONTENTS (4 bytes extracted from burst, after Sync) *********** DSI PACKET DECODE (Short, 4 bytes, Display->Host) -------------------------VC : 00 DT : 0x02 (000010): Acknowledge and Error Report WC : 0x0201 (0000001000000001) (0d513) ECC: 0x23 (00100011) 02 01 02 23 ERROR REPORT DECODE: 1 = SoT Error 0 = SoT Sync Error 0 = EoT Sync Error 0 = Escape Mode Entry Command Error 0 = Low-Power Transmit Sync Error 0 = Peripheral Timeout Error 0 = False Control Error 0 = Contention Detected 0 = ECC Error, single-bit (detected and corrected) 1 = ECC Error, multi-bit (detected, not corrected) 0 = Checksum Error (Long packet only) 0 = DSI Data Type Not Recognized 25
0 = DSI VC ID Invalid 0 = Invalid Transmission Length 0 = Reserved 0 = DSI Protocol Violation Figure 10 Escape Mode Entry Command Error: ******* BURST 1 CONTENTS (4 bytes extracted from burst, after Sync) *********** DSI PACKET DECODE (Short, 4 bytes, Display->Host) -------------------------VC : 00 DT : 0x02 (000010): Acknowledge and Error Report WC : 0x0008 (0000000000001000) (0d8) ECC: 0x2E (00101110) 02 08 00 2E ERROR REPORT DECODE: 0 = SoT Error 0 = SoT Sync Error 0 = EoT Sync Error 1 = Escape Mode Entry Command Error 0 = Low-Power Transmit Sync Error 0 = Peripheral Timeout Error 0 = False Control Error 0 = Contention Detected 0 = ECC Error, single-bit (detected and corrected) 0 = ECC Error, multi-bit (detected, not corrected) 0 = Checksum Error (Long packet only) 26
0 = DSI Data Type Not Recognized 0 = DSI VC ID Invalid 0 = Invalid Transmission Length 0 = Reserved 0 = DSI Protocol Violation 0 bytes remaining... (Done, no complete packets left Figure 11 LP Transmission Sync Error Flag: ******* BURST 1 CONTENTS (3.125 bytes extracted from burst, after Sync) ******* *** ERROR *** :(decodedsipacket.m): Invalid packet, contains < 32 bits. Aborting packet decode. BTA Request: LP-10/00/10/00 BTA Accept : LP-10/11 Esc Entry : LP-10/00/01/00 Esc Command: 11100001 (LPDT) ******* BURST 2 CONTENTS (4 bytes extracted from burst, after Sync) *********** DSI PACKET DECODE (Short, 4 bytes, Display->Host) -------------------------VC : 00 DT : 0x02 (000010): Acknowledge and Error Report WC : 0x0010 (0000000000010000) (0d16) ECC: 0x2D (00101101) 02 10 00 2D ERROR REPORT DECODE: 27
0 = SoT Error 0 = SoT Sync Error 0 = EoT Sync Error 0 = Escape Mode Entry Command Error 1 = Low-Power Transmit Sync Error 0 = Peripheral Timeout Error 0 = False Control Error 0 = Contention Detected 0 = ECC Error, single-bit (detected and corrected) 0 = ECC Error, multi-bit (detected, not corrected) 0 = Checksum Error (Long packet only) 0 = DSI Data Type Not Recognized 0 = DSI VC ID Invalid 0 = Invalid Transmission Length 0 = Reserved 0 = DSI Protocol Violation BTA Request: LP-10/00/10/00 Figure 12 False control error due to LP request: ******* BURST 1 CONTENTS (4 bytes extracted from burst, after Sync) *********** DSI PACKET DECODE (Short, 4 bytes, Display->Host) -------------------------VC : 00 DT : 0x02 (000010): Acknowledge and Error Report 28
WC : 0x0040 (0000000001000000) (0d64) ECC: 0x21 (00100001) 02 40 00 21 ERROR REPORT DECODE: 0 = SoT Error 0 = SoT Sync Error 0 = EoT Sync Error 0 = Escape Mode Entry Command Error 0 = Low-Power Transmit Sync Error 0 = Peripheral Timeout Error 1 = False Control Error 0 = Contention Detected 0 = ECC Error, single-bit (detected and corrected) 0 = ECC Error, multi-bit (detected, not corrected) 0 = Checksum Error (Long packet only) 0 = DSI Data Type Not Recognized 0 = DSI VC ID Invalid 0 = Invalid Transmission Length 0 = Reserved 0 = DSI Protocol Violation 29
Figure 13 False control error due to HS request: Decode: ******* BURST 1 CONTENTS (4 bytes extracted from burst, after Sync) *********** DSI PACKET DECODE (Short, 4 bytes, Display->Host) -------------------------VC : 00 DT : 0x02 (000010): Acknowledge and Error Report WC : 0x0040 (0000000001000000) (0d64) ECC: 0x21 (00100001) 02 40 00 21 ERROR REPORT DECODE: 0 = SoT Error 0 = SoT Sync Error 0 = EoT Sync Error 0 = Escape Mode Entry Command Error 0 = Low-Power Transmit Sync Error 0 = Peripheral Timeout Error 1 = False Control Error 0 = Contention Detected 0 = ECC Error, single-bit (detected and corrected) 0 = ECC Error, multi-bit (detected, not corrected) 0 = Checksum Error (Long packet only) 0 = DSI Data Type Not Recognized 0 = DSI VC ID Invalid 0 = Invalid Transmission Length 0 = Reserved 0 = DSI Protocol Violation 30
BTA Request: LP-10/00/10/00 Figure 14 LP High Fault: Decode: N/A Figure 15 LP Low Fault: Decode: N/A 31
Figure 16 Writing generic data and seeing it be returned: ******* BURST 1 CONTENTS (16 bytes extracted from burst, after Sync) ********** DSI PACKET DECODE (Long, 12 bytes, Host->Display) -------------------------VC : 00 DT : 0x29 (101001): Generic Long Write WC : 0x0006 (0000000000000110) (6 8-bit words) ECC: 0x23 (00100011) CRC: 0x84DE 29 06 00 23 54 04 11 22 33 44 DE 84 4 bytes remaining... DSI PACKET DECODE (Short, 4 bytes, Host->Display) -------------------------VC : 00 DT : 0x24 (100100): Generic READ, 2 parameters WC : 0x0454 (0000010001010100) (0d1108) ECC: 0x03 (00000011) FULL HEX PACKET DUMP: (Each byte be appears LSB first on the wire) 24 54 04 03 BTA Request: LP-10/00/10/00 BTA Accept : LP-10/11 Esc Entry : LP-10/00/01/00 Esc Command: 11100001 (LPDT) ******* BURST 2 CONTENTS (10 bytes extracted from burst, after Sync) ********** 32
DSI PACKET DECODE (Long, 10 bytes, Display->Host) -------------------------VC : 00 DT : 0x1A (011010): Generic Long READ Response WC : 0x0004 (0000000000000100) (4 8-bit words) ECC: 0x35 (00110101) CRC: 0x40F1 1A 04 00 35 11 00 33 00 F1 40 BTA Request: LP-10/00/10/00 LP Decode Complete. (No states left) Figure 17 No read data returned only error report: ******* BURST 1 CONTENTS (4 bytes extracted from burst, after Sync) *********** DSI PACKET DECODE (Short, 4 bytes, Display->Host) -------------------------VC : 00 DT : 0x02 (000010): Acknowledge and Error Report WC : 0x0201 (0000001000000001) (0d513) ECC: 0x23 (00100011) 02 01 02 23 ERROR REPORT DECODE: 1 = SoT Error 0 = SoT Sync Error 33
0 = EoT Sync Error 0 = Escape Mode Entry Command Error 0 = Low-Power Transmit Sync Error 0 = Peripheral Timeout Error 0 = False Control Error 0 = Contention Detected 0 = ECC Error, single-bit (detected and corrected) 1 = ECC Error, multi-bit (detected, not corrected) 0 = Checksum Error (Long packet only) 0 = DSI Data Type Not Recognized 0 = DSI VC ID Invalid 0 = Invalid Transmission Length 0 = Reserved 0 = DSI Protocol Violation BTA Request: LP-10/00/10/00 LP Decode Complete. (No states left) Figure 18 Read data and error report returned: Decode: LP DECODE: Recovered State Sequence: (558 states total) (H=LP-11, L=LP-00, 1=LP-10, 0=LP-01) 1L0L1L1L1L0L0L0L0L1L1L0L0L1L0L1L0L0L0L1L1L0L0L0L0L 0L0L0L0L0L0L0L0L0L1L1L0L0L0L1L0L0L0L0L1L0L1L0L1L0L 34
0L0L1L0L0L0L0L0L1L0L0L0L1L0L0L0L0L1L0L0L0L1L0L0L1L 1L0L0L1L1L0L0L0L0L1L0L0L0L1L0L0L1L1L1L1L0L1L1L0L0L 1L0L0L0L0L1L0L0L1L0L0L1L0L0L0L0L1L0L1L0L1L0L0L0L1L 0L0L0L0L0L0L1L0L0L0L0L0L0L1H1L1L1H1L0L1L1L1L0L0L0L 0L1L0L1L0L1L1L0L0L0L0L0L1L0L0L0L0L0L0L0L0L0L0L0L0L 0L1L0L1L0L1L1L0L0L1L0L0L0L1L0L0L0L0L0L0L0L0L0L0L0L 1L1L0L0L1L1L0L0L0L0L0L0L0L0L0L0L1L0L0L0L1L1L1L1L0L 0L0L0L0L0L1L0L1H1L0L1L1L1L0L0L0L0L1L0L1L0L0L0L0L0L 0L0L0L0L0L0L0L0L0L1L0L0L0L0L0L0L0L0L1L0L1L1L1L0L0L 1H1L1L1H Esc Entry : LP-10/00/01/00 Esc Command: 11100001 (LPDT) ******* BURST 1 CONTENTS (16 bytes extracted from burst, after Sync) ********** DSI PACKET DECODE (Long, 12 bytes, Host->Display) -------------------------VC : 00 DT : 0x29 (101001): Generic Long Write WC : 0x0006 (0000000000000110) (6 8-bit words) ECC: 0x23 (00100011) CRC: 0x84DE 29 06 00 23 54 04 11 22 33 44 DE 84 4 bytes remaining... DSI PACKET DECODE (Short, 4 bytes, Host->Display) -------------------------VC : 00 DT : 0x24 (100100): Generic READ, 2 parameters WC : 0x0454 (0000010001010100) (0d1108) ECC: 0x02 (00000010) (*** INVALID ECC ***, Calculated: 00000011) 24 54 04 02 BTA Request: LP-10/00/10/00 BTA Accept : LP-10/11 Esc Entry : LP-10/00/01/00 Esc Command: 11100001 (LPDT) ******* BURST 2 CONTENTS (10 bytes extracted from burst, after Sync) ********** DSI PACKET DECODE (Long, 10 bytes, Display->Host) -------------------------VC : 00 DT : 0x1A (011010): Generic Long READ Response WC : 0x0004 (0000000000000100) (4 8-bit words) ECC: 0x35 (00110101) CRC: 0x40F1 1A 04 00 35 11 00 33 00 F1 40 35
Esc Entry : LP-10/00/01/00 Esc Command: 11100001 (LPDT) ******* BURST 3 CONTENTS (4 bytes extracted from burst, after Sync) *********** DSI PACKET DECODE (Short, 4 bytes, Display->Host) -------------------------VC : 00 DT : 0x02 (000010): Acknowledge and Error Report WC : 0x0100 (0000000100000000) (0d256) ECC: 0x3A (00111010) 02 00 01 3A ERROR REPORT DECODE: 0 = SoT Error 0 = SoT Sync Error 0 = EoT Sync Error 0 = Escape Mode Entry Command Error 0 = Low-Power Transmit Sync Error 0 = Peripheral Timeout Error 0 = False Control Error 0 = Contention Detected 1 = ECC Error, single-bit (detected and corrected) 0 = ECC Error, multi-bit (detected, not corrected) 0 = Checksum Error (Long packet only) 0 = DSI Data Type Not Recognized 0 = DSI VC ID Invalid 0 = Invalid Transmission Length 0 = Reserved 0 = DSI Protocol Violation Figure 19 Non-Continuous Clocking: 36
Decode: N/A 37