PIC6F87X 3.0 INSTRUCTION SET SUMMARY Each PIC6F87X instruction is a 4bit word, divided into an OPCODE which specifies the instruction type and one or more operands which further specify the operation of the instruction. The PIC6F87X instruction set summary in Table 3 lists byteoriented, bitoriented, and literal and control operations. Table 3 shows the opcode field descriptions. For byteoriented instructions, f represents a file register designator and d represents a destination designator. The file register designator specifies which file register is to be used by the instruction. The destination designator specifies where the result of the operation is to be placed. If d is zero, the result is placed in the W register. If d is one, the result is placed in the file register specified in the instruction. For bitoriented instructions, b represents a bit field designator which selects the number of the bit affected by the operation, while f represents the address of the file in which the bit is located. For literal and control operations, represents an eight or eleven bit constant or literal value. TABLE 3: Field f W b OPCODE FIELD DESCRIPTIONS Description Register file address (0x to 0x7F) Woring register (accumulator) Bit address within an 8bit file register Literal field, constant data or label x Don't care location (= 0 or ). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. d Destination select; d = 0: store result in W, d = : store result in file register f. Default is d =. PC TO PD Program Counter Timeout bit Powerdown bit The instruction set is highly orthogonal and is grouped into three basic categories: Byteoriented operations Bitoriented operations Literal and control operations All instructions are executed within one single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. In this case, the execution taes two instruction cycles with the second cycle executed as a NOP. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is µs. If a conditional test is true, or the program counter is changed as a result of an instruction, the instruction execution time is µs. Table 3 lists the instructions recognized by the MPASM TM assembler. Figure 3 shows the general formats that the instructions can have. Note: All examples use the following format to represent a hexadecimal number: 0xhh where h signifies a hexadecimal digit. FIGURE 3: To maintain upward compatibility with future PIC6F87X products, do not use the OPTION and TRIS instructions. GENERAL FORMAT FOR INSTRUCTIONS Byteoriented file register operations 3 8 7 6 0 OPCODE d f (FILE #) d = 0 for destination W d = for destination f f = 7bit file register address Bitoriented file register operations 3 0 9 7 6 0 OPCODE b (BIT #) f (FILE #) b = 3bit bit address f = 7bit file register address Literal and control operations General 3 8 7 0 OPCODE (literal) = 8bit immediate value CALL and GOTO instructions only 3 0 0 OPCODE (literal) = bit immediate value A description of each instruction is available in the PICmicro MidRange Reference Manual, (DS3303). Microchip Technology Inc. DS309Cpage 35
PIC6F87X TABLE 3: PIC6F87X INSTRUCTION SET Mnemonic, Operands Description Cycles MSb 4Bit Opcode LSb Status Affected Notes ADDWF ANDWF CLRF CLRW COMF DECF DECFS INCF INCFS IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF BCF BSF BTFSC BTFSS ADDLW ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW f f f, b f, b f, b f, b Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Sip if 0 Increment f Increment f, Sip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Swap nibbles in f Exclusive OR W with f Bit Clear f Bit Set f Bit Test f, Sip if Clear Bit Test f, Sip if Set Add literal and W AND literal with W Call subroutine Clear Watchdog Timer Go to address Inclusive OR literal with W Move literal to W Return from interrupt Return with literal in W Return from Subroutine Go into standby mode Subtract W from literal Exclusive OR literal with W BYTEORIENTED FILE REGISTER OPERATIONS () () BITORIENTED FILE REGISTER OPERATIONS () () 0 0 0 0 LITERAL AND CONTROL OPERATIONS 0 0 0 0 0 0 0 0 0 0 0 bb 0bb 0bb bb x 0 0 xx 0xx 0x lfff 0xxx lfff 0xx0 bfff bfff bfff bfff xxxx 0 0 C,DC, C C C,DC, C,DC, TO,PD TO,PD C,DC, Note : When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, ), the value used will be that value present on the pins themselves. For example, if the data latch is for a pin configured as input and is driven low by an external device, the data will be written bac with a 0. : If this instruction is executed on the TMR0 register (and, where applicable, d = ), the prescaler will be cleared if assigned to the Timer0 module. 3: If Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP.,,,,,,3,,,3,,,,,,,,, 3 3 Note: Additional information on the midrange instruction set is available in the PICmicro MidRange MCU Family Reference Manual (DS3303). DS309Cpage 36 Microchip Technology Inc.
PIC6F87X 3. Instruction Descriptions ADDLW Add Literal and W [label] ADDLW Operands: 0 55 Operation: (W) + (W) Status Affected: C, DC, Description: The contents of the W register are added to the eight bit literal and the result is placed in the W register. BCF Bit Clear f [label] BCF f,b Operands: 0 f 7 0 b 7 Operation: 0 (f<b>) Description: Bit 'b' in register 'f' is cleared. ADDWF Add W and f [label] ADDWF f,d Operands: 0 f 7 d [0,] Operation: (W) + (f) (destination) Status Affected: C, DC, Description: Add the contents of the W register with If d is 0, the result is stored in the W register. If d is, the result is stored bac in BSF Bit Set f [label] BSF f,b Operands: 0 f 7 0 b 7 Operation: (f<b>) Description: Bit 'b' in register 'f' is set. ANDLW AND Literal with W [label] ANDLW Operands: 0 55 Operation: (W).AND. () (W) Status Affected: Description: The contents of W register are AND ed with the eight bit literal ''. The result is placed in the W register. BTFSS Bit Test f, Sip if Set [label] BTFSS f,b Operands: 0 f 7 0 b < 7 Operation: sip if (f<b>) = Description: If bit 'b' in register 'f' is '0', the next instruction is executed. If bit 'b' is '', then the next instruction is discarded and a NOP is executed instead, maing this a TCY instruction. ANDWF AND W with f [label] ANDWF f,d Operands: 0 f 7 d [0,] Operation: (W).AND. (f) (destination) Status Affected: Description: AND the W register with register 'f'. If 'd' is 0, the result is stored in the W register. If 'd' is, the result is stored bac in register 'f'. BTFSC Bit Test, Sip if Clear [label] BTFSC f,b Operands: 0 f 7 0 b 7 Operation: sip if (f<b>) = 0 Description: If bit 'b' in register 'f' is '', the next instruction is executed. If bit 'b', in register 'f', is '0', the next instruction is discarded, and a NOP is executed instead, maing this a TCY instruction. Microchip Technology Inc. DS309Cpage 37
PIC6F87X CALL Call Subroutine [ label ] CALL Operands: 0 047 Operation: (PC)+ TOS, PC<0:0>, (PCLATH<4:3>) PC<:> Description: Call Subroutine. First, return address (PC+) is pushed onto the stac. The elevenbit immediate address is loaded into PC bits <0:0>. The upper bits of the PC are loaded from PCLATH. CALL is a twocycle instruction. CLRWDT Operands: Operation: Status Affected: Description: Clear Watchdog Timer [ label ] CLRWDT None h WDT 0 WDT prescaler, TO PD TO, PD CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set. CLRF Clear f [label] CLRF f Operands: 0 f 7 Operation: h (f) Status Affected: cleared and the bit is set. COMF Complement f [ label ] COMF f,d Operands: 0 f 7 d [0,] Operation: (f) (destination) Status Affected: complemented. If d is 0, the result is stored in W. If d is, the result is stored bac in CLRW Operands: Operation: Status Affected: Description: Clear W [ label ] CLRW None h (W) W register is cleared. ero bit () is set. DECF Decrement f [label] DECF f,d Operands: 0 f 7 d [0,] Operation: (f) (destination) Status Affected: Description: Decrement If d is 0, the result is stored in the W register. If d is, the result is stored bac in DS309Cpage 38 Microchip Technology Inc.
PIC6F87X DECFS Decrement f, Sip if 0 [ label ] DECFS f,d Operands: 0 f 7 d [0,] Operation: (f) (destination); sip if result = 0 decremented. If d is 0, the result is placed in the W register. If d is, the result is placed bac in If the result is, the next instruction is executed. If the result is 0, then a NOP is executed instead maing it a TCY instruction. INCFS Increment f, Sip if 0 [ label ] INCFS f,d Operands: 0 f 7 d [0,] Operation: (f) + (destination), sip if result = 0 incremented. If d is 0, the result is placed in the W register. If d is, the result is placed bac in If the result is, the next instruction is executed. If the result is 0, a NOP is executed instead, maing it a TCY instruction. GOTO Unconditional Branch [ label ] GOTO Operands: 0 047 Operation: PC<0:0> PCLATH<4:3> PC<:> Description: GOTO is an unconditional branch. The elevenbit immediate value is loaded into PC bits <0:0>. The upper bits of PC are loaded from PCLATH<4:3>. GOTO is a twocycle instruction. IORLW Inclusive OR Literal with W [ label ] IORLW Operands: 0 55 Operation: (W).OR. (W) Status Affected: Description: The contents of the W register are OR ed with the eight bit literal ''. The result is placed in the W register. INCF Increment f [ label ] INCF f,d Operands: 0 f 7 d [0,] Operation: (f) + (destination) Status Affected: incremented. If d is 0, the result is placed in the W register. If d is, the result is placed bac in IORWF Inclusive OR W with f [ label ] IORWF f,d Operands: 0 f 7 d [0,] Operation: (W).OR. (f) (destination) Status Affected: Description: Inclusive OR the W register with register 'f'. If 'd' is 0 the result is placed in the W register. If 'd' is the result is placed bac in register 'f'. Microchip Technology Inc. DS309Cpage 39
PIC6F87X MOVF Move f [ label ] MOVF f,d Operands: 0 f 7 d [0,] Operation: (f) (destination) Status Affected: Description: The contents of register f are moved to a destination dependant upon the status of d. If d = 0, destination is W register. If d =, the destination is file register f itself. d = is useful to test a file register, since status flag is affected. NOP No Operation [ label ] NOP Operands: None Operation: No operation Description: No operation. MOVLW Move Literal to W [ label ] MOVLW Operands: 0 55 Operation: (W) Description: The eight bit literal is loaded into W register. The don t cares will assemble as 0 s. RETFIE Return from Interrupt [ label ] RETFIE Operands: None Operation: TOS PC, GIE MOVWF Move W to f [ label ] MOVWF f Operands: 0 f 7 Operation: (W) (f) Description: Move data from W register to register 'f'. RETLW Return with Literal in W [ label ] RETLW Operands: 0 55 Operation: (W); TOS PC Description: The W register is loaded with the eight bit literal ''. The program counter is loaded from the top of the stac (the return address). This is a twocycle instruction. DS309Cpage 40 Microchip Technology Inc.
PIC6F87X RLF Rotate Left f through Carry [ label ] RLF f,d Operands: 0 f 7 d [0,] Operation: See description below Status Affected: C rotated one bit to the left through the Carry Flag. If d is 0, the result is placed in the W register. If d is, the result is stored bac in C Register f SLEEP Operands: Operation: Status Affected: Description: [ label ] SLEEP None h WDT, 0 WDT prescaler, TO, 0 PD TO, PD The powerdown status bit, PD is cleared. Timeout status bit, TO is set. Watchdog Timer and its prescaler are cleared. The processor is put into SLEEP mode with the oscillator stopped. RETURN Return from Subroutine [ label ] RETURN Operands: None Operation: TOS PC Description: Return from subroutine. The stac is POPed and the top of the stac (TOS) is loaded into the program counter. This is a twocycle instruction. SUBLW Subtract W from Literal [ label ] SUBLW Operands: 0 55 Operation: (W) (W) Status Affected: C, DC, Description: The W register is subtracted ( s complement method) from the eightbit literal ''. The result is placed in the W register. RRF Rotate Right f through Carry [ label ] RRF f,d Operands: 0 f 7 d [0,] Operation: See description below Status Affected: C rotated one bit to the right through the Carry Flag. If d is 0, the result is placed in the W register. If d is, the result is placed bac in C Register f SUBWF Subtract W from f [ label ] SUBWF f,d Operands: 0 f 7 d [0,] Operation: (f) (W) (destination) Status C, DC, Affected: Description: Subtract ( s complement method) W register from register 'f'. If 'd' is 0, the result is stored in the W register. If 'd' is, the result is stored bac in register 'f'. Microchip Technology Inc. DS309Cpage 4
PIC6F87X SWAPF Swap Nibbles in f [ label ] SWAPF f,d Operands: 0 f 7 d [0,] Operation: (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) Description: The upper and lower nibbles of register f are exchanged. If d is 0, the result is placed in the W register. If d is, the result is placed in XORWF Exclusive OR W with f [label] XORWF f,d Operands: 0 f 7 d [0,] Operation: (W).XOR. (f) (destination) Status Affected: Description: Exclusive OR the contents of the W register with register 'f'. If 'd' is 0, the result is stored in the W register. If 'd' is, the result is stored bac in register 'f'. XORLW Exclusive OR Literal with W [label] XORLW Operands: 0 55 Operation: (W).XOR. (W) Status Affected: Description: The contents of the W register are XOR ed with the eightbit literal ''. The result is placed in the W register. DS309Cpage 4 Microchip Technology Inc.