Introduction to Ethernet and lab3.3 maglun@sm.luth.se Nov 200 Computation structures Agenda Introduction History Components (MAC, PHY) Packet format CRC Bit order Hubs, Switches and Routers Questions
Computation structures 2 What is (the) Ethernet Ethernet is a network BUS Ethernet is packet based Ethernet is available as 0 Mbit/s - 0 Gbit/s Ethernet is based on the CSMA/CD (Carrier Sense Multiple Access with Collision Detect access) protocol Computation structures 3 Ethernet Basics Ethernet Packets are from 64 bytes up to 58 bytes Since Ethernet is a BUS several Attached Units can talk on the BUS at the same time Collisions occur and the talking parties backoff for a time and then try again For each failed attempt the backoff time is increased exponentially
Computation structures 4 OSI model OSI Model Application L7 Presentation Session Transport Network Datalink Physical L On The OSI model with 7 layers, Ethernet is in the bottom two layers: Data Link Layer and Physical Layer OSI (Open Systems Interconnection) Computation structures 5 History of Ethernet Developed by Xerox at their PARC Research Facility by Bob Metcalfe and David Boggs First version was 3 Mbit /s Initial Ethernet standard developed by Digital, Intel and Xerox in the DIX consortium Standard for 0 Mbit/s called The Blue book was ready in 980 Standard was then submitted to a newly formed working group in IEEE called 802 IEEE splits the 802 working group in four parts 802.3 becomes the Ethernet working group
Computation structures 6 History of Ethernet Late 982 DIX s Bluebook and the IEEE 802.3 specifications merge into one standard Ethernet was already multi vendor and more company s endorsed the standard Ethernet vs 802.3 CSMA/CD Ethernet patents where inexpensive and easy to license Ethernet was developed into several different mediums. Coaxial/UTP/Optical Computation structures 7 Components MAC PHY MAU FPGA MII MDI MAC Media Access Control PHY Physical layer device MAU Medium Attachment Unit (RJ45 connector) MII Media Independant Interface MDI Media Dependant Interface
Computation structures 8 MAC - Media Access Controller Does statistical functions : Packet Lengths, Packet collisions etc. Does the stripping and adding of the preamble bits and the CRC calculations Communicates with the rest of the design Back off mechanism with random delay in case of collision A MAC usually has two different datapaths one for internal clock (Sending) and one external (Receiving) Computation structures 9 Media Independent Interface - MII This is the interface between the PHY and the MAC Regardless of the underlying Media this interface always stays the same MII is for 0 and 00 Mbit Ethernet. First bit from MAC First Nibble Second Nibble D0 D D2 D3 D4 D5 D6 D7 MSB D0 D D2 LSB D3
Computation structures 0 Media Independent Interface - MII The MII consists of 0 different signals Transmit Clock (TX_CLK) which runs at either 2.5 Mhz for 0 Mbit or 25 Mhz for 00 Mbit Transmit Data (TXD <3:0>) data nibble to the PHY circuit from MAC Transmit Enable (TX_EN) is high when data on the TXD pins are valid Transmit Error (TX_ERR) goes high when the PHY is coding incorrectly, not used in 0 Mbit Computation structures Media Independent Interface - MII Receive Clock (RX_CLK) generated by the PHY for incoming data Receive Data (RXD <3:0>) data from the sender decoded by the PHY to MAC Receive Data Valid (RX_DV) asserted when there is valid data on the RXD path Receive Error (RX_ER) asserted to indicate that something in the coding layer is wrong etc Carrier Sense (CRS) asserted by the PHY to indicate someone else is sending data Collision (COL) asserted by the PHY when a collision has taken/is taking place, useless if working in full duplex mode
Computation structures 2 MII - Sending Packets TX_CLK TX_EN TXD<3:0> COL CRS Computation structures 3 MII - Receiving Packets RX_CLK RX_DV RXD<3:0> COL CRS
Computation structures 4 PHY Encodes/Decodes (Manchester coding for 0 Mbit/s) Converts from parallel to serial Detects collisions Auto-negotiation Computation structures 5 Ethernet Packet Format Preamble Destination Addr. Source Addr. Etype/Length Data FCS 8 Bytes 6 Bytes 6 Bytes 2 Bytes 46 500 Bytes 4 Bytes
Computation structures 6 Preamble Preamble is used by the PHY to sync its RX_CLK to the transmitters TX_CLK. The Preamble consists of 8 bytes of alternating ones and zeros The two last bits of the preamble field are both high and are called the synch sequence, it is used to signal that the preamble ends and the Destination address begins. Computation structures 7 Destination and Source address Both Addresses are 6 bytes each and consists of two parts: 3 Bytes Vendor code (0x00003F = Syntrex Inc) 3 Bytes Serial number (0x000000) This address are sometimes callad MAC-address Stored in ROM in a NIC 0xFFFFFFFFFFFF is the broadcast address.
Computation structures 8 Type/Length Length / Etype field is either a type field or length. if the value is smaller than 0x0600 it contains length, otherwise it is an Ethernet Type 0x0800 is IPv4 Datagram 0x0806 is ARP 0x8DD is IPv6 Datagram 0x00 is experimental(below 0x0600?) Computation structures 9 Data Minimum data size 46 Bytes Maximum data size 500 Bytes If actual data is less than 46 Bytes the packet is padded with zeros
Computation structures 20 Frame Check Sequence (FCS) 4 Bytes used to detect bit faults in the packet Computed with the CRC-32 algorithm Computed on the Destination Address, Source Address, type and data fields. Computation structures 2 CRC theory () M F T P DA, SA, type and data fields, k bits long. The FCS field, n bits long. M and F concatenated.(k+n bits long). The CRC Polynomial. A pattern of n+ bits. (2) (3)
Computation structures 22 (4) But any binary number added to itself in a modulo 2 field yields zero so: (5) Computation structures 23 CRC polynomial The CRC polynomial for Ethernet is: CRC =
Computation structures 24 CRC in hardware The VHDL code for the -bit wide data bus implementation with polynomial crc(0) <= data_in xor crc(4); is shown below: crc() <= crc(0); crc(2) <= data_in xor crc() xor crc(4); crc(3) <= crc(2); crc(4) <= data_in xor crc(3) xor crc(4); Computation structures 25 Data In Q D CRC in hardware Q D Q D Q D Q D P(x) = x 5 + x 5 x 4 x 3 x 2 x x 0 x 4 + x 2 + Load the CRC register with 0xFFFFFFFFFF initially The resulting CRC must be inverted and reflected.
Computation structures 26 Bit Order Byte-order Bit-order Bit-order Highest Byte...... Lowest Byte MSB LSB MSB LSB Preamble Synch DA SA Type Data FCS 62 Bits 2 Bits 6 Bytes 6 Bytes 2 Bytes 46-500 Bytes 4 Bytes Note that the Bit order is reversed compared to the Byte order Computation structures 27 Bit Order example When sending the two Bytes 0x3F0 the following bit order is used. 0 3 F 0 0 0 0 0 0 0 0 0 Tx_d(3) Tx_d(0)
Computation structures 28 Bit Order CRC When sending 0xD0D5 the following bit order is used. Note that the CRC is not sent bytewise. D 0 D 5 0 0 0 0 0 0 0 0 Tx_d(3) Tx_d(0) Computation structures 29 Hubs & Switches & Routers Hubs = Is an extension cord for networks, all signals are sent to all computers on network, all users share the same bandwidth Switches = Each signal is connected to a specific link to a switch. The switch receives the packet looks where it is heading and sends it to the appropriate port Router = Is working on higher level than the Ethernet Protocol, it usually works on IP level and looks at the IP address instead of the Ethernet Address
)( &' '' '& && $ % % $ # " #"!! Computation structures 30 Clip-art Every presentation needs some clip-art Ethernet Switch NIC Computation structures 3 Questions?