Channel FIFO (CFIFO) (v1.00a)

0 Channel FIFO (CFIFO) (v1.00a) DS471 April 24, 2009 0 0 Introduction The Channel FIFO (CFIFO) contains separate write (transmit) and read (receive) FIFO designs called WFIFO and RFIFO, respectively. WFIFO and RFIFO can be used together or separately, and both are built from common functional elements such as special low level counter circuitry and compare functions. A CFIFO is intended to reside within other cores which require a multichannel FIFO capability, such as an HDLC transmitter/receiver. CFIFO does not contain a host bus interface, instead relying on core instantiation to provide the interface. FIFOs utilize Virtex -4 FPGA block RAM elements as data storage medium. A CFIFO design incorporates special purpose counters, state machines, and logic necessary to implement functional requirements of a channelized FIFO. Features Two independent channel FIFO components provided: Read CFIFO (for host bus receive data buffering) and Write CFIFO (for host bus transmit data buffering). User-controlled features include parameters for: - Setting the number of channels. - Setting FIFO data depth. - Setting FIFO data width. - Setting independent fixed length burst sizes for each side of a CFIFO. Setting size to zero removes burst transfer support logic from side and disables bursts for side of CFIFO. - Selecting target FPGA family type. Supported Device Family LogiCORE IP Facts Core Specifics Spartan -3, Spartan-3A, Spartan-3E, Spartan-3A DSP Virtex -4 Version of core channel_fifo v1.00a I/O Resources Used Min Max LUTs 199 345 FFs 61 96 Block RAMs 18 36 Documentation Design File Formats Constraints File Verification Instantiation Template Xilinx Implementation Tools Verification Simulation Synthesis Provided with Core VHDL UCF VHDL test bench VHDL Wrapper Design Tool Requirements ISE v11 Mentor Graphics ModelSim v6.4b and above Mentor Graphics ModelSim v6.4b and above Support Support provided by Xilinx, Inc. XST 2005-2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. DS471 April 24, 2009 www.xilinx.com 1

Features (contd) FIFO-like status outputs on communications interface side of HalfFull, AlmostFull, and Full for Read Channel FIFO, and HalfEmpty, AlmostEmpty, and Empty for Write Channel FIFO, in addition to true Occupancy (Write Channel FIFO) and Vacancy (Read Channel FIFO) outputs. A Tag field input to Write CFIFO is stored in a memory array on every write data transfer. This field is user definable and is intended to provide a mechanism for indicating which byte within a word is the last valid byte in a packet. Write and Read Ports on each CFIFO are synchronized to a common clock source (synchronous operation). Functional Description A Channel FIFO (CFIFO) is used as a data buffering element within an IP core in which multiple channels within a data stream, generated at one rate, must be buffered before being consumed at a later time and possibly at a different rate 1 and/or different order. A typical application might be interfacing a processor bus to a physical communication data stream in which multiple channels coexist. Figure 1 shows a CFIFO containing n channels, where each channel contains m 1 data words, and one status word. To compute m, the FIFO depth is divided by N, where N is the smallest integral power of two greater than or equal to n. This means that if n is not an integral power of two, portions of the FIFO memory will be unused. Each channel includes a status word that contains information about the state of that channel. The state information includes the occupancy count for that channel, and information necessary to allow the CFIFO control logic to perform a context switch when a new channel is selected. In essence, each channel within a CFIFO operates as an independent, m 1 word FIFO selectable via the channel number. Figure 2 shows a hypothetical IP core in which both a write CFIFO (WFIFO) and a read CFIFO (RFIFO) have been instantiated. This hypothetical core incorporates a processor bus interface via the OPB IPIF (On-chip Peripheral Bus Intellectual Property InterFace) module and transmits and receives data to and from its communication data stream. The IP core provides registers for the status information, and address decoding, to allow the host processor to read the status as well as write to the WFIFO and read from the RFIFO. The IP core also provides the clock and reset signals for both CFIFOs. 1. This is not meant to imply different clock frequencies, only that the time required to consume the data my be different than the time required to supply it. For example, the processor may fill a write channel FIFO using fixed length burst transfers on the Bus Interface side, while the Interface side uses single beat transfers to send the data. In this case the rate at which the FIFO is filled is much faster than the rate at which it is emptied. 2 www.xilinx.com DS471 April 24, 2009

Figure Top x-ref 1 channel n - 1 channel 2 data(m - 2) FIFO Depth channel 1 channel 2 channel 0 channel 2 data(2) channel 2 data(1) channel 2 data(0) channel 2 status ds471 1405 Figure 1: CFIFO with n Channels Figure Top x-ref 2 OPB Bus IPCore OPB IPIF Local Bus Interface Logic Valid status data Tag Chnl # Burst WrReq RdReq Ack Chnl # Burst DataReq StatusReq Ack data Valid WFIFO RFIFO discrete status lines data Tag Chnl # Valid Burst Req Ack Chnl # Burst Valid Req Ack data discrete status lines Data Stream unication Interface Logic Data Stream DS471_02_1405 Channel FIFO Overview Channel FIFO Status Calculation Figure 2: WFIFO and RFIFO Instantiation in an IP Core The status calculation in a normal FIFO implementation is based on the relative differences between the write address and the read address. This process is graphically shown in Figure 3. DS471 April 24, 2009 www.xilinx.com 3

Figure Top x-ref 3 Memory Write Address Pointer Difference here determines Full Condition and Occupancy Difference here determines Empty Condition and Occupancy Read Address Pointer Figure 3: FIFO Occupancy / Vacancy Calculation DS471_03_1405 For the channel FIFO the same status calculation is performed on each channel rather than the entire memory array. So for a channel FIFO there are n status calculations, where n is the number of channels.because only the status of the currently active channel is necessary, only that status is provided to the IP core. When a new channel is selected, the previous channel s status must be saved and the new channel s status must be loaded. This context switch requires several clocks before the CFIFO can begin transferring data. The CFIFOs are designed to context switch whenever the channel number changes. A channel number is allowed to change in any clock cycle in which the request (read or write) signals for that side of the CFIFO have been deasserted for at least one clock cycle. The context switch has completed when the channel valid signal is asserted and/or the status read (on the bus side of the CFIFO) has been acknowledged. The new channel s discrete status output bits (on the data stream communications side of the CFIFO) will be valid when the channel valid signal is detected asserted. On the local bus interface side of the IP, a status read request can occur in the same clock cycle that the channel number changes. The acknowledgement for the status request indicates that the context switch to the new channel has completed, the status from the memory array is valid, and that data transfer requests are allowed. At that time a new data transfer can be requested. If it is not desired to read the status to determine when a context switch to a new channel has completed, the channel valid signal can be sampled. The context switch has completed when the channel valid signal is asserted. At that time, a new data transfer can be requested. Once a context switch has completed, the CFIFOs can supply data on each clock cycle of a fixed length burst. The length of a burst can be different for each side and is set by a generic. To minimize the latency introduced by a context switch, the CFIFOs will perform a context switch as soon as possible after detecting a channel number change, as long as no transfer request is asserted. Any additional clock cycles an IP designer can introduce between a channel number change and a status/data transfer request reduces the latency between the request and the acknowledgement. The CFIFOs are designed to be insensitive to pipeline delays associated with request deassertion during burst transfers. The CFIFO will terminate a burst transfer once the correct number of words have been transferred, regardless of how long the request remains asserted after the last acknowledge. The request must be deasserted before a new transfer can begin. Also large burst sizes on one side of the CFIFO can significantly increase the time required for a context switch on the other side. 4 www.xilinx.com DS471 April 24, 2009

Channel FIFO Parameters Parameter List The CFIFO design supports user configurability via a set of design parameters implemented as VHDL input Generics. The generics for the RFIFO are listed in Table 1 and for the WFIFO in Table 2. It is important to note the ID Number Column. This ID will be used interchangeably with the Parameter name in this document. Table 1: RFIFO Parameter List. Read Generic Feature / Description Parameter Name Allowable Values FIFO Memory Sizing Default Value VHDL Type RG1 Number of channels in the CFIFO C_NUM_ CHANNELS 1 to 256 32 Positive RG2 Total number of words contained in the CFIFO C_TOTAL_DEPTH Virtex: 4 to 4096 16384 Positive RG3 FIFO word data width in bits C_DWIDTH 32 to 256 (1) 32 Positive Feature Selection RG4 Bus side fixed length burst size C_BUS_BURST_ SIZE 0 to 256 0 or 1 indicates that bursts are disabled for the bus side. 8 Natural RG5 side fixed length burst size C_COMM_BURST _SIZE 0 to 256 0 or 1 indicates that bursts are disabled for the comm side. 8 Natural Target FPGA Family Selection RG6 User Target FPGA Family selection C_FAMILY virtex: Use Virtex block RAM memory core String Notes: 1. This parameter would normally be sized to match the width of the host processor bus (that is, 32, 64, 128, etc.). The width of the FIFO memory array will be C_DWIDTH +(C_DWIDTH / 8) to allow a tag to be associated with each word of data and to provide storage for FIFO status information. DS471 April 24, 2009 www.xilinx.com 5

Table 2: WFIFO Parameter List Write Generic Feature / Description Parameter Name Allowable Values Default Value VHDL Type FIFO Memory Sizing WG1 WG2 WG3 Number of channels in the CFIFO Total number of words contained in the CFIFO FIFO word data width in bits C_NUM_CHANNELS 1 to 256 32 Positive C_TOTAL_DEPTH Virtex: 4 to 4096 16384 Positive C_DWIDTH 32 to 256 (1) 32 Positive Feature Selection 0 to 256 WG4 Bus side fixed length burst size C_BUS_BURST_ SIZE 0 or 1 indicates that bursts are disabled on the bus side. 8 Natural 0 to 256 WG5 side fixed length burst size C_COMM_BURST_ SIZE 0 or 1 indicates that bursts are disabled on the comm side. 8 Natural WG6 User Target FPGA Family selection Target FPGA Family Selection C_FAMILY virtex: Use Virtex block RAM memory core String Notes: 1. This parameter would normally be sized to match the width of the host processor bus (that is, 32, 64, 128, etc.). The width of the FIFO memory array will be C_DWIDTH +(C_DWIDTH / 8) to allow a tag to be associated with each word of data and to provide storage for FIFO status information. 6 www.xilinx.com DS471 April 24, 2009

Allowable Parameter Combinations There are several interdependencies of CFIFO parameter settings. These are captured in Table 3. Table 3: Parameter Dependencies Dependent Parameter Name / Number Impacting Parameter Name/ Number Dependency Description C_TOTAL_DEPTH RG2 C_FAMILY RG6 C_TOTAL_DEPTH WG2 C_FAMILY WG6 If RG6 is SPARTAN3 1, then RG2 can have a value in the range of 4 to 16384 words. If RG6 is any other string, then RG2 can only have a value in the range of 4 to 4096 words. If WG6 is SPARTAN3 1, then WG2 can have a value in the range of 4 to 16384 words. If WG6 is any other string, then WG2 can only have a value in the range of 4 to 4096 words. 1. The constant SPARTAN3 is provided in the family package (family.vhd) as part of the proc_common library (all versions). This constant, along with constant definitions for all other currently available family types, are defined as strings and provide a standard way for users to specify family types. These constants, plus the function equalignorecase, are used by the CFIFOs to select the appropriate block RAMs for the FIFO memory. Other Parameter Considerations 1. The FIFO memory array will always be (C_DWIDTH / 8) bits wider than C_DWIDTH (RG3,WG3) to provide storage for the channel status information and to accommodate storing the tag input with each data word in the WFIFO. 2. The port widths for the channel number and occupancy/vacancy have upper bounds which are derived from functions that calculate the width based on RG1 (for the RFIFO channel number width) and WG1 (for the WFIFO channel number width), and RG1, RG2, and RG3 (for the RFIFO occupancy width) and WG1, WG2, and WG3 (for the WFIFO vacancy width), respectively. The user is encouraged to use the functions provided in a VHDL package called channel_fifo_pkg (channel_fifo_pkg.vhd) included with the CFIFO designs. Functions are provided in this package for computing the bit width of the channel number and the vacancy/occupancy signals. These same functions are used in the CFIFO designs. Channel FIFO Package Helper Functions Channel Number Width Function get_chnl_width(num_channels: positive) return positive; The get_chnl_width function requires a positive integer containing the number of channels in the CFIFO as its only argument and returns a positive integer that contains the bit width for a signal that can represent all the channel numbers from zero to one minus the number of channels. DS471 April 24, 2009 www.xilinx.com 7

Vacancy/Occupancy Width Function get_occ_width(num_channels, total_num_bytes, data_bus_width: positive) return positive; get_vac_width(num_channels, total_num_bytes, data_bus_width: positive) return positive; The get_occ_width and get_vac_width functions require three positive integer arguments. The first argument contains the number of channels in the CFIFO and the second argument contains the total number of words in the CFIFO memory array. The third argument contains the width of the CFIFO data buses (typically C_DWIDTH). They return a positive integer that specifies the width of a signal containing all allowable occupancy/vacancy values for a single channel in the CFIFO. Read CFIFO Functional Description RFIFO Block Diagram The main requirement of the Read Channel FIFO is to provide a receive data buffer function between the data stream communication logic and the local bus interface logic in an IP core. The Block Diagram for the Read CFIFO is shown in Figure 4. The data input (write) interface is connected to the data stream communication side and the data output (read) interface is connected to the local bus interface side. The module design is centered around Dual Port Block Memory core (block RAMs) memory elements. Access to the memory core is facilitated by the Memory Read/Write Controller block. This block is composed of three major functions: Write Control, Read Control, and the Occupancy/Vacancy calculation. The input (write) side of the RFIFO is controlled by the Write Control Logic which includes such things as a write address counter and the memory write controls. The Read Control Logic block provides the timing and signal interface between the memory core read port and the local bus Interface of the IP. The Occupancy/Vacancy Calculation Block is tasked with the continuous update of the HalfFull, AlmostFull, Full, and the Vacancy discrete status outputs for the currently active channel. Figure Top x-ref 4 2RFIFO_DBus DinA DoutB RRFIFO_DBus AddrA Wr_enA BRAM Based Dual Port AddrB Rd_enB 2RFIFO_Ch_Num 2RFIFO_Burst RFIFO2_Ch_Valid 2RFIFO_WrReq RFIFO2_Ack RFIFO2_ErrAck RFIFO2_HalfFull RFIFO2_AlmostFull RFIFO2_Full RFIFO2_Vacancy Write Control Logic Read CFIFO Memory Read/Write Controller Occupancy and Vacancy Read Control Logic Bus2RFIFO_Ch_Num Bus2RFIFO_Burst Bus2RFIFO_Data_RdReq Bus2RFIFO_Status_RdReq RFIFO2Bus_Ack RFIFO2Bus_ErrAck RFIFO2Bus_Ch_Valid DS471_04_1405 Figure 4: Read Channel FIFO Block Diagram 8 www.xilinx.com DS471 April 24, 2009

In the case of the Read CFIFO, the HalfFull, AlmostFull, Full, and Vacancy outputs are provided to the data stream communication interface side of the IP. The Ch_Num signals select which channel should be the active channel for each side, respectively. Ch_Valid indicates that the selected channel is now the active channel and that the discrete status signals for the selected channel are valid. The Req signal indicates a request by the interface logic to perform a data transfer with the RFIFO. The Ack signals indicate the completion of the requested transfer. The ErrAck signals indicate an error condition has occurred. RFIFO Channel Status When the Bus Interface issues a status read request by asserting Bus2RFIFO_, the status bits returned are as shown in Figure 5. The status flags (Empty, AlmostEmpty, and HalfEmpty) are contained in the three most significant bits and the occupancy count is right justified in bits 3 to 31. If the data bus width (C_DWIDTH) is greater than 32, the status information will always be contained in the most significant 32 bits (bit locations 0 to 31). Figure Top x-ref 5 AlmostEmpty 0 1 2 3 4 31 Empty HalfEmpty Vacancy Figure 5: RFIFO Channel Status Register DS471_05_1405 Interface Pipeline Delays Because the RFIFO is designed to be incorporated into another, higher level design, the problem of pipeline delays associated with the request/acknowledge response has been addressed by separating transfers into single beat and fixed length burst transfers. In a design that relies on pipelining to achieve higher clock speeds, the latency introduced between the acknowledge and when the request signal is deasserted can be several clock cycles. To accommodate this latency, the RFIFO uses the state of the burst input (Bus2RFIFO_ or 2RFIFO_) when the data transfer request asserts, to distinguish between single beat and burst transfers. During status read requests on the bus side, the channel status will be placed on RFIFO2Bus_ for each clock cycle that Bus2RFIFO_ remains asserted, and the request will also be acknowledged on each clock cycle. Assume for the remainder of this discussion that the selected channel is not empty (bus side) or full (comm side) when the data transfer request asserts, and that it does not become empty (or full) before the end of a burst transfer. If the burst input is in the deasserted state at the time the data transfer request is asserted, a single data transfer will occur, regardless of how long the request remains asserted after the acknowledge signal (RFIFO2Bus_Ack or RFIFO2_) is asserted. Figure 6 and Figure 7 show a status read and a single beat data transfer for a read and a write, respectively, when there is a two clock delay between the acknowledge and the deassertion of the request signal. DS471 April 24, 2009 www.xilinx.com 9

Figure Top x-ref 6 Clk Rst Bus2RFIFO_Ch_Num[0:7] Bus2RFIFO_Status_RdReq Bus2RFIFO_Burst Bus2RFIFO_Data_RdReq RFIFO2Bus_Ack RFIFO2Bus_ErrAck RFIFO2Bus_Ch_Valid RFIFO2Bus_DBus[0:31] 2RFIFO_Ch_Num[0:7] RFIFO2_Ch_Valid 2RFIFO_Burst 2RFIFO_WrReq RFIFO2_Ack RFIFO2_ErrAck 2RFIFO_DBus[0:31] RFIFO2_HalfFull RFIFO2_AlmostFull RFIFO2_Full RFIFO2_Vacancy[0:7] Cycle 2005 234567 2004 FA 1 2 3 4 5 6 7 8 9 10 11 12 FB DS471_06_1405 Figure 6: RFIFO Single Beat Read Timing With ACK Delay 10 www.xilinx.com DS471 April 24, 2009

Figure Top x-ref 7 Clk Rst Bus2RFIFO_Ch_Num[0:7] Bus2RFIFO_Status_RdReq Bus2RFIFO_Burst Bus2RFIFO_Data_RdReq RFIFO2Bus_Ack RFIFO2Bus_ErrAck RFIFO2Bus_Ch_Valid RFIFO2Bus_DBus[0:31] 2RFIFO_Ch_Num[0:7] E000 60 RFIFO2_Ch_Valid 2RFIFO_Burst 2RFIFO_WrReq RFIFO2_Ack RFIFO2_ErrAck 2RFIFO_DBus[0:31] 234567 RFIFO2_HalfFull RFIFO2_AlmostFull RFIFO2_Full RFIFO2_Vacancy[0:7] FF FE Cycle 1 2 3 4 5 DS471_07_1405 Figure 7: RFIFO Single Beat Write Timing with ACK Delay If fixed length bursts are enabled (C_BUS_BURST_ SIZE or C_COMM_BURST_SIZE are greater than one), then, if the burst input (Bus2RFIFO_ or 2RFIFO_) is asserted when the request asserts, the RFIFO will perform a fixed length burst transfer, transferring data on each clock cycle, until the number of words specified for the burst size have been transferred. The acknowledge (RFIFO2Bus_Ack or RFIFO2_) will deassert after the last word and the RFIFO will wait for the request to deassert before accepting another transfer request. Figure 8 and Figure 9 show the timing for a status read request followed by a fixed length burst transfer of four words for a read and a write, respectively, with a two clock delay between the acknowledge and the request deassertion. DS471 April 24, 2009 www.xilinx.com 11

Figure Top x-ref 8 Clk Rst Bus2RFIFO_Ch_Num[0:7] Bus2RFIFO_Status_RdReq Bus2RFIFO_Burst Bus2RFIFO_Data_RdReq RFIFO2Bus_Ack RFIFO2Bus_ErrAck RFIFO2Bus_Ch_Valid RFIFO2Bus_DBus[0:31] 2004 89AB CDEF 1122 3344 5566 7788 9900 E 2RFIFO_Ch_Num[0:7] RFIFO2_Ch_Valid 2RFIFO_Burst 2RFIFO_WrReq RFIFO2_Ack RFIFO2_ErrAck 2RFIFO_DBus[0:31] RFIFO2_HalfFull RFIFO2_AlmostFull RFIFO2_Full RFIFO2_Vacancy[0:7] Cycle FB FC FD FE FF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DS471_08_1405 Figure 8: RFIFO Fixed Length Burst Read Timing With ACK Delay 12 www.xilinx.com DS471 April 24, 2009

Figure Top x-ref 9 Clk Rst Bus2RFIFO_Ch_Num[0:7] Bus2RFIFO_Status_RdReq Bus2RFIFO_Burst Bus2RFIFO_Data_RdReq RFIFO2Bus_Ack RFIFO2Bus_ErrAck RFIFO2Bus_Ch_Valid RFIFO2Bus_DBus[0:31] E000 6000 00 2000 0004 2RFIFO_Ch_Num[0:7] RFIFO2_Ch_Valid 2RFIFO_Burst 2RFIFO_WrReq RFIFO2_Ack RFIFO2_ErrAck 2RFIFO_DBus[0:31] 89AB CDEF 1122 3344 5566 7788 9900 RFIFO2_HalfFull RFIFO2_AlmostFull RFIFO2_Full RFIFO2_Vacancy[0:7] Cycle FF FE FD FC FB 1 2 3 4 5 6 7 8 9 10 DS471_09_1405 Figure 9: RFIFO Fixed Length Burst WriteTiming With ACK Delay RFIFO Write Interface Operational Description Data received from the data stream is transferred from the communications interface logic to the local bus interface logic via the Read Channel FIFO (RFIFO). The input (write port) of the RFIFO is connected to the data stream communications side of the IP ( Interface). During a data receive operation, the Interface specifies a channel number (2RFIFO_) to the RFIFO and determines that the channel is valid (RFIFO2_ is asserted). The interface ensures there is room left in the RFIFO (RFIFO2_ is not asserted) and then loads data into the write port of the RFIFO. The write to the RFIFO is initiated by asserting the 2RFIFO_ signal. If C_COMM_BURST_SIZE is greater than one, then as long as the write request signal is asserted (and the currently active channel in the RFIFO is not full, and the number of words transferred is less than C_COMM_BURST_SIZE), the Interface can load data words into the CFIFO at each rising edge of the clock signal. If the channel becomes full during a burst transfer, the RFIFO will not accept any new write requests and will indicate this by asserting RFIFO2_ while the write request is asserted. Once C_COMM_BURST_SIZE words have been written to the RFIFO it will stop responding to the write request until 2RFIFO_ is deasserted. DS471 April 24, 2009 www.xilinx.com 13

A transfer acknowledge (RFIFO2_) to the Interface is generated by the RFIFO indicating that the requested write operation will complete on the next rising edge of the clock signal. When the currently active channel in the RFIFO becomes full (indicated by RFIFO2_ asserted), any further write requests will be ignored and an error acknowledge (RFIFO2_) will be asserted. Further attempts to write to that channel will produce error acknowledgements until one or more read transfers have occurred from the read side. In addition to the full flag, there are two other status flags (RFIFO2_ and RFIFO2_) as well as a vacancy count (RFIFO2_) that the Interface can monitor. These status flags are only valid while RFIFO2_ is asserted. unications Interface Write Operation Example For this example assume both the Bus Interface and the Interface have channel one selected and the most recent context switch on either side has completed and both channel numbers are stable. The channel number is eight bits in width, reflecting the fact that there are 256 channels numbered from 0 to 255, and the discrete vacancy output on the communications side is also eight bits in width, indicating each channel can hold 255 (m 1) words. We will also assume that C_COMM_BURST_SIZE is set to 4 (fixed length bursts of four words) and that no data transfers occur on the Bus Interface side during this discussion. Also, for clarity, we will assume there are no pipeline delays associated with the request/acknowledge logic. Figure Top x-ref 10 Clk Rst Bus2RFIFO_Ch_Num[0:7] Bus2RFIFO_Status_RdReq Bus2RFIFO_Burst Bus2RFIFO_Data_RdReq RFIFO2Bus_Ack RFIFO2Bus_ErrAck RFIFO2Bus_Ch_Valid RFIFO2Bus_DBus[0:31] 2RFIFO_Ch_Num[0:7] RFIFO2_Ch_Valid 2RFIFO_Burst 2RFIFO_WrReq RFIFO2_Ack RFIFO2_ErrAck 2RFIFO_DBus[0:31] RFIFO2_HalfFull RFIFO2_AlmostFull RFIFO2_Full RFIFO2_Vacancy[0:7] Cycle E000 23 4567 89AB CDEF 1122 3344 5566 7788 0004 9900 0005 FF FE FD FC FB FA 1 2 3 4 5 6 7 8 9 10 DS471_10_1405 Figure 10: RFIFO Write Timing 14 www.xilinx.com DS471 April 24, 2009

Figure Top x-ref 11 Clk Rst Bus2RFIFO_Ch_Num[0:7] Bus2RFIFO_Status_RdReq Bus2RFIFO_Burst Bus2RFIFO_Data_RdReq RFIFO2Bus_Ack RFIFO2Bus_ErrAck RFIFO2Bus_Ch_Valid RFIFO2Bus_DBus[0:31] 00FA 00FE 0 00FF 2RFIFO_Ch_Num[0:7] RFIFO2_Ch_Valid 2RFIFO_Burst 2RFIFO_WrReq RFIFO2_Ack RFIFO2_ErrAck 2RFIFO_DBus[0:31] 1111 1111 2222 2222 3333 3333 4444 4444 5555 5555 RFIFO2_HalfFull RFIFO2_AlmostFull RFIFO2_Full RFIFO2_Vacancy[0:7] Cycle 05 04 03 02 00 1 2 3 4 5 6 7 8 9 DS471_11_1405 Figure 11: RFIFO Write Timing to Fill the FIFO Referring to Figure 10, the Bus Interface issues a status read request in the second clock cycle and the RFIFO responds in the same clock cycle with an acknowledgement and the status because there is no context switch taking place. The status value returned is hexadecimal E000, indicating that the channel is empty (and at least almost empty, and at least half empty), corresponding to the occupancy count of 0 which indicates that there is no data in the channel. Because the Interface has access to discrete status information, there is no status read request on this side. The assertion of RFIFO2_ indicates that the channel is ready and the discrete status outputs are stable. Because the channel is not full, the Interface places the data it wishes to write on the data bus and asserts the data write request in clock cycle two. The RFIFO responds with an acknowledge in cycle two, indicating that the data will be written at the end of that cycle. Because the burst signal was deasserted at the time the write request asserted, this is a single beat transfer. In cycle five, the Interface asserts the data write request with the burst signal asserted and bursts four data words to the RFIFO. The RFIFO acknowledges the write request on the each clock cycle, until four words have been written. This is a fixed length burst, and that the RFIFO will terminate the burst by deasserting RFIFO2_ after the fourth data transfer is complete, even if 2RFIFO_ remains asserted. DS471 April 24, 2009 www.xilinx.com 15

In cycle eight, the Bus Interface again asserts the status read request and the RFIFO responds with an ack and the status value of hexadecimal 0004, indicating that there are four words of data in the channel. The Bus Interface keeps its status read request asserted in clock cycle 9 and the RFIFO provides the status and the acknowledge signal in the same cycle. The status value contains hexadecimal 0005, indicating that there are five valid words of data in the channel. The discrete vacancy output on the Interface side (RFIFO2_) reflects this same condition, namely that there are 250 vacant locations in the channel. Figure 11 shows a similar operation of the Interface writing to the RFIFO, but it depicts the condition when the RFIFO becomes full. The discrete RFIFO2_ is asserted, RFIFO2_ asserts when the RFIFO2_ is one, and RFIFO2_ asserts when RFIFO2_ is zero. Also the status values read by the Bus Interface reflect the that the FIFO has an occupancy of 254 and 255 words, respectively. RFIFO Read Interface Operational Description The read port of the RFIFO is connected to the local bus interface (Bus Interface). The Bus Interface selects the active read channel by providing a channel number on Bus2RFIFO_Ch_Num. The read port is activated by the assertion of Bus2RFIFO_ or Bus2RFIFO_Data_RdReq. If a read status transfer is being requested, the RFIFO will complete a context switch if necessary, and place the channel status word on the data bus and assert RFIFO2Bus_Ack. In the case of a read data transfer, if data exists in the channel buffer (the Empty bit in the status word is zero), and any context switch has completed, the RFIFO will place the data on the data bus (RFIFO2Bus_) and assert RFIFO2Bus_Ack. If a read data request to an empty channel is detected by the RFIFO, RFIFO2Bus_ will be asserted and the state of that channel will not change. Figure 5 shows the locations of the status bits in the channel status word for the RFIFO. Bus Interface Read Operation Example For this example assume both the Bus Interface and the Interface have channel one selected and the most recent context switch on either side has completed and both channel numbers are stable. The channel number is eight bits in width, reflecting the fact that there are 256 channels numbered 0 to 255, and the discrete vacancy output on the side is also eight bits wide, indicating that each channel can hold 255 (m 1) words. We will also assume that no transfers occur on the Interface side, and, for clarity, during this discussion we will assume there are no pipeline delays associated with the request/acknowledge logic. 16 www.xilinx.com DS471 April 24, 2009

Figure Top x-ref 12 Clk Rst Bus2RFIFO_Ch_Num[0:7] Bus2RFIFO_Status_RdReq Bus2RFIFO_Burst Bus2RFIFO_Data_RdReq RFIFO2Bus_Ack RFIFO2Bus_ErrAck RFIFO2Bus_Ch_Valid RFIFO2Bus_DBus[0:31] 2000 0005 23 4567 2000 0004 89AB CDEF 1122 3344 5566 7788 9900 E000 2RFIFO_Ch_Num[0:7] RFIFO2_Ch_Valid 2RFIFO_Burst 2RFIFO_WrReq RFIFO2_Ack RFIFO2_ErrAck 2RFIFO_DBus[0:31] RFIFO2_HalfFull RFIFO2_AlmostFull RFIFO2_Full RFIFO2_Vacancy[0:7] Cycle FA FB FC FD FE FF 1 2 3 4 5 6 7 8 9 10 11 12 13 DS471_12_1405 Figure 12: RFIFO Read Timing See Figure 12 during the discussion of this example. The Bus Interface issues a status read request in the second clock cycle and the RFIFO responds in the same clock cycle with an acknowledgement and the status because there is no context switch taking place. The status value returned is hexadecimal 0005, indicating an occupancy count of 5 words with none of the status flags asserted. Because the RFIFO is not empty, the Bus Interface issues a read request in clock cycle three and the RFIFO responds with the data and an acknowledge in clock cycle four. The discrete vacancy output also changes in cycle four to indicate that there is one additional vacant location in the channel. Because the read request asserted when the burst signal was deasserted, this is a single beat transfer. In cycle six, the Bus Interface again asserts the status read request and the RFIFO responds with an ack and the status value of hexadecimal 0004, indicating that there are four words of data in the channel. The empty flag is still deasserted so the Bus Interface issues another read request in cycle seven, this time with the burst signal asserted, and in cycle eight the RFIFO acknowledges with the next data word. Because the RFIFO is capable of providing data on each clock cycle for fixed length bursts, the Bus Interface leaves its read request asserted, bursting the data from the RFIFO. In cycle twelve, the Bus Interface again asserts the status read request and the RFIFO responds with an ack and the status value of hexadecimal E000, indicating that all Empty flags are asserted and there is no data in the RFIFO. DS471 April 24, 2009 www.xilinx.com 17

RFIFO Channel Number Context Switch Operational Description When either of the channel number inputs to the RFIFO change, an internal context switch occurs in which the status and state of the previous channel are saved, and the status and state of the new channel must be retrieved, loaded, and output to the appropriate port. This context switch takes several clock cycles to complete. During a context switch initiated by a channel number change on the communications side, the discrete status outputs emitted by the RFIFO on the communications side become invalid as the previous channel s status is replaced by the new channel s status. The channel valid signal (RFIFO2_) indicates when the context switch has completed and that the new discrete status outputs are valid. The channel valid signal also indicates that data transfers can take place on that channel. An example of a context switch on the Interface is shown in Figure 13. After the Interface completes a write on channel 1, it then changes 2RFIFO_ to channel 2 in clock cycle five. Note that 2RFIFO_ is deasserted in cycle four and then reasserts in cycle 6 (it could have reasserted in cycle 5, but it must be deasserted in cycle 4). RFIFO2_ negates indicating that the discrete outputs are currently not valid. It asserts three clocks later, indicating that the context switch is complete. The RFIFO asserts RFIFO2_ in the same cycle, indicating that the write transaction has completed. Figure Top x-ref 13 Clk Rst Bus2RFIFO_Ch_Num[0:7] Bus2RFIFO_Status_RdReq Bus2RFIFO_Burst Bus2RFIFO_Data_RdReq RFIFO2Bus_Ack RFIFO2Bus_ErrAck RFIFO2Bus_Ch_Valid RFIFO2Bus_DBus[0:31] 2RFIFO_Ch_Num[0:7] RFIFO2_Ch_Valid 2RFIFO_Burst 2RFIFO_WrReq RFIFO2_Ack RFIFO2_ErrAck 2RFIFO_DBus[0:31] RFIFO2_HalfFull RFIFO2_AlmostFull RFIFO2_Full RFIFO2_Vacancy[0:7] 6000 00 02 23 4567 89AB CDEF 1122 3344 5566 7788 FF FE FE FD FC FB 9900 DS471_13_1405 Figure 13: Interface Context Switch 18 www.xilinx.com DS471 April 24, 2009

Because 2RFIFO_ was asserted for this request, the additional 3 data words are written to channel 2 of the RFIFO. On the local bus side, a context switch will typically delay the assertion of the acknowledge signal for the first read data transfer. However, if the first read transfer is a status read then the status will be available in two clock cycles following the request. An example of a context switch on the Bus Interface is shown in Figure 14. In this example, the Bus Interface completes its activity on channel 1 and then switches to channel 2. RFIFO2Bus_ negates as the context switch begins. Bus2RFIFO_ is asserted to obtain the status of channel 2 and the context switch occurs. RFIFO2Bus_ asserts 3 clocks later and the status is returned, due to the context switching. Because the status of hex 000A indicates that there is data in the RFIFO, the Bus Interface asserts Bus2RFIFO_ and Bus2RFIFO_Data_RdReq and performs a burst read of 4 words. Because the context switch occurred during the status read, the first data word of the burst is returned one clock after the read request and all subsequent words are returned each clock cycle thereafter. When the Bus Interface has concluded its read burst, it then reads the status of the channel. Figure Top x-ref 14 Clk Rst Bus2RFIFO_Ch_Num[0:7] 02 Bus2RFIFO_Status_RdReq Bus2RFIFO_Burst Bus2RFIFO_Data_RdReq RFIFO2Bus_Ack RFIFO2Bus_ErrAck RFIFO2Bus_Ch_Valid RFIFO2Bus_DBus[0:31] 0005 000A 89AB CDEF 1122 3344 5566 7788 9900 0006 2RFIFO_Ch_Num[0:7] RFIFO2_Ch_Valid 2RFIFO_Burst 2RFIFO_WrReq RFIFO2_Ack RFIFO2_ErrAck 2RFIFO_DBus[0:31] RFIFO2_HalfFull RFIFO2_AlmostFull RFIFO2_Full RFIFO2_Vacancy[0:7] FA DS471_14_1405 Figure 14: Bus Interface Context Switch DS471 April 24, 2009 www.xilinx.com 19

Read CFIFO Signal Interface I/O Signal Summary Table 4 defines the Read CFIFO I/O signal set implementation. Some ports are variable width based upon input parameter settings. The Parameter dependent widths are specified using the Parameter Number indicated in Table 1 on page 5. Table 4: Read Channel FIFO Interface Signals Read Port Signal Name Width Interface I/O Signal Description System RP1 Clk Bus I Input Synchronization clock from the IP RP2 Rst Bus I Active high master reset signal from the IP Local Bus Interface RP3 Bus2RFIFO_Ch_ Num (0:get_chnl_wid th(rg1)-1) Bus I Indicates which channel should be active for read transactions. RP4 Bus2RFIFO_ Burst Bus I Indicates that a data read request is for a fixed length burst. RP5 Bus2RFIFO_Data _RdReq Bus I This active high input signals the RFIFO that the local bus interface is requesting a read data transfer from the active channel. (1) RP6 Bus2RFIFO_ Status_RdReq Bus I This active high input signals the RFIFO that the local bus interface is requesting a read status transfer from the active channel. (1) RP7 RFIFO2Bus_Ack Bus O When asserted, this active high output indicates that the requested data or status transfer will be performed on the next rising edge of the Clk. RP8 RFIFO2Bus_ ErrAck Bus O When asserted, this active high output indicates that a read data transfer was attempted from an empty channel. RP9 RFIFO2Bus_ DBus (0:RG3-1) Bus O The output data bus. Data is valid only when RP7 is asserted. RP10 RFIFO2Bus_ Ch_Valid Bus1 O When asserted, this active high output indicates that the bus channel is now valid and data transfers can be performed. Interface RP11 2RFIFO_ Ch_Num (0:get_chnl_wid th(rg1)-1) I Indicates which channel should be active for write transactions. RP12 2RFIFO_ Burst I Indicates that a data write request is for a fixed length burst. 20 www.xilinx.com DS471 April 24, 2009

Table 4: Read Channel FIFO Interface Signals (Contd) Read Port Signal Name Width Interface I/O Signal Description RP13 RFIFO2_ Ch_Valid O When asserted, this active high output indicates that status for the active channel is valid. RP14 2RFIFO_ WrReq I This active high input signals the RFIFO that the comm interface is requesting a write data transfer to the active channel. (1) RP15 RFIFO2_ Ack O When asserted, this active high output indicates that the requested data transfer will be performed on the next rising edge of the Clk. RP16 RFIFO2_ ErrAck O When asserted, this active high output indicates that the interface attempted to write to a full channel. RP17 2RFIFO_ DBus (0:RG3-1) I The input data bus. Data is written to memory on each rising Clk while RP15 is asserted. RP18 RFIFO2_ HalfFull O When asserted, this active high output indicates that half of the locations in the active channel are occupied. RP19 RFIFO2_ AlmostFull O When asserted, this active high output indicates that only one empty location remains in the active channel. RP20 RFIFO2_ Full O When asserted, this active high output indicates that the active channel is full. RP21 RFIFO2_ Vacancy Write Channel FIFO Functional Description WFIFO Block Diagram (0:get_vac_widt h(rg1,rg2,rg 3)-1) Notes: 1. Read or write transfer aborts are not supported in the CFIFO. The Block Diagram for the Write CFIFO is shown in Figure 15. The module design is very similar to that of the Read CFIFO. However, the sense of the data transfer is in the opposite direction to that of the Read CFIFO. Also, the WFIFO contains an additional tag field for use in marking the end of data within a channel data word. The Read Control Logic provides the interface between the data stream communications interface in the IP and the read side of the FIFO. The Write Control Logic interfaces with the local bus interface in the IP. The Occupancy/Vacancy Calculation Block is similar to the same function in the RFIFO except that the HalfEmpty, AlmostEmpty, Empty, and Occupancy discrete outputs are provided to the communications interface of the IP. O Indicates the number of empty locations remaining in the active channel. DS471 April 24, 2009 www.xilinx.com 21

Figure Top x-ref 15 Bus2WFIFO_DBus Bus2WFIFO_Tag WFIFO2Bus_Status DinA DoutA AddrA Wr_enA BRAM Based Dual Port DoutB AddrB Rd_enB 2WFIFO_DBus 2WFIFO_Tag Bus2WFIFO_Ch_Num Bus2WFIFO_Burst Bus2WFIFO_Data_WrReq WFIFO2Bus_Status_RdReq WFIFO2Bus_Ack WFIFO2Bus_ErrAck WFIFO2Bus_Ch_Valid Write Control Logic Write CFIFO Memory Read/Write Controller Occupancy and Vacancy Read Control Logic 2WFIFO_Ch_Num 2WFIFO_Burst WFIFO2_Ch_Valid 2WFIFO_RdReq WFIFO2_Ack WFIFO2_ErrAck WFIFO2_HalfEmpty WFIFO2_AlmostEmpty WFIFO2_Empty WFIFO2_Occupancy DS471_15_1405 WFIFO Channel Status Figure 15: Write Channel FIFO Block Diagram When the Bus Interface issues a status read request by asserting Bus2WFIFO_ Status_RdReq, the status bits returned are as shown in Figure 16. The status flags (Full, AlmostFull, HalfFull, and Empty) are contained in the four most significant bits and the vacancy count is right justified in bits 4 to 31. If the data bus width (C_DWIDTH) is greater than 32, the status information will always be contained in the most significant 32 bits (bit locations 0 to 31). Figure Top x-ref 16 Empty AlmostFull 0 1 2 3 4 31 Full HalfFull Vacancy DS471_161405 Figure 16: WFIFO Channel Status Interface Pipeline Delays Because the WFIFO is designed to be incorporated into another, higher level design, the problem of pipeline delays associated with the request/acknowledge response has been addressed by separating transfers into single beat and fixed length burst transfers. In a design that relies on pipelining to achieve higher clock speeds, the latency introduced between the acknowledge and when the request signal is deasserted can be several clock cycles. 22 www.xilinx.com DS471 April 24, 2009

To accommodate this latency, the WFIFO uses the state of the burst input (Bus2WFIFO_Burst or 2WFIFO_ Burst) when the data transfer request asserts, to distinguish between single beat and burst transfers. During status read requests on the bus side, the channel status will be placed on WFIFO2Bus_ Status for each clock cycle that Bus2WFIFO_ Status_RdReq remains asserted, and the request will also be acknowledged on each clock cycle. Assume for the remainder of this discussion that the selected channel is not full (bus side) or empty (comm side) when the data transfer request asserts and that it does not become full (or empty) before the end of a burst transfer. If the state of the burst input is deasserted at the time the data transfer request is asserted, a single data transfer will occur, regardless of how long the request remains asserted after the acknowledge signal (WFIFO2Bus_Ack or WFIFO2_ Ack) is asserted. Figure 17 and Figure 18 show a status read and a single beat data transfer for a write and a read, respectively, when there is a two clock delay between the acknowledge and the deassertion of the request signal. Figure Top x-ref 17 Clk Rst Bus2WFIFO_Ch_Num[0:7] Bus2WFIFO_Burst Bus2WFIFO_Status_RdReq Bus2WFIFO_Data_WrReq WFIFO2Bus_Ack WFIFO2Bus_Ch_Valid WFIFO2Bus_ErrAck Bus2WFIFO_DBus[0:31] Bus2WFIFO_Tag[0:3] WFIFO2Bus_Status[0:31] 2WFIFO_Ch_Num[0:7] WFIFO2_Ch_Valid 2WFIFO_Burst 2WFIFO_RdReq WFIFO2_Ack WFIFO2_ErrAck WFIFO2_DBus[0:31] WFIFO2_Tag[0:3] WFIFO2_HalfEmpty WFIFO2_AlmostEmpty WFIFO2_Empty WFIFO2_Occupancy[0:7] 2000 0005 FA 23 4567 0 FB 2000 0004 cycle 1 2 3 4 5 6 7 8 9 10 11 DS471_17_1405 Figure 17: WFIFO Single Beat Write Timing With ACK Delay DS471 April 24, 2009 www.xilinx.com 23

Figure Top x-ref 18 Clk Rst Bus2WFIFO_Ch_Num[0:7] Bus2WFIFO_Burst Bus2WFIFO_Data_WrReq Bus2WFIFO_Status_RdReq WFIFO2Bus_Ack WFIFO2Bus_ErrAck WFIFO2Bus_Ch_Valid Bus2WFIFO_DBus[0:31] Bus2WFIFO_Tag[0:3] WFIFO2Bus_Status[0:31] 2WFIFO_Ch_Num[0:7] WFIFO2_Ch_Valid 2WFIFO_Burst 2WFIFO_RdReq WFIFO2_Ack WFIFO2_ErrAck WFIFO2_DBus[0:31] WFIFO2_Tag[0:3] WFIFO2_HalfEmpty WFIFO2_AlmostEmpty WFIFO2_Empty WFIFO2_Occupancy[0:7] cycle 23 4567 89AB CDEF 1122 3344 5566 7788 9900 0 0 0 0 8 00FF 05 04 03 02 00 1 2 3 4 5 6 7 8 9 10 11 12 13 DS471_18_1405 Figure 18: WFIFO Single Beat Read Timing With ACK Delay If fixed length bursts are enabled (C_BUS_BURST_ SIZE or C_COMM_BURST_ SIZE are greater than one), then, if the burst input (Bus2WFIFO_Burst or 2WFIFO_ Burst) is asserted when the request asserts, the WFIFO will perform a fixed length burst transfer, transferring data on each clock cycle, until the number of words specified for the burst size have been transferred. The acknowledge (WFIFO2Bus_Ack or WFIFO2_ Ack) will deassert after the last word and the WFIFO will wait for the request to deassert before accepting another transfer request. Figure 19 and Figure 20 show the timing for a status read request followed by a fixed length burst transfer of four words for a write and a read, respectively, with a two clock delay between the acknowledge and the request deassertion. 24 www.xilinx.com DS471 April 24, 2009

Figure Top x-ref 19 ClK Rst Bus2WFIFO_Ch_Num[0:7] Bus2WFIFO_Burst Bus2WFIFO_Status_RdReq Bus2WFIFO_Data_WrReq WFIFO2Bus_Ack WFIFO2Bus_ErrAck WFIFO2Bus_Ch_Valid Bus2WFIFO_DBus[0:31] Bus2WFIFO_Tag[0:3] WFIFO2Bus_Status[0:31] 2WFIFO_Ch_Num[0:7] WFIFO2_Ch_Valid 2WFIFO_Burst 2WFIFO_RdReq WFIFO2_Ack WFIFO2_ErrAck WFIFO2_DBus[0:31] WFIFO2_Tag[0:3] WFIFO2_HalfEmpty WFIFO2_AlmostEmpty 89AB CDEF 1122 3344 5566 7788 9900 0 0 0 8 2004 E000 WFIFO2_Empty WFIFO2_Occupancy[0:7] cycle FB FC FD FE FF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DS471_19_1405 Figure 19: WFIFO Fixed Length Burst Write Timing With ACK Delay DS471 April 24, 2009 www.xilinx.com 25

Figure Top x-ref 20 Clk Rst Bus2WFIFO_Ch_Num[0:7] Bus2WFIFO_Burst Bus2WFIFO_Data_WrReq Bus2WFIFO_Status_RdReq WFIFO2Bus_Ack WFIFO2Bus_ErrAck WFIFO2Bus_Ch_Valid Bus2WFIFO_DBus[0:31] Bus2WFIFO_Tag[0:3] WFIFO2Bus_Status[0:31] 00FF 2WFIFO_Ch_Num[0:7] WFIFO2_Ch_Valid 2WFIFO_Burst 2WFIFO_RdReq WFIFO2_Ack WFIFO2_ErrAck WFIFO2_DBus[0:31] WFIFO2_Tag[0:3] 89AB CDEF 1122 3344 5566 7788 9900 0 0 0 8 WFIFO2_HalfEmpty WFIFO2_AlmostEmpty WFIFO2_Empty WFIFO2_Occupancy[0:7] cycle 04 03 02 00 1 2 3 4 5 6 7 8 9 10 11 DS471_20_1405 Figure 20: WFIFO Fixed Length Burst Read Timing With ACK Delay WFIFO Write Interface Operational Description Data to be transmitted by the IP core is transferred from the local bus interface logic to the data stream communications interface logic via the Write Channel FIFO (WFIFO). The input (write port) of the WFIFO is connected to the local bus interface side of the IP (Bus Interface). During a typical data transmit operation, the Bus Interface specifies a channel number (Bus2WFIFO_Ch_Num) to the WFIFO and then requests a status read from that channel by asserting Bus2WFIFO_ Status_RdReq. The WFIFO responds by loading the channel status information onto WFIFO2Bus_ Status and asserting WFIFO2Bus_Ack. If the channel is not full, the Bus Interface loads data into the write port of the WFIFO (Bus2WFIFO_DBus) and the tag information associated with the data into the tag port (Bus2WFIFO_Tag). The write to the WFIFO is initiated by asserting Bus2WFIFO_Data_WrReq. As mentioned earlier, during data transfers the state of Bus2WFIFO_Burst determines the length of the transfer. If Bus2WFIFO_Burst is deasserted when the data write request asserts, only one word will be transferred (WFIFO2Bus_Ack will assert for only one clock cycle), regardless of how long the request remains asserted. 26 www.xilinx.com DS471 April 24, 2009

If bursts are enabled (C_BUS_BURST_ SIZE is greater than zero) then, a burst transfer occurs when Bus2WFIFO_Data_WrReq asserts while Bus2WFIFO_Burst is asserted. The WFIFO will accept C_BUS_BURST_ SIZE number of words and then terminate the transfer (by deasserting WFIFO2Bus_Ack), regardless of the state of Bus2WFIFO_Data_WrReq and Bus2WFIFO_Burst. The write request must be deasserted and then reasserted to begin a new transfer. If the Bus Interface attempts to write data to a full channel, the WFIFO will assert an error acknowledge (WFIFO2Bus_ ErrAck) rather than the transfer acknowledge and the state of the channel will not change. Bus Interface Write Operation Example For this example assume both the Bus Interface and the Interface have channel 1 selected and the most recent context switch on either side has completed and both channel numbers are stable. The channel number is eight bits in width, reflecting the fact that there are 256 channels numbered from 0 to 255, and the discrete occupancy output is also eight bits wide, reflecting the fact that each channel can hold 255 (m 1) words. We will also assume that C_BUS_BURST_ SIZE is set to 4, no pipeline delays exist, and that no data transfers occur on the Interface side during this discussion. Figure Top x-ref 21 Clk Rst Bus2WFIFO_Ch_Num[0:7] Bus2WFIFO_Burst Bus2WFIFO_Status_RdReq Bus2WFIFO_Data_WrReq WFIFO2Bus_Ack WFIFO2Bus_ErrAck WFIFO2Bus_Ch_Valid Bus2WFIFO_DBus[0:31] Bus2WFIFO_Tag[0:3] WFIFO2Bus_Status[0:31] 2WFIFO_Ch_Num[0:7] WFIFO2_Ch_Valid 2WFIFO_Burst 2WFIFO_RdReq WFIFO2_Ack WFIFO2_ErrAck WFIFO2_DBus[0:31] WFIFO2_Tag[0:3] WFIFO2_HalfEmpty WFIFO2_AlmostEmpty WFIFO2_Empty 2000 0005 23 4567 89AB CDEF 1122 3344 5566 7788 9900 0 0 0 0 8 F 2000 0004 E000 55AA 55AA WFIFO2_Occupancy[0:7] cycle FA FB FC FD FE FF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 DS471_21_1405 Figure 21: WFIFO Write Timing DS471 April 24, 2009 www.xilinx.com 27

Referring to Figure 21, the Bus Interface issues a status read request in clock cycle 2 and the WFIFO responds in the same clock cycle with an acknowledge and the status, Because there is no context switch taking place, the status value returned is hexadecimal 2005. This value indicates that the channel is at least half full and that there are 5 empty locations remaining in the channel. Because the channel is not full, the Bus Interface places the data and tag information it wishes to write on the data bus and tag field, respectively, and asserts the data write request in clock cycle 3. Because Bus2WFIFO_Burst is deasserted, this is a single beat transfer. The WFIFO responds with an acknowledge in cycle 3, indicating that the data will be written at the end of that cycle. In cycle 5 the Bus Interface again asserts the status read request and the WFIFO responds with an ack and the status value of hexadecimal 2004, indicating that there is one less empty location remaining in the channel. Next, the Bus Interface asserts the burst signal along with the data write request and bursts four data words and their associated tag fields to the WFIFO. The WFIFO acknowledges the write request in the same clock cycle, and on each clock cycle thereafter, until four words have been transferred, at which time the acknowledge is deasserted. For this example, the end of the data to be transmitted occurs in the last word, and the last data word is only partially filled (zeros are used to pad in this example). Its associated tag field has the most significant bit set, indicating that the first byte in that data word contains the last valid byte of the data to be transmitted. 1 Finally, the Bus Interface asserts its status read request in clock cycle 13 and the WFIFO provides the status and the acknowledge signal in the same cycle. The status value contains hexadecimal E000, indicating that the channel is full, (at least) almost full, and (at least) half full, as well as there being no vacancies remaining in the channel. The discrete occupancy output on the Interface side (WFIFO2_ Occupancy) reflects this same condition, namely that there are 255 occupied locations in the channel, the maximum number of words it can hold. WFIFO Read Interface Operational Description The read port of the WFIFO is connected to the data stream communications interface logic ( Interface). The Interface selects the active read channel by providing a channel number on 2WFIFO_ Ch_Num and ensuring that the channel is valid (WFIFO2_ Ch_Valid is asserted). The read port is activated by the assertion of 2WFIFO_ RdReq. Like the bus side, the comm side of the WFIFO is also insensitive to pipeline delays associated to the request/acknowledge interaction. If 2WFIFO_ Burst is deasserted when the read request asserts, only a single word will be transferred regardless of how long the request remains asserted. If 2WFIFO_ Burst is asserted when the read request asserts, then a fixed length burst will be transferred. 1. Because the tag field is user definable, the user is free to define the tag bits in any manner they choose (see "WFIFO Tag Field" on page 33). For this example each bit in the tag field corresponds to a byte in the associated data word. The most significant bit in the tag corresponding to the most significant byte in the data, etc. The tag field will be all zeros for normal data words. For the last data word in a packet, the tag field will indicate which byte is the last byte in the packet. Pad bytes in the data, if necessary, will contain zeros. 28 www.xilinx.com DS471 April 24, 2009