Laboratory Exercise 3 Davide Rossi DEI University of Bologna AA 2017-2018
Objectives Summary of finite state machines (Mealy, Moore) Description of FSMs in System Verilog Design of control blocks based on FSMs Exercise: semaphore
Overview Finite State Machine Design Mealy Moore Implicit Explicit
FSM Models & Types Explicit Declares a state register that stores the FSM state May not be called state might be a counter! Implicit Describes state implicitly by using multiple event controls Moore Outputs depend on state only (synchronous) Mealy Outputs depend on inputs and state (asynchronous) Outputs can also be registered (synchronous)
Mealy & Moore FSMs (contd.) Mealy Machine Only Combinational Logic Sequential Logic Circuit Combinational Logic Next State Logic Next Present State FF s State Output Logic outputs CLK
Binary Encoded or One Hot Encoding Binary Encoded FSM (Highly Encoded) One Hot Encoding 110 S4 IDLE 000 S1 001 10000 S4 IDLE 00001 S1 00010 010 S3 S2 011 01000 S3 S2 00100
Binary Encoded or One Hot Encoding A binary-encoded FSM design only requires as many flip-flops as are needed to uniquely encode the number of states in the state machine. Number of FF if(log2(number of states) == integer) else required FF = log2(number of states) required FF = integer(log2(#states))+1;
Binary Encoded or One Hot Encoding A onehot FSM design requires a flip-flop for each state in the design and only one flip-flop (the flip-flop representing the current or "hot" state) is set at a time in a onehot FSM design. For a state machine with 9-16 states, a binary FSM only requires 4 flip-flops while a onehot FSM requires a flip-flop for each state in the design (9-16 flip-flops).
FSM Coding Goals The FSM coding style should be easily modified to change state encodings and FSM styles. The coding style should be compact. The coding style should be easy to code and understand. The coding style should facilitate debugging. The coding style should yield efficient synthesis results.
Two Always Block FSM Style (Good Style) One of the best Verilog coding styles is to code the FSM design using three always blocks: one for the sequential state register one for the combinational next-state onefor combinational output logic. Mealy Machine Only Combinational Logic Sequential Logic Circuit Combinational Logic Next State Logic Next Present State FF s State Output Logic outputs CLK
State Diagram S0 reset = 1 a = 0 b = 0 a = 1/ Z = 1 S1 Y=1 S2 b = 1/ Z = 1 Outputs Y and Z are 0, unless specified otherwise. We don t care about the value of b in S0, or the value of a in S1, or either a or b in S2. Is this Mealy or Moore?
State Diagram: Mealy! a = 0 b = x/ Y = 0, Z = 0 S0 a = 1 b = x/ Y = 0, Z = 1 a = x b = 0/ Y = 1, Z = 0 S1 Outputs Y and Z are 0, unless specified otherwise. We don t care about the value of b in S0, or the value of a in S1, or either a or b in S2. reset = 1 ab = xx/ YZ = 00 S2 a = x b = 1/ Y = 1, Z = 1 Is this Mealy or Moore?
Mealy FSM Inputs Next State and Output Logic Outputs State Register Current State FF
Mealy Verilog Part 1 module fsm_mealy ( input logic clk, input logic reset, input logic a, input logic b, output logic Y, output logic Z); enum { S0, S1, S2 } state, next_state; always_ff@(posedge clk) begin if (reset) state <= S0; else state <= next_state; end //continued on next slide
Mealy Verilog Part 2 // next state & output logic always_comb begin Y = 0; Z = 0; case (state) S0: if (a) begin next_state = S1; Z = 1; end else next_state = S0; S1: begin Y = 1; if (b) begin next_state = S2; Z = 1; end else next_state = S1; end S2: next_state = S0; default: begin next_state = S0; Y = 1 b1; Z = 1 b1; end endcase endmodule
Moore FSM Inputs Next State Logic Output Logic Outputs State Register Current State FF Next State
State Diagram: Moore a = 0 b = 0 Outputs Y and Z are 0, unless specified otherwise. S0 a = 1 S1 Y=1 If an input isn t listed for a transition, we don t care about its value for that transition reset = 1 b = 1 S2 Z=1
Moore Verilog Part 1 module fsm_moore ( input logic clk, input logic reset, input logic a, input logic b, output logic Y, output logic Z ); always_ff@(posedge clk) begin if (reset) state <= S0; else state <= next_state; end //continued on next slide
Moore Verilog Part 2 //next state & output logic always@(state or a or b) case (state) S0: if (a) next_state = S1; else next_state = S0; S1: Y = 1; if (b) next_state = S2; else next_state = S1; S2: Z = 1; next_state = S0; default: next_state = S0; endcase endmodule
Exercise Desig, using SystemVerilog hardware description language, a digital circuit implementing the functionality of a controller for a beverage dispensing machine. The IO interface of the digital circuit is the following: module vending ( input logic input logic input logic input logic output logic ); clk, rstn, dime, niche, out endmodule The dispensing machine only accepts 5 cents (nichel) and 10 cents (dime) coins. Once the amount of 15 cents is reached the machine activates a signal to enable the release of the beverage (output). The machine does not give back change. It is not allowed to insert more than one coin for a given clock cycle.